Commit Graph

15966 Commits

Author SHA1 Message Date
Konstantin Aladyshev 3c47e8a782 intel/gma: Return success for Intel int15 VGA set panel type hook
One of the interrupts in intel_vga_int15_handler lacks
positive return status. Write correct status to avoid
error messages in log.

TEST=With this change `int15 call returned error` is not shown anymore
     on a custom board with Intel Atom CPU, i945GME northbridge and
     i82801gx southbridge.

Change-Id: I740b2df9bd6a7d261d89bef74b924edbb64354aa
Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru>
Reviewed-on: http://review.coreboot.org/12255
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-31 21:39:02 +01:00
Patrick Georgi ee0028da3b util/scripts/no-fsf-addresses.sh: Strip last paragraph
checkpatch.pl that we inherited from Linux checks for its absence, so it
may be easiest to follow their style of not caring for the FSF's address
anymore.

TEST=visual check that `git diff` and `git diff |grep "^[+-]" | \
grep -v "^--- " |grep -v "^+++ " |sort | uniq -c  |sort -n` look
reasonable (matching number of removed and added comment terminators */,
etc.).
Also, `git grep -A3 "You should have received a copy"` only
returns license texts, imported files, patches and help strings in
applications as remaining copies of that paragraph

Change-Id: I7c43860b6fd7ec526983c24b608994539128cfb9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11887
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-31 21:38:15 +01:00
Patrick Georgi a73b93157f tree: drop last paragraph of GPL copyright header
It encourages users from writing to the FSF without giving an address.
Linux also prefers to drop that and their checkpatch.pl (that we
imported) looks out for that.

This is the result of util/scripts/no-fsf-addresses.sh with no further
editing.

Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11888
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-31 21:37:39 +01:00
Timothy Pearson 74b13a5616 mainboard/asus/kfsn4-dre_k8: Fix broken dual CPU package support
The existing KFSN4-DRE support hung during ramstage while initializing
AP #3 if a second CPU package was installed.  After analyzing the
Sun Ultra 40 M2 support code it became apparent that the K8 code
cannot function correctly if sequential RAM training is disabled,
and that there were a few other missing calls.  This patch adds
the missing calls, adjust the CAR space to an appropriate level, and
explicitly defines the link numbers and connections in devicetree.cb

TEST: Booted ASUS KFSN4-DRE with 2x Opteron 8222 installed.

Change-Id: I96178b7367b0c13de5c9d5d90d032fb0c53639c2
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12285
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-10-31 21:29:40 +01:00
Patrick Georgi ab355750fc arch/x86: avoid race condition on build.h
Change-Id: I15375ac1247b7cc8d80d910a767c7f3e67eb8739
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11904
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-10-31 19:23:47 +01:00
Nico Huber 0ace013523 sandybridge: Disable parallel CPU initialization
Disable the parallel CPU initialization for model_206ax, that is Sandy
Bridge and Ivy Bridge processors. We never did it the way that Intel
recommends and it became unreliable with the introduction of SMM_MODULES
in commit a3e41c0 Migrate 206ax to SMM_MODULES.

Tested by booting kontron/ktqm77 2.6k times into Linux user space. No
issues so far.

Change-Id: Idffc352341419f22a36bf772534a5e11e711edf1
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/12266
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-31 14:22:12 +01:00
Patrick Georgi 172a14de8e cbfstool: avoid naming variables "index"
Those may collide with strings.h's index(), included transitively
through system headers.

Change-Id: I6b03236844509ea85cfcdc0a37acf1df97d4c5f3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/12279
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-10-31 08:31:23 +01:00
Stefan Reinauer f7613ecacc cpu: port amd/pi to 64bit
Change-Id: I66ef081fa1a520f0199366587800783ea1ef8719
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11023
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2015-10-30 23:08:05 +01:00
Stefan Reinauer 42444f6f53 Drop SuperIO nuvoton/nct6779d
All boards using this SuperIO have been removed from the tree already.

Change-Id: I57eacf2a88077d0d0bffdcf44b3c2ecbd301e625
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12242
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 18:54:28 +01:00
Stefan Reinauer a57ad8f2ab Drop SuperIO ite/it8661f
All boards using this SuperIO have been removed from the tree already.

Change-Id: Ifca91ae44ab222371808ff1e0027a7cbd4646b0a
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12243
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 18:53:49 +01:00
Stefan Reinauer 53552cc08c Drop SuperIO nuvoton/nct6776
All boards using this SuperIO have been removed from the tree already.

Change-Id: Ic5604c75de249b945dca58aa904edec86558d3ec
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12241
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 18:53:37 +01:00
Stefan Reinauer 6c4ea738ff Drop SuperIO nsc/pc97307
All boards using this SuperIO have been removed already.

Change-Id: I667a8d15a2d16671115f62de656b1c5c6a8259b9
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12240
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 18:53:29 +01:00
Stefan Reinauer 0cca93162f Drop SuperIO nsc/pc8374
All boards using this SuperIO have been removed from the tree.

Change-Id: I1d13ec7c5f27e82523612af7f07fca3176953600
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12239
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 18:53:24 +01:00
Stefan Reinauer 3e6ba4dacc Drop southbridge intel/esb6300
All mainboards using this southbridge have been removed from
the tree already.

Change-Id: I4398ef1e270bd0f36c5dd1c6ec3bfec6c2c091e6
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12238
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 18:53:19 +01:00
Stefan Reinauer 3efcd2eeee Drop southbridge intel/i82801cx
All boards using this southbridge have been removed from
the tree already.

Change-Id: I08269931d845d1f57b34174238bcce245ad77894
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12237
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 18:53:13 +01:00
Stefan Reinauer 31ff120a2c Drop northbridge/i440lx
All boards using it have been deleted a long time ago.

Change-Id: Ib1c4018ab6ec27868c0e2fdbf9c91323ead076fb
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12236
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 18:53:08 +01:00
Stefan Reinauer ac901e6bed wakeup: Switch back to 32bit mode first
On x86_64 we need to leave long mode before we can switch to 16bit
mode. Oh joy! When's my 64bit resume pointer coming?

Why didn't this get caught earlier? Seems the Asrock E350M2 didn't
do Suspend/Resume?

Yes, I know it's Intel syntax. Will be converted to AT&T syntax
as soon as the whole thing actually works.. 8)

Change-Id: Ic51869cf67d842041f8842cd9964d72a024c335f
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11106
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 18:52:45 +01:00
Stefan Reinauer f79d05b778 Drop geode_post_code.h
It's unused and empty.

Change-Id: Ieb9225083cb779b7b94ca47488dad4d7beb30a94
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12235
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 18:52:13 +01:00
Stefan Reinauer 01327d185b smm: 64bit fixes
Change-Id: I35dab4e66514948aafa912d993fb8d42c5a520a0
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11089
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 18:39:37 +01:00
Stefan Reinauer 16643aa686 Drop unused code from gcc-intrin.h
Change-Id: I3df66320d0bc18221f947b47e7f09533daafabad
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11108
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 18:39:03 +01:00
Stefan Reinauer dd132a5d2d AMD mainboards: Fix 64bit BiosCallOuts.c
Change-Id: I0f3297dff47dfb44da034ac6f305dcf1981b9de1
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11080
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 18:31:35 +01:00
Stefan Reinauer 5fa4cb6d32 cpu/amd: Fix cbtypes.h to match UINTN convention
There are some inconsistencies in AMDs APIs between the coreboot
code and the vendorcode code. Unify the API.

UINTN maps to uintptr_t in UEFI land. Do the same
here. Also switch the other UEFI types to map to
fixed size types.

Change-Id: Ib46893c7cd5368eae43e9cda30eed7398867ac5b
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-on: http://review.coreboot.org/10601
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 18:24:39 +01:00
Stefan Reinauer d91ddc8d31 vendorcode/amd: 64bit fixes
Change-Id: I6a0752cf0c0e484e670acca97c4991b5578845fb
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11081
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 18:24:07 +01:00
Stefan Reinauer 772029fe73 More Hudson 64bit fixes
Change-Id: I2a6cd7ad27cb6d16dfe3267ea6fb844a5e2e20c6
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11083
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 18:23:52 +01:00
Stefan Reinauer 0390cc6b3a SB900 64bit fixes
Change-Id: I5ea0f9338ccdd658b5fbec72aa35b4f80d63d4f9
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11084
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 18:20:43 +01:00
Stefan Reinauer a843211481 SB700: 64bit fixes
Change-Id: Ib4b643441a5b887abf73cc55930ea9b01037f6ea
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11085
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 18:20:26 +01:00
Stefan Reinauer 6a2df9a5e8 RD890: 64bit fixes
Change-Id: I326c070398c72a877054969d3a03e6e427edc304
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11086
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 18:20:11 +01:00
Timothy Pearson 59d0e040c8 northbridge/amd/amdmct/mct_ddr3: Add initial Suspend to RAM (S3) support
Change-Id: Ic97567851fa40295bc21cefd7537407b99d71709
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11952
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 18:19:37 +01:00
Timothy Pearson 4ea0cc087e northbridge/amd/amdfam10: Add Suspend to RAM (S3) Flash data storage area
Change-Id: I169fafc3a61e11c3e4781190053e57bf34502d7b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11951
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-10-30 18:19:11 +01:00
Stefan Reinauer fce128cdfb Hudson: Port to 64bit
Bring http://review.coreboot.org/#/c/10582/ to Hudson

Change-Id: I1ba3047699c304a769215fe901dc3511bf23199d
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11022
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 18:16:28 +01:00
Stefan Reinauer 77a1d1adae Port AGESA based northbridge code to 64bit
This is extending http://review.coreboot.org/#/c/10583/
(29e6548) to the remaining AGESA northbridge drivers.

Change-Id: I6fa53b36a1420e92cb4aecb0f7b4c71541a94c71
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11021
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 18:15:15 +01:00
Stefan Reinauer 273911cfd6 mainboard 64bit fixes
Change-Id: I2b4338927d56a2075c0a95f2ab981f1beaf69cc7
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11082
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 18:13:53 +01:00
Timothy Pearson 5c5c4a6943 cpu/amd/model_fxx: Clear out unused / stale MTRRs in ramstage
This mirrors a similar commit made to Family 10h support
in changeset 11966 file model_10xxx_init.c

TEST: Booted ASS KFSN4-DRE with 1x Opteron 8222

Change-Id: I760ef27be00aed11c0ac21b9bd741189f4b05834
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12250
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-30 17:44:10 +01:00
Timothy Pearson e3b5d36321 cpu/amd/model_fxx: Enable FIDVID code on Socket F K8
The existing Kconfig option for FIDVID was permanently
set to "no" due to Kconfig stopping at the first matching
value set when parsing the file.  This patch moves the
conditional set above the unconditional set, resolving
the issue.

Change-Id: Ic19f68f6b17943f9133ff32a9b6538f0bf942eca
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12224
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-30 17:44:02 +01:00
Timothy Pearson 6b171b3163 cpu/amd/model_fxx: Backport APIC code and debug aids from Family 10h
Backport a handful of debugging routines and the extended APIC
initialization code from Family 10h support to K8 support.

Change-Id: I08cc5c8bc65635ce09a69e32940dd7edd8d3be87
TEST: Booted ASUS KFSN4-DRE with 1x Opteron 8222
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12251
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 16:33:46 +01:00
Timothy Pearson e67d240444 cpu/amd/car: Honor BKDG recommendations for DisFillP in CAR
The recommendation to set DisFillP during CAR initialization
on K8 NPT CPUs was ignored.  The consequences of this are
largely unknown; fix up coreboot to follow the recommendations.

Change-Id: Ide512bbc1d9aa284179628e2aa598ef5475e8eeb
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12249
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 16:32:51 +01:00
Timothy Pearson 2caf3cbac0 mainboard/asus/m2n-e|msi/ms9282: Clean up FIDVID mistakes
These two mainboards contained trivial mistakes related
to FIDVID that broke build when FIDVID was enabled.

Change-Id: Ie7bec77f26ec37eada21308984db4a9fd7a1866f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12226
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 16:08:05 +01:00
Timothy Pearson 56699948b7 southbridge/nvidia/ck804: Fix FIDVID build failure on CK804
Change-Id: I74c285ff86993898e0120170cf07f48ef4dc9612
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12225
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 16:07:04 +01:00
Timothy Pearson c6cd5d4ed5 cpu/amd/model_fxx: Fix invalid P-state power values
Change-Id: Ifdb1d1f267af289d962effe1150c7bc0a39cb5d2
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12233
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-30 16:01:45 +01:00
Timothy Pearson ab95702f1e mainboard: Add initial K8-compatible version of the KFSN4-DRE
This is a clone of the original Family 10h-compatible ASUS
KFSN4-DRE board, modified for basic K8 support to allow for
future K8 Socket F Opteron testing.

TEST: Booted KFSN4-DRE with 1 Opteron 8222 processor

KNOWN ISSUES:
 * Second CPU package fails to initialize AP
   This prevents use of a secondary CPU package
 * Second memory channel of at least CPU package #0
   does not function (crash at CAR handoff)

Change-Id: I591725babe685fa50a0d7473b17005fbd258056e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12212
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 16:01:13 +01:00
Timothy Pearson 529fd81f64 cpu/amd/model_fxx: Add Socket F CPU ID mappings
Change-Id: If1df7f3ae9661fae49557c07def397b36b1d38f0
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12210
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 16:00:57 +01:00
Kyösti Mälkki 439a527014 Revert "device/pciexp_device: Tune PCIe bridges before scanning children"
This reverts commit 785b3eb6e8.

The commit re-tuned the upstream link again, it does not tune secondary side.

Change-Id: I9be70e95b06ceff99beba8a7c7eb6402b32fcca1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/12253
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2015-10-30 00:36:07 +01:00
Douglas Anderson 6db10452b4 rockchip/rk3288: If we fail to read the EDID 5 times in a row, it's an error
Previously if we tried to read the HDMI EDID several times and failed
each time then we're return from hdmi_read_edid() with no error.  Then
we'd interpret whatever happened to be in memory at the time as an
EDID--not so great.

Let's actually look at the error.

BRANCH=none
BUG=chrome-os-partner:46256
TEST=Monitor that can't read EDID not shows that in the log

Change-Id: I6e64b13ae3f8c61bf1baaa1cfc8b24987bd75cf3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 44bda7311f9ee677235e4dc8db669226518b3895
Original-Change-Id: I9089755b75118499bec37bdb96d1635f66252e65
Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/309298
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/12231
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-29 21:07:19 +01:00
Shawn Nematbakhsh 5ece96a00f util/cbmem: Handle EC_VBOOT_DONE timestamp
This timestamp marks that EC verification has completed.

BUG=chromium:537269
TEST=Run cbmem on glados, verify "1030:finished EC verification" is
seen.
BRANCH=None

Change-Id: I0114febae689584ec8b12c169e70f2d3995d8d4d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: deeb2ab8085e5ea0a180633eb8fb1c86aadffe94
Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Change-Id: I4f09e970ffedc967c82e6283973cbbcb2fbe037f
Original-Reviewed-on: https://chromium-review.googlesource.com/309280
Original-Commit-Ready: Shawn N <shawnn@chromium.org>
Original-Tested-by: Shawn N <shawnn@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/12230
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Tested-by: build bot (Jenkins)
2015-10-29 21:07:08 +01:00
Julius Werner 8db7e6702b libpayload: usbmsc: Add small delay during initialization to fix CZ60
We found that some SanDisk Cruizer Glide CZ60 sticks (confirmed on 16GB
and 64GB versions) have a problem responding to our first GET_MAX_LUNS
request right after they received their SET_CONFIGURATION. They will
continually return a NAK until the host gives up (which is 2
user-noticable seconds for us). Adding a small delay of about 15us seems
to be enough to fix the issue, but let's do 50 to be save.

Confirmed with both MT8173 and Intel LynxPoint XHCI controllers.

BRANCH=None
BUG=chrome-os-partner:45473
TEST=No notable delay before detecting stick on Oak and Falco.

Change-Id: Ib03944d6484de0ccecbb9922d22666f54c9d53dd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 589f19a901275fb8b00de4595763a7d577bed524
Original-Change-Id: I95c79fe40d3ad79f37ce2eb586836e5de55be454
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/308980
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/12229
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-29 21:06:45 +01:00
Patrick Georgi 564fbbeac9 libpayload: Fix building dwc2 UDC driver
Change Ie54699162 changed a structure's name and field names and we
didn't notice. Adapt.

BUG=none
BRANCH=none
TEST=building with UDC_DWC2 works

Change-Id: I592ebc29b2a08a23e6dbc9d2186807cbbbbca330
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3dda8ad5ffc36593d8b8fd6664a7f9b4816f0f93
Original-Change-Id: I4a065de0f4045a01bef1dc9fbb2e0578b5508518
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/308791
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/12228
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-10-29 21:06:38 +01:00
Timothy Pearson 919d9ba633 mainboard/asus/kgpe-d16: Add nvram option to enable/disable IEEE 1394
Change-Id: I4f0f6c1cb1fad5b65f196dc6b443252a0ecc70a1
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11947
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-10-29 20:21:57 +01:00
Patrick Georgi 8f5053c626 util/fuzz-tests: Add fuzzer for jpeg decoder
Mostly a proof of concept for adding fuzzing to our tree.

Change-Id: I10e5ef3a426b9c74c288d7232a6d11a1ca59833b
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/12183
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-10-29 19:00:42 +01:00
Aaron Durbin 5907eb8f5a commonlib/region: add xlate_region_device
There are cases where one region_device needs to be
accessed using offset/sizes from one address space
that need the offset translated into a different
address space for operations to take place. The
xlate_region_device provides an offset that is
subtracted from the incoming transaction before
deferring to the backing access region.

Change-Id: I41d43924bb6fbc7b4d3681877543209e1085e15c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12227
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-10-29 18:58:07 +01:00
Patrick Rudolph e11f6c3be1 nb/intel/sandybridge/gma: add disable function
Issue observed:
In a multi GPU setup (IGD and PEG) the system still uses the IGD.
CONFIG_ONBOARD_VGA_IS_PRIMARY has no effect on Sandy/Ivy Bridge.

Test system:
* Gigabyte GA-B75M-D3H
* Intel Pentium CPU G2130
* ATI Radeon HD4780

Problem description:
The GMA is missing a disable function.

Problem solution:
Add a GMA disable function. Deactivate PCI device until remaining multi
GPU issues are resolved. Do not claim VGA decode any more.

Final testing results:
The system is able to boot using the PEG device as primary VGA
device.

Change-Id: I52af32df41ca22f808b119f3a4099849c74068b3
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: http://review.coreboot.org/11919
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-10-29 17:08:48 +01:00