Commit Graph

46862 Commits

Author SHA1 Message Date
Sergii Dmytruk 206328d57b lib/device_tree.c: zero-initialize new DT nodes
Prevents bad things from happening later when these new nodes are used.

This issue is hard to observe because:
 1. Heap is zero-initialized, so you need to use allocated memory
    filling it with non-zero values, free, allocate it again, use
    uninitialized.
 2. Most of allocated memory is not freed.
 3. Implementation of free() does something only for one last malloc'ed
    block, making most of freed memory unavailable for future
    allocation.

Change-Id: I38a7ec1949d80f7a2564fac380ce94de6056a0c7
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62928
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-22 20:45:26 +00:00
Tim Wawrzynczak 9ad63e4460 mb/google/brya/var/moli: Fix overridetree
Commit 5a0ad1186 missed one chip config member that got converted to
snake case in commit 215a97ee1.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ie92106f0fee0bb18863b7063c07673e0f7995c74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63005
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Martin L Roth <martinroth@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-22 20:36:25 +00:00
Tim Wawrzynczak ec5a5cc292 drivers/tpm/cr50: Use cr50_get_firmware_version in get_board_cfg
cr50_get_board_cfg() may be called in ramstage for some mainboards in
order to determine the BOARD_CFG register's value. The code was
written assuming that the firmware version was already retrieved, but
for boards calling this in ramstage, this is not the case. Therefore,
instead of using the cached cr50_firmware_version (which is all 0s in
ramstage at that time), use the cr50_get_firmware_version function
instead.

BUG=b:225206079, b:220685274
BRANCH=firmware-brya-14505.B
TEST=boot on brya0 and see:
[INFO ]  Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.6.93/cr50_v3.94
[INFO ]  Enabling GPIO PM b/c CR50 has long IRQ pulse support
in the logs.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ia6e5f4965a8852793d2f95e6eb21ea87860335a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-03-22 20:02:20 +00:00
Raihow Shi 5a0ad11868 mb/google/brask/variants/moli: init overridetree for moli
init overridetree.cb based on the schematic adl_rfq_mb_20220310.pdf

BUG=b:220814038

Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I8829d4b39d48ae574eeccbfc62e79b671211ae2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-22 19:01:46 +00:00
Terry Chen f613ce0479 mb/google/brya/variants/crota: set up gpio
Set the GPIO configuration of crota by bernadino 14 adl-p 20220112.pdf

BUG=b:219891328

Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I164bc7a8b682eb8682f02b06708bc7c72a5c449a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-22 19:01:25 +00:00
Felix Held 390a28057c soc/amd/common: move FCH IOAPIC and HPET init from SMBUs to LPC device
Despite the SMBus device being function 0 of the FCH PCI device, the
MMIO resource of the FCH IOAPIC is on the LPC device which is function 3
of the same PCI device, so move the FCH IOAPIC initialization code to
the LPC device. Since the HPET was enabled in the same function, also
move it to the LPC device initialization.

TEST=On Mandolin both IOAPICs are still correctly detected by Linux.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I585afd463c1c00cd87ced0617e7802503c5deba5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58334
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-22 17:05:21 +00:00
Robert Zieba a6425f170c util/spd_tools: Add support for exclusive IDs
Currently memory parts that use the same SPD are assigned the same ID by
spd_tools. This commit adds support for exclusive IDs. When given an
exclusive ID a memory part will not share its ID with other parts unless
they also have the same exclusive ID.

BUG=b:225161910
TEST=Ran part_id_gen and checked that exclusive IDs work correctly and
that the current behavior still works in their abscence.

Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: Ife5afe32337f69bc06451ce16238c7a83bc983c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-22 16:17:06 +00:00
Dtrain Hsu 5d3b1bbce4 mb/google/brya/var/kinox: Modify DDR4 to non-interleaved
Kinox is designed to 8-layer PCB. In order to reduce the length of
memory singals, the DDR4 is designed from interleaved to
non-interleaved.

BUG=b:210094309
TEST=emerge-brask coreboot

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I03c6fcccf8b1646cec1a35cc1f9cbb1cfb942c4e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-22 15:21:26 +00:00
Kevin Chang 1f54599b98 mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s
GL9763e doesn’t support L0s state, so disable L0s at the root port.

BUG=b:220079865
TEST=Build FW and run stress exceed 2500 cycles.

Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I6ed790c833d1c01a30aed0fd09cac260a3837ead
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
2022-03-22 05:04:50 +00:00
Kevin Chang 6e52c1da4a soc/intel/{adl,common}: Add ASPM setting in pcie_rp_config
This change provides config for devicetree to control ASPM per port

BUG=b:220079865
TEST=Build FW and run stress exceed 2500 cycles on taeko.

Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I19b5f3dc8d95e153301d777492c921ce582ba988
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62919
Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Martin L Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-22 05:01:57 +00:00
Kevin Chang 4b1f25d82f mb/google/brya/var/taeko: Enable Genesys L1 max entry delay
The workaround causes the eMMC controller to not enter its L1 
during the boot process

BUG=b:220079865
TEST=Build FW and run stress exceed 2500 cycles.

Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I142a816611e204e6c8577d15b3f0a0e08251f848
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <martinroth@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
2022-03-22 03:46:59 +00:00
Ben Chuang 15854c9134 drivers/genesyslogic/gl9763e: Add set L1 entry delay to Max for GL9763E
Add an option to set L1 entry delay to Max for GL9763E. The L1 entry
delay will be changed to expected value by sdhci-pci-gli driver in
Linux v5.14.

BUG=b:220079865
TEST=build and verify the value of GL9763E's 0x8A4[28:19] register is
0x3FF.

Change-Id: I19d4dfb7b873d09ff30ad4d2d63b876047c21601
Signed-off-by: Ben Chuang <benchuanggli@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
Reviewed-by: Martin L Roth <martinroth@google.com>
2022-03-22 03:45:30 +00:00
Sean Rhodes e8c186cdef payloads/tianocore: Add missing CONFIG_
Add missing CONFIG_ to the Boot Timeout parameter.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I88f4aa0286a77f6c94b5e5ec97a0034ea7594b4f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62920
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-21 21:39:43 +00:00
Yu-Ping Wu 374e6b4080 mb/google: Remove unused cpu device
The cpu device listed in MediaTek platforms' devicetree.cb doesn't
actually do anything, except causing an error during device
initialization:

 CPU: 00 missing read_resources

Therefore, remove it from the devicetree.

BUG=b:224419346
TEST=emerge-corsola coreboot
TEST=Krabby booted up successfully
BRANCH=none

Change-Id: Ibf9f7cf65da6a0dd0a0e1f556d5772573ba3e930
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62805
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-21 20:40:18 +00:00
Bora Guvendik c79da5f211 util/cbmem: Keep original Total Time calculation when no negative timestamps
"Total time" calculation changed after CL 59555 to include
"1st timestamp" value in the calculation. This patch restores original
Total Time calculation where "1st timetamp" is subtracted from
"jumping to kernel". If pre CPU reset timestamps are added (negative
timestamps), "Total time" calculation still includes the pre-reset time
as expected.

1) Before https://review.coreboot.org/c/coreboot/+/59555:
   0:1st timestamp                                     225,897
1101:jumping to kernel                                 1,238,218 (16,316)

Total Time: 1,012,281

2) After https://review.coreboot.org/c/coreboot/+/59555:
   0:1st timestamp                                     225,897
1101:jumping to kernel                                 1,238,218 (16,316)

Total Time: 1,238,178

3) After this patch:
   0:1st timestamp                                     225,897 (0)
1101:jumping to kernel                                 1,238,218 (16,316)

Total Time: 1,012,281

BUG=none
TEST=Boot to OS, check cbmem -t on Redrix board

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I0442f796b03731df3b869aea32d40ed94cabdce0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-03-21 20:30:05 +00:00
Felix Held fc45b1b90b mb/amd/chausie: add APCB binaries if available
The APCB files that provide the firmware components running on the PSP
some mainboard-specific information like the DRAM interface
configuration. Those files aren't yet in the upstream 3rdparty/blobs
repository, so only add those files if they are present and print that
no APCB was added and the image won't boot if they aren't present.

TEST=Both cases behave as expected.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1e8621901741b8b0531fe134273b47e85911e19f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-03-21 17:22:26 +00:00
Nikolai Vyssotski 9f85958b7e mb/amd/chausie/chromeos.fmd: increase A/B RW section size to 4MB
To have enough space in the A/B RW sections, increase those sizes to 4
MByte and decrease the RO section size to 6 MByte to free up the space
needed for that.

Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib107fd05cfb0ef7de95425abcce6c82b88a9835d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-03-21 17:20:38 +00:00
Sean Rhodes 629f8c5da1 ec/starlabs/merlin: Don't store EC values on change
Since CB:62741, the EC values are backed up to the CMOS when entering
S3, S4 and S5. Consequently, they don't need to be stored when they're
changed.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: If0ea392afae4a4d3c605cdea3c5896fbff606215
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-21 16:57:54 +00:00
Sean Rhodes fbb46c5438 ec/starlabs/merlin: Always store EC values
The EC values will be changed when entering S3, S4 or S5, so move
the function that stores the current settings outside of logic
that restricts it to S4 or S5. This means the state isn't lost
when entering S3.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ia007a8ad9c08a309489e9f64f1ed311858bfcd10
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-21 16:57:37 +00:00
Zheng Bao 52a1898d44 amdfwtool: Check the length of matching string before accessing
If AB recovery is enabled and get a "Lx" in fw.cfg, wrong character
is got or access violation happens.

Change-Id: Ibd8ffe34fd44d860ec2115cd36117da7b02169cd
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-03-21 16:55:46 +00:00
Frank Wu 0c893d2624 mb/google/brya/var/banshee: Add WiFi SAR table
Add WiFi SAR table

BUG=b:225285426
TEST=emerge-brya chromeos-config chromeos-config-bsp-private
coreboot-private-files-baseboard-brya coreboot chromeos-bootimage
and checked SAR table can load by WiFi driver.

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I8fa833409bd69e080fda735c89015b9548252190
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-03-21 14:16:27 +00:00
John Zhao b1dd019de2 soc/intel/common: Add IOE P2SB for TCSS
Meteor Lake has the IOE Die for TCSS. This change adds the IOE P2SB
sideband access and exposes API for TCSS usage.

BUG=b:213574324
TEST=Build platforms coreboot images successfully.

Change-Id: I01f551b6e1f50ebdc1cef2ceee815a492030db19
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-03-21 14:16:07 +00:00
= 32d53c9df0 mb/google/zork/var/dirinboz: Add fw_config probe for ALC5682-VD & VS
ALC5682-VD/ALC5682I-VS load different kernel driver by different hid
name. Update hid name and machine_dev depending on the AUDIO_CODEC_SOURCE
field of fw_config. Define FW_CONFIG bits 36 - 37 (SSFC bits 4 - 5)
for codec selection.

ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"

BUG=b:211672259
BRANCH=firmware-zork-13434.B
TEST=ALC5682I-VS audio codec can work

Change-Id: Icd4321ec0a284e35511dd4b860a16506f54cf663
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-hsuan Hsu <yuhsuan@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-21 14:14:27 +00:00
= e204daa3e2 mb/google/zork/var/gumboz: Add fw_config probe for ALC5682-VD & VS
ALC5682-VD/ALC5682I-VS load different kernel driver by different hid
name. Update hid name and machine_dev depending on the AUDIO_CODEC_SOURCE
field of fw_config. Define FW_CONFIG bits 36 - 37 (SSFC bits 4 - 5)
for codec selection.

ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"

BUG=b:215292608
BRANCH=firmware-zork-13434.B
TEST=ALC5682I-VS audio codec can work

Change-Id: I0b0231a3ee9c0dad289ffd50607b3ae6201f56a0
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-hsuan Hsu <yuhsuan@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-21 14:13:56 +00:00
Robert Chen 977282f6ce mb/google/brya/vell: Move WWAN devices for vell
This was to merge PCIe ACPI code to WWAN device. Also, RTD3 devices are
add to overridetree.cb where WWAN is present for vell.

BUG=none
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot

Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Change-Id: If27abcf31ed948899bfaecbe8ef494fe8a80609b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-21 14:13:39 +00:00
Sridhar Siricilla d9beb7bc50 mb/google/brya: Deselect ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR
The patch deselects ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR Kconfig which
updates PMC settings in the IFD for Alder Lake A0 silicon.
As Alder Lake A0 is intermediate stepping, and the IFD is locked in the
production systems, so the Kconfig is deselected.

BUG=b:190588098
BRANCH=firmware-brya-14505.B
TEST=Build the coreboot for Gimble

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I81fe7c792dd82d9d547d318ebda55ee4a0f3ac96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-21 14:09:38 +00:00
Rex-BC Chen d6727ba972 mb/google/corsola: Revise power-on sequence of PS8640
Although the panel initializes fine and the fw recovery screen is
displayed without issues, the current power-on sequence of the
PS8640 violates the spec of the PS8640, which can be confirmed by
measuring it with an oscilloscope.

The sequence is:
- set VDD12 to be 1.2V
- set VDD33 to be 3.3V
- pull hign PD#
- pull down RST#
- delay 2ms
- pull high RST#
- delay more than 50ms (55ms for margin)
- pull down RST#
- delay more than 50ms (55ms for margin)
- pull high RST#

This flow will increase 110ms if firmware display is enabled in
krabby. For normal booting flow, the firmware will not be enabled,
so it will meet boot time requirements of Chrome OS. (Less than 1s.)

Datasheet name: PS8640_DS_V1.4_20200210.docx.
Chapter: 14.

BUG=b:222650141
TEST=show fw display normally in krabby.
TEST=result of waveform meets the spec.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I7706c56dc7fc13ac84c0d52a6e534bc0988e8fd3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-21 03:11:44 +00:00
Felix Held 5b51faaaea mb/google/skyrim/devicetree: set PSPP policy to DXIO_PSPP_DISABLED
Right now, the PSPP policy that controls if the PCIe lanes can be
dynamically downgraded to a lower speed to save some power needs to be
disabled in order for the link training to be successful. Once this
feature is working, PSPP will be reenabled.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6ea602596acb8e5ea92076386e80102c3bc757af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-03-19 18:27:05 +00:00
Felix Held b9ee6f351b mb/amd/chausie/devicetree: set PSPP policy to DXIO_PSPP_DISABLED
Right now, the PSPP policy that controls if the PCIe lanes can be
dynamically downgraded to a lower speed to save some power needs to be
disabled in order for the link training to be successful. Once this
feature is working, the PSPP policy will be switched to balanced again.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I85a06f322c4ddff25c3a858e2b79c84b36c48932
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-19 18:26:56 +00:00
Subrata Banik 7c477a9d1a soc/intel/common/block/p2sb: Add helper function to enable BAR
This patch creates a new helper function to enable P2SB BAR.

`p2sb_dev_enable_bar()` takes the PCI P2SB device address (B/D/F)
and BAR address (combining high and low base addresses).

BUG=b:224325352
TEST=Able to build and boot brya.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ica41e8e8bdfcfe855e730b3878b874070062ef93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2022-03-19 05:27:28 +00:00
Robert Chen 9b6e851e5b mb/google/dedede/var/lantis: Add ELAN touchscreen support for Landrid
The touchscreen slave address for landrid is 0x10 same as lantis, so we use SSFC to switch touchscreen controller.

BUG=b:222976965
TEST=emerge-dedede coreboot

Change-Id: I23d3de5e45aa2876c1590a1e09679d652a3f2906
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-19 01:44:15 +00:00
Felix Held e9172a14f9 mb/google/guybrush/port_descriptors: use enum values for link speed
Use GEN3 from enum dxio_link_speed_cap instead of the number 3.

TEST=Timeless build results in identical firmware image for guybrush

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0dddc57e05ec2395ca980bb63320bb9ee5242c29
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-18 23:09:21 +00:00
Subrata Banik 2bf9599cf1 vendorcode/intel/edk2/edk2-stable202111: Use fixed size struct elements
Fix the FSP headers and replace void pointers by fixed sized integers
depending on the used mode to compile the FSP.
Change request here:https://github.com/intel/FSP/issues/59

This is necessary to run on x86_64, as pointers have different size.
Add preprocessor error to warn that x86_64 FSP isn't supported by the
current code.

BUG=b:200113959
TEST=Verified on Meteor Lake platform, without any compilation error

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I1f33db43f7932cf6d165d0c70a0e2922dad00a09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-18 18:41:42 +00:00
Felix Held 79993d8be7 mb/google/brya/nivviks/overridetree: update tcss_aux_ori register name
Commit 215a97ee1c (soc/intel/adl/chip.h:
Convert all camel case variables to snake case) converted the camel case
used in the parameter name to snake case, but
commit bd529e2e20 (mb/google/nissa/var/
nivviks: Add TcssAuxori for nivviks) still used the old names which
breaks the upstream build. his patch is intended to be merged via
fast-path before the 24h are over to fix the tree.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2b9049553889c77bd8c59a2c4564d36d836a4eea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62927
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-18 17:55:56 +00:00
Rex-BC Chen bff1210f24 soc/mediatek/mt8186: Disable unused spm_thermal
In MT8186, we need to disable spm_thermal to prevent it from
influencing other wdt status.

There are two hardware pathes which are used for asserting watchdog
from thermal. We can disable status of path 1 because status of
path 2 is used.
1. Thermal -> SPM -> WDT
2. Thermal -> WDT

Spm_thermal (path 1) is a flexible option for software control, and
the hardware designer suggests that we should disable it if we don't
use it.

BUG=none
TEST=build pass

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I0ffde6bad3000a64e3b5782edaa72c62da034302
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62890
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-18 15:43:45 +00:00
Rex-BC Chen 1e24b20475 soc/mediatek: Trigger wdt SW reset when wdt status is not equal to 0
Because we close external signal in kernel driver since MT8195, it's
more reasonable to trigger sw reset with exteranl signal again
whenever the wdt status is not equal to 0.

BUG=none
TEST=build pass

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ic6128df7eadaebcf7ff8d4c5492e3e0cfbab6e36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62797
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-18 15:42:40 +00:00
Usha P bd529e2e20 mb/google/nissa/var/nivviks: Add TcssAuxori for nivviks
Enable SBU orientation handling by SoC for both USBC port0 and USBC
port1. Nivviks USBC port0 do not have retimer, USBC port1 has redriver,
but that do not flip the data lines. Hence we need to set bits for both
the USBC ports.

BRANCH:None
TEST=emerge-nissa coreboot chromeos-bootimage. Flash the image on
nivviks board and verified USBC display is working on both the ports in
normal and inverted connections.

Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I219de6092ac9a9c773adbaa99f5a7d6196a2c937
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62731
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-18 15:42:12 +00:00
Yu-Ping Wu 39e6f85ea2 soc/mediatek: Set soc_ops.set_resources as no-op
Without setting the set_resources field for soc_ops, we will get an
error during device initialization:

 [ERROR]  CPU_CLUSTER: 0 missing set_resources

Because the set_resources field is considered mandatory, explicitly set
it as no-op noop_set_resources.

BUG=b:224419346
TEST=emerge-corsola coreboot
TEST=Did not see the error on krabby
BRANCH=none

Change-Id: Ic82b86f0482a9de09e942c1674be5f0ac615851f
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2022-03-18 15:41:37 +00:00
Frank Wu 12cc10fe8b mb/google/brya/var/banshee: Replace amp max98357 with max98360
Based on the latest schematic, replace amp max98357 with max98360.

BUG=b:224692387, b:216110896
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Id265a4276c3f8b5553a0e5d7ed824b1d9a520d44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62887
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-18 15:41:00 +00:00
Frank Chu d402fdff5d mb/google/dedede/var/galtic: update Wifi SAR for for galnat
Add wifi sar for galnat/galnat360
Use SKU ID to load wifi table.

Each Project and SKU ID correspond as below
galtic (sku id:0x120000)
galith (sku id:0x130000)
galnat (sku id:0x140000)*
gallop (sku id:0x150000)
galtic360 (sku id:0x260000)
galith360 (sku id:0x270000)
galnat360 (sku id:0x2B0000)*

BUG=b:222008376
TEST=emerge-dedede coreboot chromeos-bootimage \
     coreboot-private-files-baseboard-dedede
     verify the SAR table is correct in each project

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I868a7416a002732736cabea48ce80548ea75e517
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-by: Ivan Chen <yulunchen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-18 15:40:44 +00:00
Xi Chen 0ca7aab760 commonlib/bsd: Add struct name "mem_chip_channel" for external access
struct mem_chip_info {
  ...
  struct { --> If no struct name, can't access the channel structure
    ...
  } channel[0];
};

BUG=b:182963902,b:177917361
TEST=Build pass on Kingler

Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com>
Change-Id: I8dcd3b52f33f80afb7885ffdcad826d86b54b543
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-18 15:40:26 +00:00
Ren Kuo 8df9cbb6ab mb/google/brya/var/volmar: Disable thunderbolt
Volmar does not support Thunderbolt, therefore disable all of the TBT
devices in the devicetree. The volmar fit image had been disabled already, cf. chrome-internal:4459289.

BUG=b:2233193
TEST=Build and run on DUT.

Change-Id: Ic1bba80707b1d4a97c486e22f79feccf6241865e
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-18 15:40:01 +00:00
Dtrain Hsu b24e45d215 mb/google/brya/var/kinox: Reconfigure GPIO settings
Configure GPIOs according to updated schematics.
- GPP_A21 from NC to TCP_DP1_CTRLCLK.
- GPP_A22 from NC to TCP_DP1_CTRLDATA.
- GPP_E22 from DDIA_DP_CTRLCLK to NC.
- GPP_E23 from DDIA_DP_CTRLDATA to NC.

BUG=b:214025396
TEST=emerge-brask coreboot

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I9d2d73820fbb191b682713e4e351c6375927ddf4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-18 15:39:47 +00:00
Cliff Huang 2b19d547c0 mb/intel/adlrvp: Set EPP to 45% for all Adl RVP variants
This sets EPP value to be 45% for all Adl RVP variants.

Historically, EPP Ratio has always been 50% (128) on Chrome platforms.
But on Intel Alderlake EPP ratio of 45% is recommended for optimal
power and performance on Chrome platforms.

TEST=
Use 'iotools rdmsr [cpu id] 0x774' command and check field 32:24 = 0x73.

Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: If83a2148d596efccd2e50cc82f1afcbfb9ebb935
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2022-03-18 15:39:33 +00:00
Shon Wang 8d296b1eba mb/google/brya/var/vell: Change AMP driver setting
1.Change I2S GPP_Sx (S0-S3) Native PAD Configuration from NF2 to NF4
2.Select CS35l53 AMP driver for Vell variant.

Change-Id: I96d49bd1a2ba061c4fd52b450b31d0885f49552c
Signed-off-by: Shon.Wang <shon.wang@quanta.corp-partner.google.com>
Signed-off-by: Vitaly Rodionov <vitaly.rodionov@cirrus.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-18 15:39:08 +00:00
Stefan Binding 7cd505873b drivers/i2c/cs35l53: Add driver for generating device in SSDT
This patch is adding support for Cirrus Logic CS35l41/CS35l53
smart amplifier. This part is now used in number of new chromebook's
HW designs by several vendors.

This driver uses the ACPI Device Property interface to generate
the required parameters into the _DSD table format expected by
the kernel. For detailed information about these properties, please
check Linux kernel documentation:
/Documentation/devicetree/bindings/sound/cirrus,cs35l41.yaml

Change-Id: I2cbb1cef89f8d56ee73fab06c68933a2ab8c3606
Signed-off-by: Stefan Binding <sbinding@opensource.cirrus.com>
Signed-off-by: Vitaly Rodionov <vitaly.rodionov@cirrus.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-18 15:38:21 +00:00
Karthikeyan Ramasubramanian 92dc7d2b4f mb/google/skyrim: Build APCB sources into amdfw when present
BUG=b:224618411
TEST=util/abuild/abuild -t GOOGLE_SKYRIM with and without APCB

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I71b30a5716f2e0d60d07a0ec29f98609c1f2a8b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-18 15:14:44 +00:00
Raul E Rangel 4fdcefc9f6 mb/google/skyrim: Fix I2C voltages
Needed so i2c communication works.

BUG=b:224618411
TEST=build skyrim

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8ec7c18cae509b5683cb73153fd6d3747cf9d753
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62874
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-18 15:10:48 +00:00
Raul E Rangel 7496392bd9 mb/google/skyrim: Enable tis_plat_irq_status
This will fix:
> [INFO ]  Probing TPM I2C: tis_plat_irq_status() not implemented, wasting 20ms to wait on Cr50!

BUG=b:224618411
TEST=Compile skyrim

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5add694506ad089adcc8961f101bf507bc39a522
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62873
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-18 15:10:39 +00:00
Nick Vaccaro 1abbb96c36 Revert "Revert "drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run serially""
This reverts a change that was causing hangs and exceptions during boot
on an ADL brya4es.

The hang (or APIC exception) occurs at what appears to be the FSP MP
initialization sequence, prior to the "Display FSP Version Info HOB"
log being displayed :

  [DEBUG]  Detected 10 core, 12 thread CPU.
  [DEBUG]  Display FSP Version Info HOB

This reverts commit 40ca79714a.

BUG=b:224873032
TEST=`emerge-brya coreboot chromeos-bootimage`, flash and verify brya4es
is able to successfully reboot 200 times without any issues.

Change-Id: I88c15a51c5d27fbd243478c923e75962d3f8d67d
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-18 07:24:04 +00:00