I also removed the unnecessary #include in soc.asl.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifbd79871fd49b18f45d97f64ccd68fa96eaaebce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50572
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With chipset_power_state filled in romstage CBMEM hooks and
GNVS allocated early in ramstage, GNVS wake source is now
also filled for normal boot path.
Change-Id: I2d44770392d14d2d6e22cc98df9d1751c8717ff3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
When USE_PSPSECUREOS isn't selected, we get stuck in FSP-S.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I60d0e5ab0bd9f4d76cc48d08ca05d27c60e898c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The number of data fabric MMIO registers is SoC-specific, so we need to
keep that in the SoC code. This also removes a redundant pair of
brackets and moves a loop counter declaration into the head of the loop.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8499f1c1f7bf6849b5955a463de2e06962d5de68
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50638
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The exact same mechanism is used on Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3179d8ec35efa29f9bc66854c3690b389d980bba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50619
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We also want to support uCode loading on cezanne.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6f10564c93ce72aea7ff52a8565d65d8b56452f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Stoneyridge used CONFIG_MAX_CPUS and CONFIG_MAX_CPUS + 1 directly as
IOAPIC IDs and Picasso had Kconfig options to configure that, but still
used the common SMBus controller code that used CONFIG_MAX_CPUS as ID
for the FCH IOAPIC. If a board overrides the PICASSO_FCH_IOAPIC_ID
Kconfig option to a value that isn't CONFIG_MAX_CPUS, we'll get a
mismatch between the ID that gets written into the FCH IOAPIC register
and the ID in the corresponding ACPI table. In order to avoid that add
defines to each SOC's southbridge.c and use them in all soc/amd code.
Change-Id: I94f54d3e6d284391ae6ecad00a76de18dcdd4669
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50575
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is another common ACPI setting.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iefecabae1d83996a9a4aaadd2a53c2432441e1b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50558
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is ACPI specific config that applies to all the AMD SoCs. Stoney
doesn't currently use this, but we can add that functionality later.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0be7d917d7c5ba71347aa646822a883e2cf55743
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50557
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is common between stoney, picasso, and cezanne.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5fb40e8c6817773212c5fbd66c5c06bd2bae1eda
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50556
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is common between all the chipsets.
It's also required by common/block/lpc/lpc.c.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I361dfabfe0c04667a2c112955133831a985d5cc0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The same functionality will eventually be needed on Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib49124c2c774ad3352ea2f7d8d827388029be041
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Since SMM is in TSEG on the platforms which is the default, drop the
SMM_TSEG condition for the default of SMM_TSEG_SIZE.
Change-Id: I7bd965c0794efa12ea4886a55522cc5193a1d3ac
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50498
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The corresponding bit is marked as reserved in the PPR. Also there's no
BKDG for Picasso any more; the BKDG was mostly replaced by the PPR. Also
fix the style of the comment.
Change-Id: Iffdbb9e951cb140e4352ab0f198f72a71ba798dc
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50495
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Variable PICM was not inside GNVS region and can use a static
initialisation value.
For most AMD platforms PICM default changes from 1 to 0.
Fix comments about PICM==0 used to indicate use of i8259 PIC for
interrupt delivery.
Change-Id: I525ef8353514ec32941c4d0c37cab38aa320cb20
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49905
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Initialize variable to 1 to indicate AC power supply.
If platform has EC it will set this correctly based on
whether plugged on the charger or not.
Change-Id: I3f834cf7563b9e512fcab34cdb7a27a9f0fd31c0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49352
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
signed int should only be used when we need negative values and in those
cases the value shouldn't became negative.
Change-Id: Iefac021260ff363c76bf5cd3fe3619ea1dbabdba
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50486
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The common code gets moved to soc/amd/common/block/cpu/smm, since it is
related to the CPU cores and soc/amd/common/block/smi is about the SMI/
SCI functionality in the FCH part. Also relocation_handler gets renamed
to smm_relocation_handler to keep it clear what it does, since it got
moved to another compilation unit.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I45224131dfd52247018c5ca19cb37c44062b03eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50462
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The old name was misleading, since it doesn't disable the generation of
SMIs, but clears the status registers.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iddadbec013091c2e5993a6303e291451c3d1e7ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50459
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The picasso SPI registers are different than the ones defined in
amdblocks/lpc.h. The BASE_ALIGNMENT has changed and the
PSP_SPI_MMIO_SEL bit has been added.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0b5a0c88c6dbb95cdbc62b949a7d30bfad1fa725
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
southbridge.c was renamed and split into early_fch.c and fch.c.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie439e746fb3dfe9ec865481a76a09eab378242bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50458
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Triggering SMI is not part of the semantics of global_smi_enable(), so
move it to the post_mp_init handler. Even without the !acpi_is_wakeup_s3
check we don't get PSP warnings/errors during resume, so we can drop the
workaround introduced in commit 5dbe45e0f5
in this patch.
Change-Id: Id0e7723c2bb9811f80fe36c38199a01445dc1d7d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42987
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 75f6ab35ff.
Reason for revert: The 5.4 Linux kernel is not configured for AMDI0030. This causes an issue where the WP pin is not recognized.
BUG=b:179320024
TEST=WP pin shows up properly in crossystem after reverting this change.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I0850fd085b5ee70522752633900f69d4d3732321
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50052
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The same functionality is needed on Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I40f9d2fe7d144e94369a417225bcca0a299d1f45
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
No PCI or PNP functions are used in here.
TEST=Timeless build results in identical image.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I577e2ecdc59dbd09e739ae800cbe021168a34812
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50399
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ACPI S3 is a global state and it is no longer needed to
pass it as a parameter.
Change-Id: Id0639a47ea65c210b9a79e6ca89cee819e7769b1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
We need the same functionality for cezanne.
TEST=Boot ezknil
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0800c662bb473eb571c74e76a8247298f534b53f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
add UPD for RV2 USB3 phy setting adjust.
Note: it only for RV2 silicon and not available for RV/PCO.
Usb 3.1 PHY Parameters:
1. RX_EQ_DELTA_IQ_OVRD_VAL
-Override value for rx_eq_delta_iq. Range 0-0xF
2. RX_EQ_DELTA_IQ_OVRD_EN
-Enable override value for rx_eq_delta_iq. Range 0-0x1
3. Override value for rx_vref_ctrl. Range 0 - 0x1F
4. Enable override value for rx_vref_ctrl. Range 0 - 0x1
5. Override value for tx_vboost_lvl: 0 - 0x7.
6. Enable override value for tx_vboost_lvl. Range: 0 - 0x1
7. Override value for rx_vref_ctrl. Range 0 - 0x1F
8. Enable override value for rx_vref_ctrl. Range 0 - 0x1
9. Override value for tx_vboost_lvl: 0 - 0x7.
10. Enable override value for tx_vboost_lvl. Range: 0 - 0x1
BUG=b:175192931
TEST=Build/verify the valule will been apply on dirinboz
Change-Id: I1d5f69e840952cc5171af1ce8597628d1bede5cb
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50240
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This was the only I/O base address in Kconfig, no board changed it and
if a board changed it, it needs to make sure that it won't overlap with
other I/O resources, so just use the same value as constant in the
define instead of the value from Kconfig. Also remove the PICASSO_
prefix from ACPI_IO_BASE.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7ea62f1101ddefa8785da92de5ba2aaf7945694a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Add new Kconfig symbols to mark FSP binary as x86_32.
Fix the FSP headers and replace void pointers by fixed sized integers
depending on the used mode to compile the FSP.
This issue has been reported here:
https://github.com/intel/FSP/issues/59
This is necessary to run on x86_64, as pointers have different size.
Add preprocessor error to warn that x86_64 FSP isn't supported by the
current code.
Tested on Intel Skylake. FSP-M no longer returns the error "Invalid
Parameter".
Change-Id: I6015005c4ee3fc2f361985cf8cff896bcefd04fb
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The `_MASK` macros should be using the corresponding `_SHIFT` macros.
Change-Id: I78370e17d2396f77ab820771f93cf15957bcf674
Found-by: Coverity CID 1445928
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Picasso has 32 configurable GPEs, not only 28.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia156e64e7a69764776f3af7597b680b8ddd4e650
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50244
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
