83b991afff
- O2, enums, and switch statements work in romcc
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- Support for compiling romcc on non x86 platforms
- new romc options -msse and -mmmx for specifying extra registers to use
- Bug fixes to device the device disable/enable framework and an amd8111 implementation
- Move the link specification to the chip specification instead of the path
- Allow specifying devices with internal bridges.
- Initial via epia support
- Opteron errata fixes
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1200 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-10-11 06:20:25 +00:00
be956f096f
size memory
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1192 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-10-05 05:13:12 +00:00
ccf4d34bb7
use standard name
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1191 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-10-05 05:12:56 +00:00
95ae7c1e5c
pci.S moved into arch/ppc/lib/pci_ops.c
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1190 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-10-05 05:11:52 +00:00
430111b9d1
It builds!
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1150 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-26 16:12:23 +00:00
aa4b4e031f
add cpufixup.o
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1149 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-26 15:55:11 +00:00
9b4457afb0
cpu fixup for p6
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1148 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-26 15:54:34 +00:00
481b5688b5
moved init_timer() to static initialization
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-03 21:30:18 +00:00
95bbf58b8c
missing file chip.h
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1071 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-08-05 13:43:18 +00:00
60e185fcc4
patches from Yh Lu. Tested and working on HDAMA
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1068 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-08-04 22:13:57 +00:00
a43048d371
Commits for the new config static device design, to allow more than one static
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cpu of a certain type and to eliminate the
cpu p5
cpu p6
cpu k7
nonsense in the old config files.
Next step is to hook into Eric's pci device stuff.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1067 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-08-04 21:05:19 +00:00
a265d5c0a0
- Update cpufixup so we support more than 4GB of memory
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1063 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-08-01 03:01:28 +00:00
57ffeb0578
updates from YhLu, plus fixes for PPC/K8 issues.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1059 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-30 03:05:20 +00:00
714caaea38
PPC 4XX support
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1056 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-28 21:21:03 +00:00
821730906b
corrected cpu path, added clock.o
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1048 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-28 21:11:26 +00:00
f7dd989955
*** empty log message ***
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1030 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-24 21:03:45 +00:00
99d0d7b300
getting HDAMA to build.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1005 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-23 01:45:47 +00:00
2c018fba95
- First pass at s2880 support.
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- SMP cleanups (remove SMP only use CONFIG_SMP)
- Minor tweaks to romcc to keep it from taking forever compiling
- failover fixes
- Get a good implementation of k8_cpufixup and sizeram for the opteron
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@998 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-21 20:13:45 +00:00
9b4336cf41
- Major cleanup of the bootpath
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- Changes to allow more code to be compiled both ways
- Working SMP support
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@987 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-19 04:28:22 +00:00
61b29a9b72
- Commit a binutils safe version of reset16.inc
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-16 01:58:18 +00:00
ae948f78e6
- Compile fixes
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@963 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-14 20:40:38 +00:00
655bf44cde
- Remove all of the annoying $Id strings
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@956 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-12 02:15:12 +00:00
58f74a2514
- Remove use of useless EXT macro
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@950 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-12 01:39:05 +00:00
57fa1b8279
- Code to enable and disable use of the sse and mmx registers
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@930 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-01 06:51:27 +00:00
1807c37418
Fixes to various config files.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@908 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-24 19:44:00 +00:00
99acb49cf7
added config and other test files.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@882 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-17 16:51:06 +00:00
8d9c123812
- Minor mod to reset16.inc to work with newer binutils hopefully this works with older ones...
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- Update apic.h to include the APIC_TASK_PRI register definition
- Update mptable.c to have a reasonable board OEM and productid
- Additional testfiles for romcc.
- Split out auto.c and early failover.c moving their generic bits elsewere
- Enable cache of the rom
- Fixes to amd8111_lpc.c so that we successfully setup virtual wire mode on the ioapic
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@880 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-17 08:42:17 +00:00
526855741b
- Cleanups on the romcc side including a pci interface that uses
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fewer registers, and is easier to hardcode.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@838 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-05-19 19:16:21 +00:00
8ca8d7665d
- Initial checkin of the freebios2 tree
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@784 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-04-22 19:02:15 +00:00
Eric Biederman