The PCI_INTR table is an Index/Data pair of I/O ports
0xC00 and 0xC01. This table is responsible for physically
routing IRQs to the PIC and IOAPIC. The settings given
in this table are chipset and mainboard dependent, so the
table values will reside in the mainboard.c file. This
allows for a system to uniquely set its IRQ routing.
The function to write the PCI_INTR table resides in
cimx_util.c because the indices into the table have
the same definitions for all SBx00 FCH chipsets.
The next piece is a function that will read the PCI_INTR
table and program the INT_LINE and INT_PIN registers in
PCI config space appropriately. This function will read
a devices' INT_PIN register, which is always hardcoded to
a value if it uses hardware interrupts. It then uses this
value, along with the device and function numbers to
determine an index into the PCI_INTR table. It will read
the table and program the corresponding value into the PCI
config space register 0x3C, INT_LINE. Finally, it will set
this IRQ number to LEVEL_TRIGGERED on the PIC because it is
a PCI device interrupt and the must be level triggered.
For example, the SB800 USB EHCI device 0:18.2 has an INT_PIN
value hardcoded to 2. This corresponds to PIN B. On the
Persimmon mainboard, I want the USB device to use IRQ 11. I
will program the PCI_INTR table at index 0x31 (this USB device
index) to 11. This function will then read the INT_PIN register,
read the PCI_INTR table, and then program the INT_LINE register
with the value it read. It will then set the IRQ on the PIC to
LEVEL_TRIGGERED by writing a 1 to I/O port 0x4D1 at bit position 4.
Also, the SB700 has slightly different register definitions than
the newer SB800 and SB900 so it needs its own set of #defines for
the pci_intr registers.
Only the Persimmon mainboard is adapted to this change as an
example for other mainboards.
Change-Id: I6de858289a17fa1e1abacf6328ea5099be74b1d6
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/5877
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
The PIC i8259.c file has a lot of #defines and function
definitions in it. I am moving these to the i8259.h file
and also adding a few functions to update the PIC IRQ mask
register. The PIC default configuration has all of its
interrupts masked off except for IRQ2. IRQ2 is where
the Slave PIC is cascaded from the Master PIC.
Change-Id: I78d505358c29fadbc184137a09120863ea1d5c13
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/5950
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
S3 resume is expected to work now, however the 3s delay and flash wear
is still there.
Change-Id: I7edbce7bcf9c2160099fd5e371562b1ec63d45d8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5971
Tested-by: build bot (Jenkins)
Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Without this change the IOAPIC memory window would collide
with PCI config space. This was tested on the hp/abm board.
Change-Id: I5dd53463961f75bab80a41dc7beff8d0434b24ae
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/5946
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The Kabini MMIO region was assigned a 256MB region at
0xA0000000. That location is below TOP_MEM and is getting
carved out of useable system memory which is not being
reclaimed above 4GB. This changes its size to 64MB and
moves it to 0xF8000000.
This was tested on the hp/abm and asrock/imb-a180 boards.
Change-Id: Ib226bc954311a3a2a15f182ab4618f4924e95a5b
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/5945
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This patch supports northbridges: 0x0150 0x0154 0x0158 0x015c as 3rd gen core.
Tested on 0x0150 (0x0154 previously only model).
Change-Id: I53a33d864494dd4ac1cb9e8330450f56001ed92c
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/5873
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The romstage of Nuvoton Super I/O chips (but not Nuvoton BMC chips)
is identical, so the early_serial.c file can be moved under
nuvoton/common.
The Nuvoton BMC chip WPCM450 is however left untouched.
Change-Id: I4663176c1003b24a49a9fe5f9ebd27a1963b5565
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/5909
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
1. Remove #include .c in romstage.
2. Make romstage component symbols linker-time.
3. Provide header guards and prototypes in superio romstage support.
4. Correct function type-signatures to be static/non-static where
appropriate, avoid 'pretend optimisations' by unnecessarily inlining
functions.
5. Separate out UART enable from various other PNP hard coding
Change-Id: I9b8dad7c02d802e97db73ddf2913d5c6bb33a419
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5916
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This GCC specific workaround of wrapping of libgcc runtime symbols with
gcc.c is not nessary with libcompiler-rt linkage.
Change-Id: I50a2bc99d97f68a2ad2b51a92ea0e7086bab35fe
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5812
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Rewrite smsc/smscsuperio romstage component to be more consistent and
provide header there-by removing #include's of early_serial.c's in
mainboard's.
Change-Id: I572e0c76422f09d4de88935a36c0a59e5350e6e0
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5915
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Following similar reasoning as commit:
d304331 superio/fintek/f81865f: Avoid .c includes
Avoid any mistaken future inclusion of early_serial.c in mainboard.c
code by providing symbols in romstage.
Change-Id: I9e763a7ad9de090e35acdcf4d6a280d8227c6015
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5508
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
These non-ROMCC boards #include the model specific w83977tf Super I/O
romstage component. The generic winbond_early_serial() function serves
well here to further tighten integration into the new Super I/O
framework and drop dependence on #include'ing .c files, leaving only
ROMCC boards.
Change-Id: Ib63c0f29f994c54e6112702506f288535799706c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5898
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
We have better written generic implementations of these functions
introduced in commit:
a7d14a1 ite/common: Introduce common watchdog and 3.3V VSB helpers
Change-Id: Ic93d78fce18c68d1d1bf3b537e8985a2532a8fcf
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5901
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Move samsung/stumpy board towards generic romstage component and away
from poorly written hard-coded model specific Super I/O component. This
is an incremental step towards getting obj-level abstraction between
board and Super I/O.
Change-Id: I358c5abef85c2ffa1b7178025cde8834a35b0a51
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5899
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The Base of Stolen Memory (BSM) register belongs to device 2,
function 0.
Change-Id: I2381f87ffaccb2f8034c160fc30c1d92f8b19402
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5922
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Seems boards with i945 had TSEG disabled so this had gone unnoticed.
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Change-Id: I6a00ea9121847ce2fede22538e1b53a870d761f1
Reviewed-on: http://review.coreboot.org/5892
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
TSEG appears in memory below graphics UMA region. Seems boards
with i945 had TSEG disabled, so the incorrect order did not make
a difference.
Change-Id: Ie293aab17b60b5f06a871a773cd42577c7dc7c7b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5891
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
The lock bit for UVSVC/LVSVC was set before both registers were programmed.
Change-Id: I000440db5c8dd2f260ebc1b69108b75621faf7b3
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5167
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Without it option ROM run results in just a black screen.
Change-Id: Id203f55ca0f02c290a3f40ac1ec7c5f23c5580bf
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5344
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
thinkpad_acpi checks that BIOS version matches some pattern.
Report version in this form.
Not cleaned up as the idea of this patch seems to be met with resistance.
Can make it Thinkpad-specific if the idea is accepted.
Change-Id: I15e33e87e7a7f42d6a06f12fb39b5172153af8a1
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4650
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Commit 40e936a1 [1]
util/board_status/board_status.sh: Save ROM contents in `cbfs.txt`
creates `cbfs.txt` in `${tmpdir}` but does not move it to the results
directory `${tmpdir}/${results}`. So move it to the correct place.
[1] http://review.coreboot.org/5867
Change-Id: Ibca691ccf72b56b6271a611d92deaed7d377773b
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5883
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Move towards the removal of the superio model specific xxx_serial_enable
implementation. Make remaining superio romstage parts link-time symbols
and fix corresponding mainboards to match.
The following mainboards remain unconverted as they are ROMCC:
- mainboard/supermicro/x6dai_g
- mainboard/supermicro/x6dhe_g
- mainboard/supermicro/x6dhr_ig
- mainboard/supermicro/x6dhr_ig2
and so block the final removal of w83627hf_serial_enable().
Special cases:
- mainboard/supermicro/h8qme_fam10: Provide local pnp_ sio func
Provide local superio pnp_ programming entry/exit functions as to avoid
making superio implementation global symbols. Although this is not the
proper/final solution, it does mitigate possible symbol collisions and
allow for continued superio refactorisation.
Change-Id: Iaefb25d77512503050cb38313ca90855ebb538ad
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5601
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Part 1/2: These are actually not necessary if Super I/O support is
properly utilized.
Change-Id: I39b621e582f8d0762276d29492c91dce500f0665
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5870
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Add a define for the register Base of Stolen Memory (BSM) and use it.
Change-Id: I5b1df4e088d88344fac8cd8d218e76b08a885f58
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5884
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
realpath and readlink can be used to do the same thing - in this case
we're turning path1/path2/../path3/path4 into path1/path3/path4 so
that the makefile's wildcard routine can evaluate it.
Debian derivatives don't seem to include realpath. (and even when it's
installed, it's not the gnu coreutils version.)
Change-Id: I0a80a1d9b563810bdf96aea9d5de79ce1cea457a
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/5793
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
Bay Trail-I Platform – Bayley Bay-I Customer Reference Board
The Bayley Bay CRB-I is a dual-channel DDR3L SO-DIMM non-ECC platform.
It is designed to support the Bay Trail-I SoC.
This implementation uses the Intel FSP (Vist the Intel FSP
website for details on FSP architecture and support).
This code does not currently support S3. All other features and IO
ports are functional. Booted on Ubuntu 14.04, Mint 16,
Fedora 20 with SeaBIOS payload. Memtest86, FWTS, and
other tests pass.
Notes:
- Generates a 2MB binary to be flashed to the upper 2MB of the ROM,
to preserve the existing Intel Flash Descriptor & TXE binary.
- Tested with B0 & B3 Baytrail I parts
Board support page will be updated on acceptance.
Change-Id: I80c836c7590f2dc25ec854e7a0bb939024cea600
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5792
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The PCI Specification states that devices that implement
a bridge and a secondary bus must swizzle (rotate) the
interrupt pins according to the table below:
Child Dev # Child PIN Parent PIN
0,4,8,12... A/B/C/D A/B/C/D
1,5,9,13... A/B/C/D B/C/D/A
2,6,10,14.. A/B/C/D C/D/A/B
3,7,11,15.. A/B/C/D D/A/B/C
Which is also described by this equation:
PIN_parent = (Pin_child + Dev_child) % 4
When a device is found and its bus number is greater than 0,
it is on a bridge and needs to be swizzled. Following the
string of parents up to the root bus and swizzling as we go
gives us the desired swizzling result. When BIOS_SPEW is
defined, it will print out each step of the swizzling process.
Change-Id: Icafeadd01983282c86e25f560c831c9482c74e68
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/5734
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Mike Loptien <mike.loptien@se-eng.com>
While similar to the Bay Trail-M/D code based on the MRC, there are
many differences as well:
- Obviously, uses the FSP instead of the MRC binaries.
- FSP does additional hardware setup, so coreboot doesn't need to.
- Different microcode & microcode loading method
- Uses the cache_as_ram.inc from the FSP Driver
- Various other changes in support of the FSP
Additional changes that don't have to to with the FSP vs MRC:
- Updated IRQ Routing
- Different FADT implementation.
This was validated with FSP:
BAYTRAIL_FSP_GOLD_002_10-JANUARY-2014.fd
SHA256: d29eefbb33454bd5314bfaa38fb055d592a757de7b348ed7096cd8c2d65908a5
MD5: 9360cd915f0d3e4116bbc782233d7b91
Change-Id: Iadadf8cd6cf444ba840e0f76d3aed7825cd7aee4
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5791
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
When going from a configuration with fast boot disabled to one with
it enabled, ENABLE_MRC_CACHE was not being enabled properly. This
forces it on with ENABLE_FSP_FAST_BOOT.
Change-Id: If7b6374e0c0a1d5403a50a1b0a958cea6f96cc88
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/5794
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The FSP clears the bit that tells us whether or not the RTC has lost
power when it sets up memory. Because of this, we need to initialize
the RTC in romstage instead of ramstage.
Change-Id: I158e4339fc539d32cfb2428042df6156d312a5f4
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5735
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Depreciate the model specific early_serial.c romstage component for this
Super I/O in favor of the recent generic winbond romstage framework.
Change-Id: I22775dc9b6341c8994d21591b7176abe4dd99911
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5724
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Depreciate the model specific early_serial.c romstage component for this
Super I/O in favor of the recent generic winbond romstage framework.
Convert dependent board to generic winbond serial init. Note the clock
function is actually invalid since it never enters into PNP config mode
to twiddle the register. Further, 48MHz is the default (page 9 of
data-sheet) and so romstage.c need not do anything to the clock rate
hence why it presumably works with this invalid function.
Change-Id: I4706a1446c1b391b8390ac0361700ce6f15b9206
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5725
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Vladimir Serbinenko