Configure the TPM IRQ GPIO for TGL (StarBook Mk V) so that the
hardware TPM can be used.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ife88075e70184b46e69f2e24c70b85ec254edd64
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60756
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Don't configure ESPI GPIOs as the default values are correct.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I052fbfccd075d19340d3e27ad0c62965c80badaf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth - Personal <martinroth@google.com>
Rework edkii makefile so that the various build options are
unified between CorebootPayloadPkg, uefipayload_202107 and
upstream.
This sets the project directory based on the git repository name
i.e. https://github.com/mrchromebox/edk2 becomes mrchomebox
Also builds to $(obj)/UEFIPAYLOAD.fd and allows using a commit
ID without a branch.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I3cc274e7385dd71c2aae315162cc48444b7eaa5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Martin Roth - Personal <martinroth@google.com>
The SoC-specific I2C code and header file have been verified some time
ago, but it seems that I forgot to remove the corresponding TODOs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifd162bda10e5993bc32db3a77588491397e3c19e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
CPUID_ALDERLAKE_N_A0 is ES. Add it to generate is_es = 1 in ACPI
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: Icc65c52a9dadebe4ebab3d0c30599eb0db38bc3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Using __fallthrough instead of a comment about the fall-through being
intentional should make clang stop complaining about intended fall-
through statements.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I940529be02e20c72f6e97b2cfa10f0dd8f7020b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Compiling vboot_check.c depends on fmap_config.h already being generated
so add this dependency.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1fe2b738d76ae16dee3e1ebdca512264303a481c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
On mc_apl2 the external RTC is connected to I2C bus 3. All other I2C bus
devices (16.0, 16.1 and 16.2) have been disabled as they are not used.
While coreboot can handle the case where a PCI device does not have
function 0 enabled but a later one (here function 3), Linux seems to
check for function 0 first and ignores the rest if function 0
is missing. So enable PCI device 16.0 in order to let Linux use 16.3
again.
Test=Boot into Linux and make sure that PCI device 16.0 and 16.3 are
visible and I2C attached RTC works properly.
Change-Id: I55a748b6de8128f4b26b908118feff9f06d3fb7c
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62215
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Modify function to set default audio codec HID
to be original setting 10EC5682.
BUG=b:204517112
BRANCH=volteer
TEST=ALC5682-VD/ALC5682I-VS audio codec can work
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Ic37e7e6757476f1d30bea31fcde4deebebd488a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Modify function to set default audio codec HID
to be original setting 10EC5682.
BUG=b:204523176
BRANCH=volteer
TEST=ALC5682-VD/ALC5682I-VS audio codec can work
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I36e35522aba2463124b7e6e7046b1a56758b534d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Modify function to set default audio codec HID
to be original setting 10EC5682.
BUG=b:218245715
BRANCH=volteer
TEST=ALC5682-VD/ALC5682I-VS audio codec can work
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I30a1fe2ef8d750616f6907f86a5329f035920504
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Change-Id: Ie9dbed7d6dd1e5f0c97d4a6cedea3d6bd7b000a2
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Change-Id: I69c4b3cdd2473655064d1329d5319cffdba2425a
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
The rom layout for A/B recovery:
EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A
0x4A -> PSP L2 B -> BIOS L2 B
The coreboot doesn't implement the AMD's A/B recovery. This is only
for the ROM layout. To save some flash space, the entire B section can
be eliminated.
To enable A/B recovery in PSP layout, add "--recovery-ab" to
amdfwtool.
TEST=Majolica(Cezanne)
Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add the information of substance and instance in the string for PMUI
and PMUD. It is amdfwtool's job to extract the number from the string.
Change-Id: I43235fefcbff5f730efaf0a8e70b906e62cee42e
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Based on the nivviks and nereid schematics, nissa is using eMMC HS400
mode, so enable this in devicetree.
BUG=b:197479026
TEST=Build test nivviks and nereid
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: Ie9772385276d3629079b95024d3ffa04438f22c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Only the info about the location of the EC firmware will be stored right
at the beginning of the flash, so the size can be reduced to 4kByte
which is the erase block size of the flash. The CHAUSIE_MCHP_SIG_FILE
file itself is smaller than this.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Icde5f7071183cd8423fc022caf49e2c9ee288527
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62189
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
const void is not a proper return type for a function. It's the
function pointer themselves that need to be const.
This fixes building with clang.
Change-Id: I99888ab9d9d80f1d6edb33b9f4a3f556f211a6e2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
NixOS 21.11 introduced the option `programs.flashrom.enable`. The option
allows installing flashrom and hooking up its udev rules. Thus, set it
to `true` and add the user `user` to the `flashrom` group allowing it to
use the programmers.
Change-Id: I017ddb4314702a5252dfc0d05cd1e4961043d23b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This patch adds `pmc_mmio_regs` a public function for other IA common
code may need to get access to this function.
BUG=none
TEST=none
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I67a0f7fdcd0827172426bc938569a5022eff16f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This patch selects SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE config to
reflect the SoC actual behaviour where PMC PCI device is still
visible over bus even after FSP-S exit.
Additionally, add DNV PMC PCI ID into PMC IA-common code.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iaaea20e54c909800e4d75b58c29507fc1944cfba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
Need to tune I2C bus 0/1/3/5 clock frequency under the 400kHz for
audio, TPM, touchscreen, and touchpad.
Audio CLK: 385 kHz
TPM CLK: 380.5 kHz
Touch Screen CLK: 373.3 kHz
Touch Pad CLK: 372.7 kHz
BUG=b:218577918
BRANCH=master
TEST=emerge-brya coreboot chromeos-bootimage
measure by scope with felwinter.
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I3e5cc10d6605f9cc41fa6b31da07a81364b72fe0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Move the EC to a location that does not conflict with where the main
CBFS is in the chromeos FMAP
Change-Id: I28c84cbe2ff10d45383d896ae4f942ee49eb15c0
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62190
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Lack of strip made it required to pass arguments to the
kconfig-to-binary macro without spaces. Strip fixed invalid behavior of
this macro.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I9889b45f773b9675fae287086d324c180c505a4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Alder Lake N SOC has eMMC device. Add ACPI ASL methods for it.
Change-Id: I53f04e81584493049d37b46e078d394d3c8a2f09
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Replace HTTP links with paths to Markdown files where possible.
Change-Id: I0ecca6460105b10b81c4fc014f00235b5d9b861c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Fix formatting when text should be bold.
Change-Id: I7a88ddc0a56dba8c05d0997f37121d0f2cc84ce6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Add a site containing general information for GSoC contributors and
mentors. It was initially copied from https://www.coreboot.org/GSoC.
Change-Id: I5c21d026118cba571dc6b817e89cc4da296a1799
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
On Sabrina SoCs the size of the APOB has increased, so the size of the
RW_MRC_CACHE FMAP sections needs to be increased in order for the data
to still fit in the corresponding FMAP partition.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib31b918aba90dd507b47aec9e1f75c138857cd02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62155
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Sean Rhodes