Commit Graph

25837 Commits

Author SHA1 Message Date
Gaggery Tsai 8aee7f7fad src/soc/intel: Add AML IGD in platform reporting
This patch revises IGD naming and adds AML IGD in platform reporting.

BUG=None
BRANCH=None
TEST=emerge-atlas coreboot chromeos-bootimage & Ensure AML IGD is shown
     in platform reporting.

Change-Id: Id8f8379703abdaa5b14a4337a4fca04b370f3a2a
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/27846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-06 07:58:21 +00:00
Gaggery Tsai c14307e50a soc/intel/skl: Add AML IccMax and remove unused info
This patch adds AML IccMax for VR configuration. From doc #594883, the
IccMax for Core was changed to 28A, we need this patch to accommodate
the changes. Besides, removes unused sku information from
sku_icc_max_mapping structure.

BUG=b:110890675
BRANCH=None
TEST=Remove icc_max from DT &
     emerge-atlas coreboot chromeos-bootimage &
     Tested with AML-Y and KBL-Y SKUs.

Change-Id: Ic22bae162b58b06b9519f1b708be55bde5e4641e
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/27610
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-06 07:58:06 +00:00
Sumeet Pawnikar f5fd9a3e59 mb/google/octopus/variants/baseboard: Update Power Limit1
Update power limit1 value from 8W to 10W. There is an error
in the energy calculation for current VR solution on GLK.
Experiments show that when power limit1 set to 10W, gained
performance improvement with SoC TDP reaches max (6W) power.

BUG=b:79779737
BRANCH=None
TEST=Build coreboot for Octopus board.

Change-Id: Ic320d442e7401e4be2e8e16d691db4c803f0fdc1
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/27819
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-06 07:57:34 +00:00
Raul E Rangel 6b0fc80ff2 soc/amd/stoneyridge: Enable spread spectrum in bootblock
setup_spread_spectrum is called in early_init, meaning the console is
not initialized yet. So you won't see boot block booting twice.

BUG=b:111610455
TEST=booted grunt and verified that AmdInitReset does not reboot. I had
AGESA patched to skip the JTAG check.

Change-Id: Ia036ea513ac67d4b8bcf5a78029d969a4ae012a6
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-06 07:57:12 +00:00
Kane Chen c024381f8f vendorcode/intel/fsp/fsp2_0/glk: Add nWR config in Odt Config
From doc 571118, the bit 5 of OdtConfig is nWR config.
If the bit 5 is set, MRC will set MR1 nWR field to 24.
If the bit 5 is clear, MRC will set MR1 nWR field to 6.

Change-Id: Ic8e4e2ffb098c8ba2f670535981e9a30c3d45b64
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/27814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-06 07:56:47 +00:00
Raul E Rangel a8b4b75d24 exception: Fix segment error code mask
The segment error descriptor is actually 13 bits long.

BUG=b:109749762
TEST=Verified by causing a segment error

Change-Id: I3439f9ce1e8cf0c472c4eb82d74a787718c9609f
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27812
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-06 07:56:00 +00:00
Crystal Lin 54bb0ce17c mb/google/octopus/variants/fleex: Enable Weida touchscreen device
This change adds ACPI properties for WDT8752A device.

BUG=b:111402335, b:111102092
BRANCH=master
TEST=Verify touchscreen on fleex works with this change

Change-Id: Id186d5b87343007ae7e631d5d27464ee27e5b27d
Signed-off-by: Crystal Lin <crystal_lin@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-06 07:55:33 +00:00
Zhuohao Lee 11f016063f mb/google/poppy/variants/rammus: add rammus devicetree.cb
Use the default value for Iccmax which is specified in vr_config.c.
The AcLoadline and DcLoadline keep the poppy value. Besides, the
USB 2.0 ports located on the mainboard are set to USB2_PORT_SHORT
and the others on the daughterboard are set to USB2_PORT_LONG.
Those setting need to be fine tuned later.

BUG=b:111579386
BRANCH=Master
TEST=Build pass

Change-Id: Icabfac04c94b3d480872c243d811509e274ef122
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/27808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-06 07:55:20 +00:00
Zhuohao Lee 351655cfd0 mb/google/poppy/variants/rammus: add gpio setting
The gpio setting is based on the proto board schematics

BUG=b:111579386
BRANCH=Master
TEST=Build pass

Change-Id: I20fc081d372b8686f6128a7e85276f9c6798b199
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/27807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-06 07:55:12 +00:00
Zhuohao Lee 3d1bd1f042 mb/google/poppy/variants/rammus: add memory configuration
Add memory configuration based on the proto board schematics

BUG=b:111579386
BRANCH=Master
TEST=Build pass

Change-Id: I45efdc7893b5bcbca0de6e932e1452cc1a2ff028
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/27806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-06 07:55:04 +00:00
Zhuohao Lee bd6f00f7a3 mb/google/poppy/variants/rammus: add audio, mic and codec configuration
Rammus uses DA7219 Headset, Maxim MAX98927 Smart Amps and 4 channel dmic

BUG=b:111579386
BRANCH=Master
TEST=Build pass

Change-Id: If21a3870ee4b000a776d2f3e025fb43ef2fe48c7
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/27805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-06 07:54:55 +00:00
Zhuohao Lee 0d8d4c642a mb/google/poppy/variants/rammus: change build directory to rammus
Move the build board directory from poppy to rammus.

BUG=b:111579386
BRANCH=Master
TEST=Build pass

Change-Id: I3a9fc2bbfe7261661f0c5c073baff0ff1434d09f
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/27804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-06 07:54:46 +00:00
Raul E Rangel 9ea7762e79 mp_init: fix typo
BUG=none
TEST=none

Change-Id: Ic2d7bf5f5335894ede98dc7e6cc6a65e4897e487
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-06 01:10:14 +00:00
Richard Spiegel b978b61b4a mb/google/kahlee: Disable SATA in all boards
Kahlee based boards don't use SATA, so disable SATA on all boards to save
power.

BUG=b:112139043
TEST=Build and boot grunt, checked the absence of SATA PCI.

Change-Id: I6a12c03a5a95b1c8b40609a3fe656df92548b80b
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-06 01:09:48 +00:00
Richard Spiegel bb18b43065 soc/amd/stoneyridge: Disable SATA based on devicetree setting
Grunt boards don't use SATA, so it should be disabled to save power.
Check if SATA is enabled in devicetree, and enable/disable the device
based on that setting.

BUG=b:112139043
TEST=Buil and boot grunt, checked the absence of SATA PCI.

Change-Id: I4a3b5f65e612e8da5bedff0c557a0850f350dfa8
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-06 01:09:04 +00:00
Angel Pons cea8493285 southbridge/intel/bd82x6x/Kconfig: Do not include any IFD by default
Since only a handful of boards have descriptor blobs in the tree, it makes no
sense to have `HAVE_IFD_BIN` enabled by default then disabled on each mainboard.
This patch flips the default value of said variable, rendering all current
overrides unnecessary. The few boards which have an IFD in the blobs repo use
`select HAVE_IFD_BIN` to enable adding the IFD by default.

Since `HAVE_ME_BIN` depends on `HAVE_IFD_BIN`, the former has been removed
alongside the latter, and has been added to the boards with a ME blob as
`select HAVE_ME_BIN`.

Both `HAVE_IFD_BIN` and `HAVE_ME_BIN` have been removed from autoport as well.

Change-Id: I330c4886f8bea4b1a8ecad6505a0e5cc381654d1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/27218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-05 19:57:56 +00:00
Felix Held 3a2f900cfe x4x/raminit_ddr23: use MCHBAR AND/OR/AND_OR macros [2/2]
This patch contains the parts that changed the hash of the generated binary;
probably due to the compiler optimizing things slightly different.

Change-Id: I3233ba1747dcf5ad05b2ad771a86e3936f655d1c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-08-04 18:44:11 +00:00
Felix Held f83d80bfe8 nehalem/raminit: remove read_mchbar functions
Change-Id: I7935cc166aa39f4053f45eef925d92ce50fd98ba
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-08-04 18:28:03 +00:00
Felix Held 22ca8cb415 nehalem/raminit: clean up code and remove write_mchbar functions
This part of the cleanup patches changes the hash of the output binary; likely
due to the compiler optimizing things differently.

Change-Id: I1a22f6216a75e2b463d4e169e97ad6e0bbaafae8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27708
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-04 18:27:31 +00:00
Felix Held 752cdbc132 northbridge/nehalem: add MCHBAR8/16 AND_OR macros
Change-Id: I62e4a8610689e72944e1a9c020f13a47d402c136
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-08-04 18:26:32 +00:00
Felix Held 04be2dd757 nehalem/raminit: clean up code and use MCHBAR macros
On a a timeless build with coreboot i386 crossgcc 6.3.0, this doesn't change the
hash of the output binary.

Change-Id: I15e09320e72cffb8a2617eca0cfe40780f74bece
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27707
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-04 18:26:01 +00:00
Felix Held 29a9c0718d nehalem/raminit: remove REAL define and most dead code
The code only compiled when REAL was set to 1; the other case included an
unpublished include.

Change-Id: I7f31e9cd02f45492d6c9e88ec6164a537ca5e3c2
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27706
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-04 18:25:44 +00:00
Michał Żygowski 6837769a90 mb/pcengines/apu2: turn LED 2 and LED 3 off in final stage
Due to vendor's requirements LED 2 and LED 3 should be turned
off in late boot process. Add appropriate functions to read and
write GPIO status.

Change-Id: Ia286ef7d02cfcefacf0e8d358847406efe1496fb
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/27729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-04 15:20:12 +00:00
Michał Żygowski a4432f469a mb/pcengines/apu2: change GPIO setting
Change GPIO setting to use IOMUX to refer to GPIO by
IOMUX register as in BKDG for Family 16h Models 30h-3fh
Processor Rev 3.06.

Change-Id: Icf4a60acabe65cd7f9985bb3af8bd577764d4196
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/27665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-04 15:19:01 +00:00
Patrick Rudolph 6838aaebf9 drvs/intel/gma/acpi: Add methods to use MBOX3
* Add Mailbox 3 driver
* Request brightness change through Mailbox 3
* Return Ones on error or if unsupported
* Mark existing code as legacy
  (still required if no GMA driver is running)
* Call legacy code if Mailbox 3 is unsupported, on error or
  if gma driver isn't running

Tested on Lenovo T430:
* Brightness control still works
* Brightness is the same on S3 resume

Change-Id: I51554c819148336b204d28972cbf775a10c3fb8a
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/27711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nathaniel Roach <nroach44@gmail.com>
Reviewed-by: Nicola Corna <nicola@corna.info>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-04 00:23:09 +00:00
Philipp Deppenwiese bce49c2304 security/tpm: Improve TCPA log generation
* Make tcpa_log_init static and move init code into
the tcpa_log_add_table_entry routine.
* Add more checks for log initialization.
* Fix minor issues

Change-Id: I215d79eed7ad17c6ab87f0c4b14a282e519ef07d
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/27769
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-03 23:46:21 +00:00
Julius Werner 0a0340e42e gpio: Change gpio_baseX_value() function return types to unsigned
This patch changes the return type of gpio_base2_value() and related
functions from int to uint32_t. This makes more sense now that
board_id() and related functions (which are the primary use case) also
return that type. It's unlikely that we'll ever read a strapping of 32
GPIOs in a row, but if we did, we'd probably want to treat it as
unsigned.

Change-Id: I8fb7e3a7c76cb886aed40d0ada1f545180e43117
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/27809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-08-03 18:10:02 +00:00
Philipp Deppenwiese 62431a7224 southbridge/intel: Remove leftover TPM ACPI code
Remove ACPI code which isn't necessary anymore due
to the LPC TPM ACPI generator.

Change-Id: I2fae286d61ec7c1036d1a8fa800dc8d9603252e9
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/27767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-08-03 17:30:23 +00:00
Marc Jones 2d5f9cace5 soc/amd/common: Remove PSPP override setting
For some reason the PSPP setting was being overwritten in the common
code. Remove the setting and allow the oem customize function to
make the setting.

BUG=b:112020107
TEST= build test

Change-Id: If7f4511a71f725fedd60d33552656850e50d955d
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/27783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-03 16:01:12 +00:00
Tristan Corrick 921a4cfa3f mainboard: Add ASUS P8H61-M LX
Tested with GRUB 2.02 as a payload, booting Debian GNU/Linux 9.5 with
kernel 4.9. This code is based on the output of autoport.

The file `data.vbt` matches the VBT in the latest version of the vendor
firmware (version 4601).

This board works well under coreboot. A list of what works and what
doesn't can be found in the documentation part of this commit. To
summarise: the only known issues are that S3 suspend/resume doesn't
work, and that there is no automatic fan control via the super I/O.

Change-Id: I2a0579f486d3a44de2dd927fa1e76b90c3b48f62
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/27798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-08-03 15:18:07 +00:00
Tristan Corrick 66da032891 superio/nuvoton/nct6776/acpi: Add PS/2 mouse support
By defining SUPERIO_KBC_PS2M, ACPI code is added to show the PS/2 mouse.
This has been tested on an ASUS P8H61-M LX with Linux 4.9.110 and
4.17.8. In each case, the PS/2 mouse works automatically, whereas it was
not detected before.

Change-Id: I7983f85b3fd23547950f1f75a81bbca63c63d52b
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/27797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-08-03 15:17:01 +00:00
Tristan Corrick 8f731b847e superio/acpi: Make _CRS methods Serialized, eliminating IASL remarks
When compiling for the ASUS P8H61-M LX, IASL 20180531 emits the
following remark: "Control Method should be made Serialized (due to
creation of named objects within)". Making the appropriate methods
Serialized eliminates these remarks.

Change-Id: I8e95d9a00a629a2f904c79b78fac20810327ed37
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/27796
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-03 15:10:34 +00:00
Tristan Corrick 19961a4b1b superio/nuvoton/nct6776/acpi: Add parallel port support
Exposing the parallel port via ACPI causes Linux to automatically detect
the parallel port and load the appropriate modules. Tested on an ASUS
P8H61-M LX with Linux 4.9.110 and 4.17.8.

However, no parallel port device has been tested.

Change-Id: I2529a074e24433d093ad0650a45c7b29238620f3
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/27795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-08-03 11:18:03 +00:00
Matt DeVillier ad691ad65d sandybridge/raminit_mrc: remove reference to report_platform_info()
Commit ef8c559e53
[nb/intel/sandybridge/report_platform: Move remaining code to sb folder]

moved reporting code to the southbridge, but missed a reference in the
non-default MRC raminit path (so testing missed it).
Remove invalid reference to fix compilation error.

Test: build google/link with MRC raminit option selected

Change-Id: I270a95ac53fbc9f8792f375908cf91585261f6a1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-03 11:16:37 +00:00
Tristan Corrick 4505ab2a1f superio/nuvoton/nct6776/acpi: Fix typo in comments
The constant used in the ACPI code is NCT6776_SHOW_KBC, so update
the comments to reflect that.

Change-Id: I9ba69384866088f84a516557d76864104a024968
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/27794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-08-03 10:22:06 +00:00
Arthur Heymans b3587a60ab cpu/x86/lapic/apic_timer.c: Compile the same code for all stages
timer_monotonic_get() was only compiled in a !__PRE_RAM__ environment.
Clean up the code paths by employing CAR_GLOBAL for the global state
which allows the same code to be used in all stages.

Change-Id: I08fd1795508f76abdab1618585366bf9d06482ff
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27801
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-03 09:13:20 +00:00
Matt DeVillier 59962f3015 mb/google/auron,cyan: Remove interrupt from devicetree LPC TPM chip driver
These boards require polling vs interrupts, so remove the IRQ definition to
prevent it being added to the SSDT device entry.

Test: Boot Linux on various auron and cyan variants, verify no error for
'TPM interrupt not working' present in kernel boot log.

Change-Id: Ia1139389f075934d41e823ce5190011c90c7cc88
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-03 08:07:31 +00:00
Lijian Zhao 4c1b6b31c0 soc/intel/cannonlake: Report Whiskey Lake info
According to #574725, report Whiskey Lake CPUID, MCH device ID and
graphics device ID in bootblock stage.

BUG=N/A
TEST=Build and boot up whiskey lake rvp platform and check serial log to
see proper CPU/MCH/GFX/PCH got recognized.

Change-Id: I3fbc190e0520989d2fd4a9b3294e84d67e49b2cf
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/27756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2018-08-03 08:06:00 +00:00
Lijian Zhao 3638a52a64 soc/intel/coffeelake: Add initial coffeelake support
Add coffeelake config and include path to coffeelake fsp header files.

BUG=N/A
TEST=Using private mainboard file can boot up on coffeelake rvp
platform.

Change-Id: Ide180de32a9d1896bed85b9e093963721c3d6041
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/27468
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-03 08:05:35 +00:00
Gaggery Tsai 177f343bcc mb/google/poppy/variants/atlas: Apply correct AC/DC loadlines
This patch applies correct AC/DC loadline settings for Atlas from
VRTT report.

BUG=b:111419622
BRANCH=None
TEST=emerge-atlas coreboot chromeos-bootimage and use DbC to check
     the AC/DC loadline settgins.

Change-Id: I6e85b885a6d3a1db9a980d12f3cfc036a771422a
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/27788
Reviewed-by: Caveh Jalali <caveh@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-03 08:04:58 +00:00
Julius Werner 32912997bc google/cheza: Deassert USB hub reset pin
This patch makes sure we deassert the USB hub reset pin so the hub will
work with the next board revision that drops the external pull-up.
(Actual USB support comes in a later patch.)

Change-Id: I1efdc3594cfa3229891d42d445a21c1739170b79
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/27790
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-02 22:09:17 +00:00
Julius Werner 302e7bc5de cheza: Add board ID, RAM code and SKU ID
This patch adds the required callbacks to read all strapping IDs on
Cheza.

Change-Id: I6437bbd03bdd00dfeedcafebabeb00b13588d052
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/27789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-08-02 22:09:07 +00:00
Arthur Heymans cc7a411fc5 util/ectool: Handle arguments more carefully
Check if an argument is given and if not print the usage.
Check if all arguments are handled by getopt and if not print the usage.

Change-Id: I40dbd2a51d018eb549e9b2fa4365b3e4f9355bff
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Evgeny Zinoviev <me@ch1p.com>
2018-08-02 21:55:27 +00:00
Arthur Heymans 8cd17eae2f util/cbmem: Handle arguments more carefully
Check if all arguments are handled by getopt and if not print the usage.

Change-Id: Iccbb65ca768a62791af54afd9b7903495bc690af
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-08-02 21:55:20 +00:00
Alexander Couzens 4af5d9a94a mb/lenovo/x1_carbon_gen1: add vbt
Extracted from live running Thinkpad x1 carbon gen1 with vendor firmware.
Thanks to Igor Lee.

Change-Id: Id59517d9040c98e67a42fbce537f42f6b0c6db2d
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Tested-by: Igor Lee <getrun@gmail.com>
Reviewed-on: https://review.coreboot.org/27782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-02 21:55:08 +00:00
Sumeet Pawnikar f56ac33f3b mb/google/poppy/variants/nami: Tune Fan speed
Tuning of fan speed for different temperature values. Earlier while
running few benchmarks, fan was always getting on and starting at
higher speed. With this change fan will start with lower speed and
slowly speed gets increased if temperature continue going high.
Thermal team provided these data after fine tuning of fan speed.

BUG=None.
TEST=Verified on Nami running with different benchmarks and observed
fan speed.

Change-Id: Ic3be9e44deef9570200c71807a2ee712d9f20876
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/27683
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-02 21:54:44 +00:00
Shelley Chen 60c44e2578 mb/google/poppy/variants/nami: Enable mbox command for ISL VR c-state issue
There is a potential IMVP8 issue for KBL that affects Intersil VRs
Nami is using one of the affected parts. The fix is to use an updated
microcode and also send a mailbox box command from FSP.

BUG=b:112081534
BRANCH=None
TEST=Build and boot Nami
     Verify that suspend/resume and consecutive reboots are working

Change-Id: I6ec18a4c3fae6a66cf8a95685d91a8ba51e2697c
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/27780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-02 18:23:25 +00:00
Matt DeVillier 5745456343 google/banon: Add support for additional RAM types/configs
Adapted from chromium commits 831a372 and cc96c27
[Banon: board 2nd source DDR memory]

Add support for hynix/H9CCNNN8GTALAR-NUD and Nanya/NT6CL256T32CM-H1

Original-Change-Id: Ifd161ba5ade44e71c88655f760ca66668b5c5178
Original-Change-Id: I5cba13701ed8e037e21d34ed55162ee56291a842
Original-Signed-off-by: T.H. Lin <T.H_Lin@quantatw.com>
Original-Tested-by: TH Lin <t.h_lin@quanta.corp-partner.google.com>
Original-Reviewed-by: Vincent Wang <vwang@chromium.org>
Original-Reviewed-by: YH Lin <yueherngl@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I2166d1025ede33148c7ab623ba59190a342c4736
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-02 10:54:46 +00:00
Matt DeVillier c9f0732cf1 google/edgar: Add support for additional RAM types/configs
Adapted from chromium commits 2319742 and 3b59fb2
[Edgar: Add Micron MT52L256M32D1PF-107 SPD data]
[Edgar: Add Hynix H9CCNNN8GTALAR-NUD and Nanya NT6CL256T32CM-H1 SPD data]

Supported 2nd source Hynix, Micron, and Nanya memory.

TEST=Built and used mosys command by "mosys -k memory spd print all"

Original-Change-Id: Iec9160b74d2812620d2d28f841d503e2d63c8579
Original-Change-Id: I610f01a0198f835a2038511ff78bf0cfba7812a0
Original-Signed-off-by: Hank2_Lin <Hank2_Lin@pegatroncorp.com>
Original-Reviewed-by: Vincent Wang <vwang@chromium.org>
Original-Reviewed-by: YH Lin <yueherngl@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: If2379d6e58425616f49d77b0cdea1cd90f9a8bfa
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-02 10:54:05 +00:00
Matt DeVillier 404962f32c google/cyan: Configure WLAN_CLKREQ as GPIO and always assert low
Adapted from chromium commit adcb858
[cyan: Configure WLAN_CLKREQ as GPIO and always assert low]

This is a workaround for issue b/35648315 as proposed by Intel to
ensure that WLAN_CLKREQ always stays low.

BUG=b:35648315

Original-Change-Id: I178b3e4fbf74cf08eadfa8bd31b80b018f330e77
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/1055652
Original-Reviewed-by: Rajat Jain <rajatja@chromium.org>
Original-Tested-by: Rajat Jain <rajatja@chromium.org>

Change-Id: Ie3458b3fbd1ecadf6b99b9804fb98440cf8d6938
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-02 10:53:55 +00:00