Based on Brya EVT schametic, replace audio amp max98357 with max98360.
Add a new audio FW_CONFIG field to support ALC5682I+MAX98360.
BUG=b:224423056
BRANCH=firmware-brya-14505.B
TEST=dmidecode -t 11
Change-Id: I3033e31cf5c2dade02dc19531f5e5365eeeb7a78
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Use MOCK TPM in vboot, since TPM is not enabled in ADLN RVP.
BRANCH:NONE
TEST=build and boot ADL-N RVP. Verify no TPM errors in depthcharge.
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: Ibc0112545dbd80921d89d48eff58c512729243af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Image Slot Header (ISH) is a new feature.
The rom layout for A/B recovery with ISH:
EFS -> PSP L1 0x48 -> ISH A -> PSP L2 A -> BIOS L2 A
0x4A -> ISH B -> PSP L2 B -> BIOS L2 B
The newer 55758 will updated about the boot priority and update retry
in ISH header.
Change-Id: Ib0690cde1dce949514c7aacebe13096b7814ceff
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Compared to Cezanne, the Sabrina SoC has a 3 additional PSP firmware
table entries, so add those as a preparation for Sabrina support.
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iaa5aacd53b3c7637f6d5e94b1a8d92bba57ddb9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Sabrina only supports PCIe and no SATA or 10 GBit/s ethernet on its DXIO
lanes.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib5aa3abf21e20bbe846f1acfdc2755e97eca1e63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63121
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We use bool in this file, so switch to using types.h.
BUG=b:226635441
TEST=Build skyrim with DEBUG_ESPI
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I78b579de4e3832dd49a18413bf5d03870e347c91
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63092
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To control I2S in MT8195 for dojo project, we need to enable adsp
power before audio power. Therefore, we need to update bus protection
steps to correct the setting.
TEST=build pass
BUG=b:204391159
BRANCH=cherry
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Change-Id: I0bcf1ddeebf0d3df0a1d6b22273123be1aaf85a8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63106
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Parts K4U6E3S4AB-MGCL and K4UBE3D4AB-MGCL require special handling. This
commit assigns them exclusive IDs 9 and 11 to facilitate this.
BUG=b:224884904
Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: I01ea1442b20849a404cf397614c25a441cc84c4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
These are all set but unused variable problems.
Change-Id: I40aaa1d1cdd90731a23142f1f7a0f67a45915f25
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This patch implements coreboot native debug handler to manage the FSP
event messages.
`FSP Event Handlers` feature introduced in FSP to generate event
messages to aid in the debugging of firmware issues. This eliminates
the need for FSP to directly write debug messages to the UART and FSP
might not need to know the board related UART port configuration.
Instead FSP signals the bootloader to inform it of a new debug message.
This allows the coreboot to provide board specific methods of reporting
debug messages, example: legacy UART or LPSS UART etc.
This implementation has several advantages as:
1. FSP relies on XIP `DebugLib` driver even while printing FSP-S debug
messages, hence, without ROM being cached, post `romstage` would
results into sluggish boot with FSP debug enabled.
This patch utilities coreboot native debug implementation which is
XIP during FSP-M and relocatable to DRAM based resource for FSP-S.
2. This patch simplifies the FSP DebugLib implementation and remove the
need to have serial port library. Instead coreboot `printk` can be
used for display FSP serial messages. Additionally, unifies the debug
library between coreboot and FSP.
3. This patch is also useful to get debug prints even with FSP
non-serial image (refer to `Note` below) as FSP PEIMs are now
leveraging coreboot debug library instead FSP `NULL` DebugLib
reference for release build.
4. Can optimize the FSP binary size by removing the DebugLib dependency
from most of FSP PEIMs, for example: on Alder Lake FSP-M debug binary
size is reduced by ~100KB+ and FSP-S debug library size is also
reduced by ~300KB+ (FSP-S debug and release binary size is exactly
same with this code changes). The total savings is ~400KB for each
FSP copy, and in case of Chrome AP firmware with 3 copies, the total
savings would be 400KB * 3 = ~1.2MB.
Note: Need to modify FSP source code to remove `MDEPKG_NDEBUG` as
compilation flag for release build and generate FSP binary with non-NULL
FSP debug wrapper module injected (to allow FSP event handler to execute
even with FSP non-serial image) in the final FSP.fd.
BUG=b:225544587
TEST=Able to build and boot brya. Also, verified the FSP debug log is
exactly same before and with this code change.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I1018e67d70492b18c76531f9e78d3b58fa435cd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The variable actually makes to code look a lot better.
TESTED: BUILD_TIMELESS=1 results in identical binaries
Change-Id: Ie9104e4736a3c30b7592bb0e79a8ddc6af579800
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Vendorcode is messy so instead of trying to fix the warnings thrown by
clang ignore them on AGESA platforms.
Change-Id: I378571c2b7272901761c786c6daec0a403155d4c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Clang complains that the terniary '?' operator is executed before the
bitwise '|'. This is true and desired in this case. Being explicit
about won't hurt however.
Change-Id: I27d1fc1c19e1dab3d1c82e407151eaa46f8c7b03
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
FSP 2.3 spec introduced new version of NV storage HOB
FSP_NON_VOLATILE_STORAGE_HOB2. This new HOB addresses the limitation of
FSP_NON_VOLATILE_STORAGE_HOB which can support data length
upto 64KB. FSP_NON_VOLATILE_STORAGE_HOB2 allows >64KB of NVS data to be
stored by specifying a pointer to the NVS data.
FSP_NON_VOLATILE_STORAGE_HOB HOB is deprecated
from FSP 2.3 onwards and is maintained for backward compatibility only.
This patch implements the parsing method for
FSP_NON_VOLATILE_STORAGE_HOB2 HOB structure .The HOB list is first
searched for FSP_NON_VOLATILE_STORAGE_HOB2. If not found we continue
to search for FSP_NON_VOLATILE_STORAGE_HOB HOB.
BUG=b:200113959
TEST=Verified on sapphire rapids and meteor lake FSP platform that
introduces FSP_NON_VOLATILE_STORAGE_HOB2 for retrieving MRC cached data.
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I27647e9ac1a4902256b3f1c34b60e1f0b787a06e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Fixes building with clang.
Change-Id: I7027f3681e18b8ca0d2f0c899412806082846463
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63050
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds EFI status code macros in `efi_datatype.h` to implement
FSP debug event handler natively in coreboot.
Added `PiStatusCode.h` and `StatusCodeDataTypeId.h` files for
`UDK base >= 2017`, as these files were added with UDK version 2017.
BUG=b:225544587
TEST=Able to build and boot Brya.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib2debb6a50581456783dc9f22f892f8f92a25509
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch resolves compilation issue of including `efi_datatype.h`
in other stage files due to unresolved EFI_PROCESSOR_INFORMATION macro
definition. EFI_PROCESSOR_INFORMATION defined in `Protocol/MpService.h`
hence, included to resolve compilation issue.
TEST=Able to build brya.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4c0ca4f8876e46f1748ffc9e3b90de00ead80ebd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Include paths fixup macro for vboot was broken and was adding
unnecessary prefix to paths from $(coreboottop). This patch adds correct
filters to fix this behavior.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I264e715fa879a4e56b6e5f5423916298e8780a2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Putting
src/soc/*/common before src/soc/*/*, and
src/superio/common before src/superio/*,(which is already moved but
with duplicated folder "common")
can make the variables in
common Makefile get the expected value before they are used in other
subdirs.
The later "*" also contains "common", which needs to be eliminated by
"filter-out".
Then we can put some common variables from all the subdir Makefile.inc
to the common Makefile.inc to reduce code redundancy.
Change-Id: I99597af22cac6d12aaef348789664cd7db02ba06
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
ABL generates memory training data whose size is ~80KiB. So increase the
RW_MRC_CACHE region size to accommodate that.
BUG=b:224618411
TEST=Build and boot to payload in Skyrim.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Id2040026a1fe2b3f760724023e2e252e137b31c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The commit message has a (soft) line length limit of 72 characters and
the subject has a (soft) line limit of 65 characters. This change
updates checkpatch to warn at those limits.
Note that neither of these are hard limits because git & gerrit can both
handle longer lines, it just doesn't look good.
Change-Id: I4ef131a65254e2b184b05e0215969aef97e12712
Signed-off-by: Martin Roth <martin@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
SMMINFO is already set up in S5, so it should be skipped in S3 resume
TEST=builds
Change-Id: I58e25075a007505e53962525ec4d9acd2ce6c7ae
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
SMMINFO is already set up in S5, so it should be skipped in S3 resume
TEST=builds
Change-Id: Ia58000ce9dac5ecb69ca39354f7775524e439bd0
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
SMMINFO is already set up in S5, so it should be skipped in S3 resume
BUG=b:194990818
TEST=Build guybrush
Change-Id: I30ee6d7006ddac4dbdae9825bd4fa6eac7fd48cb
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
For SoC that don't support LPC any more the definition of the PSP soft
fuse chain bit 15 has changed. Earlier SoCs that still supported a
physical LPC bus used this bit to determine if the I/O port 0x80 POST
code are sent to LPC or eSPI. Newer SoCs like Sabrina don't have a
physical LPC bus any more and on those this bit selects if the PSP debug
output is sent to the SoC's MMIO UART or an UART on I/O port 0x3F8 that
the needs to be decoded to eSPI.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0bffb6efacc585a1d02a0455b32f7cf8662b3232
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The separate FMD file for Kano is no longer required, as it was
only required for early prototype testers, and those devices will
be retired soon, therefore switch back to the original FMD file.
BUG=b:226018550
TEST=Build pass.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I09833039a450fa014e8e501bde9fec6e7ed59c7a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Ti50 FW under 0.15 is not support board cfg command which causes I2C
errors and entering recovery mode. And ODM stocks are 0.12 pre-flashed.
Add workaround for the old Ti50 chip.
BUG=b:224650720
TEST=no I2C errors in coreboot.
[ERROR] cr50_i2c_read: Address write failed
[INFO ] .I2C stop bit not received
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ieec7842ca66b4c690df04a400cebcf45138c745d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Precision is a Mid Tower chassis platform with very similar mainboard
to OptiPlex 9010. It has one more PCIe port and a PCI port. It also
incorporates C216 chipset instead of Q77 and enables DRAM ECC support.
Other changes are related to subsystem ID and fan control
initialization.
TEST=Boot Dell Precision T1650 and launch Debian 10.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I4ec2013d5f53af36cab0d1def19272f5ef1a9516
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
New boards like Dell Precision T1650 will be added as variants, in
subsequent commit. They share most of the code, except some EC
initialization tables, PCIe port configuration and subsystem ID.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I4075f0ae3b24892fcc2be07061a01f8070659239
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
The patch add APIs to check CSE Region's write protection information.
Also, adds helper functions to get the SPI controller's MMIO address
to access to BIOS_GPR0 register. The BIOS_GPR0 indicates write and read
protection details.
During the coreboot image build, write protection is enabled for CSE RO.
It is enabled through a Intel MFIT XML configuration.
TEST=Verify write protection information of CSE Region
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: If1da0fc410a15996f2e139809f7652127ef8761b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The Realtek RT8168 and RTL8111K have a similar programming interface,
therefore add the PCI device ID for the RTL8111K into driver for support.
BUG=b:226253265
TEST=emerge-brask coreboot chromeos-bootimage.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I5ad8f14483393d6f25026847cc0d4229d362bba0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
The "Getting started" section is not an appropriate place for the
documentation license. It should rather be listed in the main menu.
Thus, move it there.
Change-Id: I8bfc4f52da8a93d78a62e3a68fd6f1dc8ae4d335
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
coreboot needs to propagate the CnviDdrRfim value info of the feature
enable/disable state into the CNVi via the WiFi DSM ACPI object. This
will be consumed by the Wi-Fi driver and it will act according to
CB enablement configuration. This patch adds _DSM method for that.
Add support for following 2 functions in _DSM method
- Function 0: Function Support Query Returns a bitmask of functions
supported.
- Function 3: RFI enablement 0 Feature Enable 1 Feature Disable
Note: Wifi Dsm already has provision for SAR. This patch will add
additional support to return RFIM structure based on UUID.
BUG=b:201724512
TEST=Build, boot brya0 and dump SSDT entries
Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
{
ToBuffer (Arg0, Local0)
If ((Local0 == ToUUID ("7266172c-220b-4b29-814f-75e4dd26b5fd")))
{
ToInteger (Arg2, Local1)
If ((Local1 == Zero))
{
Return (Buffer (One)
{
0x09
})
}
If ((Local1 == One)){}
If ((Local1 == 0x02)){}
If ((Local1 == 0x03))
{
Return (Zero)
}
Return (Buffer (One)
{
0x00
})
}
Return (Buffer (One)
{
0x00
})
}
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I217b736df3d4224a6732d1941a160abcddbd8f37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
This will allow configuring the concerned config through an external
defconfig file.
BUG=None
TEST=Ensure that AMDFW_CONFIG_FILE is configurable.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I97817a822c8c41822e699adc31f0e7452f93fdb9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62971
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update the two load line slope settings for the telemetry.
AGESA sends these values to the SMU, which accepts them as units
of current. Proper calibration is determined by the AMD SDLE tool
and the Stardust test.
VDD scale: 73331 -> 94623
VDD offset: 1893 -> 1847
SOC scale: 31955 -> 29904
SOC offset: 852 -> 756
BUG=b:217963719
BRANCH=guybrush
TEST=emerge-guybrush coreboot chromeos-bootimage
pass AMD SDLE/Stardust test
Change-Id: Icad97644dd9391a325dfe1dbb1ec176e1f6d3dc3
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The Pubkey(0), PSP bootloader(1) and IKEK(0x21) should be put to
level 2 only for A/B recovery for Sabrina, which is going to be the
long term and A/B recovery layout only. So the amdfwtool should be
changed for Sabrina.
The old levels of these 3 FWs are for Cezanne, which doesn't use AB
recovery now. Just set the specific field levels in generic Cezanne
folder for demo. Leave the fw.cfg in Guybrush unchanged.
Change-Id: I11092b52927b2c526a5be719104ba39a790b6fa8
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Backlight GPIO was set to HIGH, when it should have been set LOW to
enable the backlight in the embedded display.
BUG=b:224618411
TEST=load on Skyrim proto1, observe backlight
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ife3335ca5a3c2517a6817fccf0544e5fcacb1f9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63003
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current behavior does not actually check if a device is present
before enabling the corresponding gpp_clkx_clock_request_mapping bits
which may cause issues with L1SS. This change sets the corresponding
gpp_clkx_clock_request_mapping to off if the corresponding device is
disabled.
BUG=b:202252869
TEST=Checked that value of GPP_CLK_CNTRL matched the expected value
when devices are enabled/disabled, checked that physically removing a
device that is marked as enabled also disables the corresponding clk req
BRANCH=guybrush
Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: I77389372c60bdec572622a3b49484d4789fd4e4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61259
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Amanda Huang