This function isn't used outside of the same compilation unit.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I332046341bc7a5a499355f2147296e8c09d7e0ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50817
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TEST=Boot majolica to linux and see IO-APIC logs
ACPI: Local APIC address 0xfee00000
ACPI: LAPIC_NMI (acpi_id[0xff] high edge lint[0x1])
IOAPIC[0]: apic_id 16, version 33, address 0xfec00000, GSI 0-23
ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 low level)
ACPI: IRQ0 used by override.
ACPI: IRQ9 used by override.
Using ACPI (MADT) for SMP configuration information
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib8094c3edf401659d9d740e2cc6266ddd5f91da9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Since all bridges to the internal buses have the same PCI ID, we can
just add this one ID to the pci_driver struct and don't need to use a
list of PCI IDs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ice024b91f49f03995acbd8dfc8b33d3ae3559dde
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50804
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Without the cast the left shift is done on a 32 bit variable that gets
extended to 64 bits afterwards which results in missing MSBs. To avoid
this, do the cast to 64 bits before the left shift.
Found-by: Coverity CID 1443793, 1443794
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7cfa5b9b6ad71f36445ae2fa35140a8713288267
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This was replaced by APM_CNT defined in src/include/cpu/x86/smm.h, so
remove the now unused definitions.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibd25dcdb57de14fe42352f01067cedca53712d56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
n is the default of bool Kconfig options, so no need to have that added
to each option.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8775d84caee6fda95eb7749e96090fe05417e764
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50779
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
I also removed the unnecessary #include in soc.asl.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifbd79871fd49b18f45d97f64ccd68fa96eaaebce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50572
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This fixes the undefined reference for NVB0, NVB1, and NVB2.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib4ba24b66b9ae7899ccd40f91cdd23074f6afc4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
With chipset_power_state filled in romstage CBMEM hooks and
GNVS allocated early in ramstage, GNVS wake source is now
also filled for normal boot path.
Change-Id: I2d44770392d14d2d6e22cc98df9d1751c8717ff3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Additionally to the PCI IDs of Cezanne it also handles the Renoir ones.
The main difference between those two is that Renoir has two core
complexes while Cezanne only has one core complex. I haven't seen
incompatible changes between those two though, so for example the fabric
IDs are the same and the one that's only present in Renoir is just not
used in Cezanne. Also adding the ACPI parts for those don't have
anything to do with those differences.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3b2517bc15d872f41183a33857333f1972ff2cb9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
When USE_PSPSECUREOS isn't selected, we get stuck in FSP-S.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I60d0e5ab0bd9f4d76cc48d08ca05d27c60e898c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
I'm not 100% sure yet if this code will be common for all AMD SoCs, so
I'll add a copy for Cezanne for now. This part of the code should
probably be reworked after the initial bringup of Cezanne anyway.
DF MMIO register configuration at the beginning of
data_fabric_set_mmio_np:
=== Data Fabric MMIO configuration registers ===
Addresses are shifted to the right by 16 bits.
idx control base limit
0 a3 fc00 febf
1 a3 1000000 fffcffff
2 a3 d000 f7ff
3 a0 0 0
4 a3 fed0 fed0
5 a0 0 0
6 a0 0 0
7 a0 0 0
DF MMIO register configuration at the end of data_fabric_set_mmio_np:
=== Data Fabric MMIO configuration registers ===
Addresses are shifted to the right by 16 bits.
idx control base limit
0 a3 fc00 febf
1 a3 1000000 fffcffff
2 a3 d000 f7ff
3 10a3 fed0 fedf
4 a0 0 0
5 a0 0 0
6 a0 0 0
7 a0 0 0
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia243a0cad311eb210d14d6242c52f599db22515c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50624
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The number of data fabric MMIO registers is SoC-specific, so we need to
keep that in the SoC code. This also removes a redundant pair of
brackets and moves a loop counter declaration into the head of the loop.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8499f1c1f7bf6849b5955a463de2e06962d5de68
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50638
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The exact same mechanism is used on Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3179d8ec35efa29f9bc66854c3690b389d980bba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50619
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix regression with commit aa969e887a ACPI: Move PICM declaration.
While mentioned in the commit message there already, the default
value for AMD boards changed from IOAPIC mode to PIC mode.
ACPI 6.3 spec has this text regarding _PIC method:
If the platform CPU architecture supports PIC mode and the method
is never called, the platform runtime firmware must assume PIC mode.
If MADT has IOAPIC entries, OS will want to change to APIC model. But
the method _PIC was not in the global scope so it could not be called
and therefore _PRT continued to report PIC model interrupt routing.
Already fixed for soc/amd/picasso in commit 839f668.
Change-Id: I7f3bb0d45946cec315694de1d540fea4d828348e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This will be common for all boards, so move it to the chipset device
tree.
TEST=CPU cluster and LAPIC still show up in console logs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia49e7b4cfc09c60b6152b8ccc47f37b6adc1e319
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50613
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The MADT doesn't populate the IO-APICs yet since we need FSP to
configure those.
The FADT differs from picasso in the following ways:
* The duty_offset is supposed to be 0
* Don't clear x_firmware_ctl_l
* Make the extended addresses use MMIO
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib6c3a01084a0de33894885b47c637a292d252ed4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
TEST=Boot majolica and see microcode update
CBFS: Found 'cpu_microcode_blob.bin' @0x6900 size 0x15c0 in mcache @0xcf7fe9d8
microcode: patch id to apply = 0x0a50000b
microcode: being updated to patch id = 0x0a50000b succeeded
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: If50b1d8b3ebf4b3e6f8a9dd3ab96073e0cb92424
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
We also want to support uCode loading on cezanne.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6f10564c93ce72aea7ff52a8565d65d8b56452f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Stoneyridge used CONFIG_MAX_CPUS and CONFIG_MAX_CPUS + 1 directly as
IOAPIC IDs and Picasso had Kconfig options to configure that, but still
used the common SMBus controller code that used CONFIG_MAX_CPUS as ID
for the FCH IOAPIC. If a board overrides the PICASSO_FCH_IOAPIC_ID
Kconfig option to a value that isn't CONFIG_MAX_CPUS, we'll get a
mismatch between the ID that gets written into the FCH IOAPIC register
and the ID in the corresponding ACPI table. In order to avoid that add
defines to each SOC's southbridge.c and use them in all soc/amd code.
Change-Id: I94f54d3e6d284391ae6ecad00a76de18dcdd4669
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50575
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When USE_PSPSECUREOS isn't selected, we don't even get post codes on
Majolica, so remove this option.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0ec976f40d962a2d9f2bd36dc97d86526bd661ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Without this part being present in amdfw the PSP won't enter its normal
operation mode, but goes into recovery mode instead.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If13b5495e9f246afd0317daaa53c3d2cefbaa4dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
On Picasso we missed setting this bit in coreboot and since the default
after reset is 0, we had to rely on the FSP to set this bit. Stoneyridge
and Cezanne have the HPET decode enable bit in the same position in the
same register. In the ACPI table entry written by
southbridge_write_acpi_tables the HPET entry gets added, so we should
make sure that we enable the decode.
TEST=HPET still works on Mandolin.
Change-Id: Ie98dae1d6036748f700f884d4b9653f2e59c24da
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50512
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The default value of this bit is 0, so set it right before calling
setup_ioapic to make sure that it's set and not to have to rely on FSP
doing the right thing.
Change-Id: Ife886451a6927965769282fc5644c2085abb9585
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50513
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A copy of Picasso's include/nvs.h was added to Cezanne right before the
commit d6ccbb9d48 that removed it for the
other mainboards and SoCs, so apply the equivalent change here as well
to keep everything in sync.
Change-Id: I76b551c05b3c3028a3afb3bc3b77df2401aed7a8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This is another common ACPI setting.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iefecabae1d83996a9a4aaadd2a53c2432441e1b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50558
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is ACPI specific config that applies to all the AMD SoCs. Stoney
doesn't currently use this, but we can add that functionality later.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0be7d917d7c5ba71347aa646822a883e2cf55743
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50557
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is common between stoney, picasso, and cezanne.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5fb40e8c6817773212c5fbd66c5c06bd2bae1eda
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50556
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is common between all the chipsets.
It's also required by common/block/lpc/lpc.c.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I361dfabfe0c04667a2c112955133831a985d5cc0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
These definitions were identical to picasso. The only thing I changed
was that I renamed Misc1 and Misc2 to HPET_L and HPET_H.
This change still doesn't write the PCI_IRQ register for all the PCI
devices. We need to refactor the picasso pci_gpp code first.
TEST=Boot majolica and see FCH IRQs being programmed.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic7e637f234d3af426959a9bbd82a0dcf25bb3c8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50451
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
