Commit Graph

24969 Commits

Author SHA1 Message Date
Srinidhi Kaushik 9e0dd0169d src/mainboard/glkrvp: Turn on CPU fan
On GLK EC does not support temperature reads and does not control
the fans anymore, OS is responsible fan control through EC.

This hack enables running of the fan for boards without External EC.

Change-Id: I361e53d4fd53678f3abb8fe9862071aec6e149a7
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-on: https://review.coreboot.org/22235
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-12-08 23:27:28 +00:00
Ravi Sarawadi 5773c4ce02 vendorcode/intel/fsp/fsp2_0/glk: Update header files as per v69_51
Update FSP header files to match FSP v69_51.
UPD updates in FSP v69_51 are:
  - SGX Epoch
  - Sub/System Vendor ID
  - Remove deprecated UPD

Change-Id: I7298615a6e051061b948814a1cd9cbd42f6574b5
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/22391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-08 23:27:01 +00:00
Shaunak Saha ea17304e64 mb/intel/glkrvp: Fix CLKRUN gpio
This patch does not put CLKRUN in IOSTANDBY.

Change-Id: I7fedd729d3bb66c2b52a63166e461f8760457721
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/22292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-08 23:26:22 +00:00
Hannah Williams 11f7dc87b2 soc/intel/apollolake/acpi/cnvi.asl: Add _PRW for CNVi
Add CNVi GPE in _PRW for wake on WLAN from S3

Change-Id: I682c76b9c5c524face7b540ecb185a3d7b4b2da3
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/22639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-08 23:24:23 +00:00
Hannah Williams cbae0cc931 soc/intel/apollolake/acpi/pch_hda: Add _PRW for HD-A
Add GPE in _PRW for wake from S3 for HD-audio controller

Change-Id: I6ad289be8c58e48ad0ec9d2ee0894fe16b8f2e1c
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/22637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-08 23:24:13 +00:00
Daisuke Nojiri a0ab764519 google/fizz: Set BJ max current and voltage
This patch makes coreboot set the max current and voltage for barrel jack
adapters.

BUG=b:64442692
BRANCH=none
TEST=Boot Fizz. Use chgsup console command to verify the max current and
voltage are set as expected.

Change-Id: Ifebee09096e0935cc7d3e53920a251b0496d3c55
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/22623
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-08 17:14:34 +00:00
Daisuke Nojiri 93fd8fa40f chromeec: Add command to override charger limit
This patch adds EC_CMD_OVERRIDE_DEDICATED_CHARGER_LIMIT, which
overrides the max input current and voltage when a barrel jack
adapter supplies power.

BUG=b:64442692
BRANCH=none
TEST=Boot Fizz. Use chgsup console command to verify the max
current and voltage are set as expected.

Change-Id: I8c6fc54e519ce13e3db82ee2cecaa96c6eb42d8a
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/22624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-08 17:14:30 +00:00
Daisuke Nojiri 40d0bfa212 cr50: Make EC clear AP_OFF before hibnernate
This patch makes AP send EC_REBOOT_HIBERNATE_CLEAR_AP_OFF, which makes
EC clear AP_OFF flag then hibernate.

This is needed to make Chromebox boot when cr50 toggles the EC's reset
line after TURN_UPDATE_ON command.

BUG=b:69721737
BRANCH=none
CQ-DEPEND=CL:802632
TEST=Verify Fizz reboot after cr50 update.

Change-Id: I5f590286393ac21382cab64afdccae92d3fc14ba
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/22657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-08 17:12:37 +00:00
Daisuke Nojiri ff906fb95b cbfstool: Add '-p' option for padding
This patch adds '-p' to the 'add' command. It allows the add
command to specify the size of the padding added with the file
being added. This is useful to reserve an extra space in case
the file is too big to be relocated.

BUG=b:68660966
BRANCH=none
TEST=emerge-fizz coreboot &&
cbfstool image.bin add -n ecrw -f EC_RW.bin -p 0x10 ...
Verify image.bin has extra space in the file header.

Change-Id: I64bc54fd10a453b4da467bc69d9590e61b0f7ead
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/22239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-12-08 16:05:52 +00:00
Patrick Georgi 9adcbfe486 device/pciexp_device: Set values numerically instead of as bitmask
As noted on linux-pci, we have a weird way to handling "value" and
"scale" fields that are supposed to contain numerical values: we encode
them as a bitfield.
Instead define the two fields (offset and mask) and use numbers.

Another issue, not fixed in this CL, is that we write hard-coded values
while these fields really need to contain the max() of acceptable delays
of the downstream devices. That way the controller can decide whether or
not to enter a deeper power management state. It's noted as a TODO.

Change-Id: I895b9fe2ee438d3958c2d787e70a84d73eaa49d2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Found-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-on: https://review.coreboot.org/22740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-08 11:38:05 +00:00
Chris Wang 97ac471a71 mb/google/reef: provide override GPIO table in coral
Allow overriding specific GPIOs by SKU ID. Override two GPIO settings
for nasher to save the power consumption when the system in S0ix.

Change as below:
AVS_DMIC_CLK_A1: IGNORE -> Tx1RXDCRx0.
AVS_DMIC_CLK_B1: IGNORE -> Tx1RXDCRx0.

BUG=b:69025557
BRANCH=master
TEST=compile/verify the power consumption change from ~150mW to ~100mW
     on clamshell SKU and from ~200mW to ~100mW for convertible SKU.

Change-Id: I9e0674f206426fddb3947273754774b310106334
Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/22752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-12-08 10:55:06 +00:00
Subrata Banik ec10fbb90e soc/intel/cannonlake: Add PCH ID support in bootblock/report_platform.c
This patch ensures that all required information for pch/mch/igd
deviceid and revision are available in single stage and makes
use of local references.

TEST=Build and boot cannonlake_rvp to get PCH information as below
PCH: device id xxxx (rev xx) is Cannonlake-Y Premium

Change-Id: I420e94043145e8a5adcf8bb51239657891915d84
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-08 02:43:45 +00:00
Subrata Banik df5ae9ce64 soc/intel/skylake: Clean up bootblock/report_platform.c
This patch ensures that all required information for
pch/mch/igd deviceid and revision available in single
stage and make use of local references.

TEST=Build and boot soraka/eve

Change-Id: I6f7f219536831210750a486ee3b3308d6f285451
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22756
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-08 02:43:27 +00:00
Subrata Banik 3c838c7399 soc/intel/skylake: Remove pch_enable_dev() from SoC
PCI resources MMIO space/bus master enabling is handled inside
pch_dev_enable_resources() from common device code. Hence
no need to have an explicit soc function to do the same.

TEST=lspci from kernel console shows same pci device list
without and without this patch.

Change-Id: I005e486dd435e9c61ae3f5dfe3ff0e8f688d16e1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-08 02:43:18 +00:00
Marc Jones 578a79d500 soc/amd/stoneyridge: Add RO_REGION_ONLY
We only need the apu firmware in the RO region when building
for ChromeOS. Adding it to the RW regions is a waste of space.

BUG=b:70027919
TEST=Build kahlee and use cbfstool to check for "apu/amdfw" sections.

Change-Id: Ieafe4a5ec4a5e3177e4e23fcf42afa2626a0b19f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-08 02:43:06 +00:00
Bora Guvendik 266aee002a mainboard/intel/glkrvp: Change gpio configuration for eSPI
Skip LPC related gpio configuration if eSPI config option
is selected.

Change-Id: I15c5f769f36a1801217b1e3650379c7b181d814f
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/22757
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-07 22:09:39 +00:00
Nico Huber 27e8412b4a buildgcc: Hide stderr output of getopt test
Change-Id: I03c38de3a3b88d569d629be7483eb53164cf136a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/22738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-07 21:56:44 +00:00
Nico Huber 4792689f67 libpayload: Add pci_free_dev() and some boilerplate
Add just enough code and boilerplate to keep it compatible with future
libflashrom.

Change-Id: If0d46fab141da525f8f115d3f6045a8c417569eb
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-07 21:51:24 +00:00
Richard Spiegel 1e2720e467 amd/stoneyridge: Delete early_setup.c
All preparation done, early_setup.c now useless. Delete early_setup.c,

BUG=b:64033893
TEST=None.

Change-Id: Ibe75a2d5cc46641e9d0af462a8a0ba5bb7a0f9c3
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22569
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-07 20:57:42 +00:00
Lin Huang ab21ab97ce google/scarlet: update Kingdisplay kd097d04 timing
With the old timing, the hblank time isn't large enough,
it may cause display artifacts. So fix it.

BUG=b:70160653
TEST=panel work on Scarlet rev2 board

Change-Id: Ib061f5e215611d20f59e3f24cfe3c7fbc507ebed
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/22746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-12-07 20:53:51 +00:00
Nico Huber 45ccab3352 payloads/external/Makefile: Add missing dependency
The depthcharge .config only exists after depthcharge was built. Other
possible `PAYLOAD_CONFIG` files most probably miss a rule, too.

Change-Id: I8e6f79bb2bd07cbef1317f2623bbef9ca0e74880
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Tested-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/22137
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-07 19:28:44 +00:00
Keith Hui 2270a15f11 asus/p2b-ls: Disable SuperI/O ACPI logical device
This logical device is disabled in OEM BIOS. Disable here to match,
since its support is currently incomplete anyway.

Change-Id: I5c07136ec6a14a8ee8cb68537a2663b78fc0fa20
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/22145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-07 19:22:22 +00:00
Keith Hui 819005f58b asus/p2b: Align ACPI tables with asus/p2b-ls
Updates ACPI tables with work done for asus/p2b-ls, including super I/O
related declarations.

Change-Id: Id2420da4ab04aa5f59ac0aa237d21477a03b826e
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/22473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-07 19:20:53 +00:00
Keith Hui cd2c3334c4 asus/p2b-ls: Add ACPI tables
Add ACPI tables support that will be needed for soft-off and S3 resume in the future.
Boot tested for soft-off.

Change-Id: I28b559406bd53efc555dcbb8282dfe2bd6d1af87
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-07 19:20:42 +00:00
Keith Hui 97041de909 sb/intel/i82371eb: Rework ACPI tables
Rework ACPI tables based on a mix of previous work on asus/p2b,
other boards in tree with better ACPI support, and OEM BIOS.
To be pulled in by DSDTs of mainboards using this southbridge.

Disable on-the-fly generation of mainboard _CRS node. It is not working
as it should and causes runtime errors when booting Linux. This node
to be included in mainboard DSDTs in followup patches.

Change-Id: Idda424de7859a36e4cac168d5469f9365a6ad421
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-07 19:20:26 +00:00
Richard Spiegel 9d0aa99c5e kahlee/ec.c: Use new wide IO function
In preparation to deleting early_setup,c, change early_ec_init() to use new
southbridge.c function sb_set_wideio_range and remove <#ifdef __PRE_RAM__>.

BUG=b:64033893
TEST=Build, boot and check serial output, search for "Covered by wideIO xx",
which should match earlier message "Range assigned to wide IO xx" generated
within modified early_ec_init().

Change-Id: Iaea17f4f636aab6bd8b05b1b3bed53a677164e74
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07 17:19:29 +00:00
Richard Spiegel b5f9645927 amd/stoneyridge/lpc.c: Use new wide IO functions
Use the new wide IO functions from southbridge.c to simplify code in
functions set_child_resource and lpc_enable_childrens_resources.

BUG=b:64033893
TEST=Boot to OS, check serial output against previously recorded serial
output from an image without all 5 related changes.

Change-Id: I8533e8ff766df8a8261298559aace7666487826d
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07 17:19:04 +00:00
Richard Spiegel ebf3aa8c63 amd/stoneyridge: Create new wide IO functions
Create new generic wide IO functions in southbridge.c. These new
functions must be usable by kahlee/ec.c and amd/stoneyridge/lpc.c.

BUG=b:64033893
TEST=Just build at this stage, full boot to OS and verify serial output
at related change 14fdd03a83. Some extra outputs for testing removed
when code was committed.

Change-Id: Icd0841a1959f3e109b3c35fa35bb4b3c44099dc3
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-07 17:18:56 +00:00
Furquan Shaikh 903472c3c8 mb/google/poppy/variants/nami: Add support for nami board
This change adds variant nami derived from baseboard poppy.

BUG=b:70160119

Change-Id: Ic6795d49d3e6e98a32f4af0b621e8bb463041412
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07 07:53:37 +00:00
Furquan Shaikh 48be29e392 mb/google/poppy: Add support for DDR4 memory
This change updates memory SPD handling code in baseboard poppy to
allow variants to define either LPDDR3 or DDR4 memory types. In
addition to that, it also updates the function to print SPD info
considering offsets that might be different across the two memory
types.

BUG=b:70188937

Change-Id: Iefad01719c62264fb0d7e987904e77647d6026c2
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07 07:53:20 +00:00
Furquan Shaikh 9bfd8141fb mb/google/poppy/variants/nautilus: Fix memory params
Until now, nautilus was using the DQ-DQS mappings provided by the
baseboard. However, based on schematics, these values are not
correct. This change adds DQ-DQS mapping tables for nautilus.

BUG=b:70188533

Change-Id: Ife6ba19b8fe8873ab8cca977ca8f34a4d86e8e6e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22706
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: shkim <sh_.kim@samsung.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07 07:46:03 +00:00
Bora Guvendik 94aed8d615 soc/intel/apollolake: add ability to enable eSPI
Add config option to enable eSPI

TEST=Boot to OS

Change-Id: Ib4634690fe4fdb902fc0bc074a3b66b91921ddd5
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/22320
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-12-07 05:45:55 +00:00
Aamir Bohra c73073c414 soc/intel/apollolake: Clean up UART code
Clean up and move UART related code under a single uart.c file.

Change-Id: I9a30258ba43ee5920f585c1bd06bc25773778ec4
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/22754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-12-07 03:21:13 +00:00
Aamir Bohra 230ada6d3c soc/intel/skylake: Clean up UART code
Clean up and move UART related code under a single uart.c file.

Change-Id: I7ed03fc5fe79e38350d7edc70ad55d54db780fed
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/22753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-12-07 03:21:04 +00:00
Subrata Banik 75c6f4aeb6 soc/intel/cannonlake: Make use of Intel common Graphics block
TEST=Build and boot cannonlake rvp.

Change-Id: Iaa1314ae3fcb4a8a3b55a314e79511f5dcba163d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-07 02:39:12 +00:00
Subrata Banik b7b5666110 soc/intel/apollolake: Make use of Intel common Graphics block
TEST=Build and boot reef.

Change-Id: I0edd7454912201598c43e35990e470ec18a32638
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-07 02:39:01 +00:00
Subrata Banik cb771a2383 soc/intel/skylake: Make use of Intel common Graphics block
TEST=Build and boot soraka/eve.

Change-Id: I416226d0374700cea6eea602f839c3d17f1f39a6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07 02:38:52 +00:00
Subrata Banik fa7cc7823a soc/intel/common/block: Add Intel common Graphics controller support
SoC need to select specific macros to compile common
graphics code.

Change-Id: Idbc73854ce9fc21a8a3e3663a98e01fc94d5a5e4
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07 02:38:44 +00:00
Tobias Diedrich 85dc0d8dae intel/bd82x6x: Fix a small mistake in DIR_ROUTE
The register is 16-bits wide. If the DIR_ROUTE call ordering was
reversed the previous writes would get overwritten.

See page 407ff on the Intel C216 datasheet, which says
"Size: 16bits" with "Default: 3210h" for all DnnIR registers.

This also makes sense given the register offsets:
3140h–3141h D31IR Device 31 Interrupt Route 3210h R/W
[3142h would be D30IR]
3144h–3145h D29IR Device 29 Interrupt Route 3210h R/W
3146h–3147h D28IR Device 28 Interrupt Route 3210h R/W
3148h–3149h D27IR Device 27 Interrupt Route 3210h R/W
314Ch–314Dh D26IR Device 26 Interrupt Route 3210h R/W
3150h–3151h D25IR Device 25 Interrupt Route 3210h R/W
[discontinuity in register addresses here]
315Ch–315Dh D22IR Device 22 Interrupt Route 3210h R/W
[315Eh would be D21IR]
3160h–3161h D20IR Device 20 Interrupt Route 3210h R/W

Change-Id: I970abbacbc2c59e86c1726171272b8779758e53e
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: https://review.coreboot.org/22621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-12-07 02:36:18 +00:00
Tobias Diedrich 7b093e4627 intel/bd82x6x: Add missing IRQs in ACPI PIRQ link devices
pch_pirq_init() sets all PIRQ links to route to irq 11.
However in the ACPI data, on half the links irq 11 is missing.
The other half is missing irq 10.

This fixes a mostly cosmetic issue in the Linux messages:
  ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 7 10 12 14 15) *11
  ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 7 *11 12 14 15)
  ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 7 10 12 14 15) *11
  ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 7 *11 12 14 15)
  ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 7 10 12 14 15) *11
  ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 7 *11 12 14 15)
  ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 7 10 12 14 15) *11
  ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 7 *11 12 14 15)

Change-Id: I002147d702cacf54a233196932b30732f6a433b3
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: https://review.coreboot.org/22600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-12-07 02:35:53 +00:00
Sathyanarayana Nujella 5c04a111e5 mainboard/intel/glkrvp: Ignore Audio DMIC IOSSTATE
Audio DMIC_CLK needs to be ON in S0ix to support Wake on Voice.
So, configuring GPIO_171 to be as IGNORE IOSSTATE, so that
clock is ON in S0ix state.

BUG=None
TEST=put DUT in S0ix, verified DMIC_CLK
     in scope when wov capture path is ON

Change-Id: I147cf3c12acb11429c6cb234e8c511f57886b6b4
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/22675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07 02:35:14 +00:00
Matt DeVillier ea629fa8c4 Revert "soc/intel/skylake: Clean up SoC ASL code."
This partially reverts commit a7b97510ae.

For the internal eMMC to be used by Windows for installation,
the CARD device and _RMV methods are required.  Without them,
Windows does not see/show the eMMC as a valid installation
target.

TEST: boot google/chell with Tianocore payload and install
Windows 10 to the internal eMMC drive.

Change-Id: I04819ff16ab4cb0d2ea6e1c7f47179f5dacb7cfd
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22684
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-07 02:34:07 +00:00
Richard Spiegel 376dc82dca amd/stoneyridge: Create new name/IRQ association
Table intr_types[] is hard to maintain, and has unused spaces filled with
NULL. A new table format is needed that creates strong association between
the APIC register index and the associated IRQ name, is easy to maintain
and has no unused space (index) to indicate that a particular register is
unused while still indicating which registers are valid.

Also, the string that defines the name of associated IRQ should be declared
with "#define" in a header, but must be physically initiated in a source
file. The "#define" must make a strong association between the used register
index and the associated IRQ name. Example:
#define INDEX_0X16_NAME "PerMon\t"

BUG=b:69868534
TEST=Check serial output against BKDG for AMD Family 15h Models 70h-7Fh
Processors definitions for Pci_Intr_Index. Also, check for new output
format to confirm write_pci_int_table() is working as desired. There's
no test for write_pci_cfg_irqs, as it's not being used by kahlee.

Change-Id: I2dde4d016cc3228e50dcfadd2d3586a3609e608d
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07 02:31:45 +00:00
Randall Spangler 8fdbd114ec security/vboot: Remove unused include of vboot_nvstorage.h
This include is not needed, and the header file is going away in
vboot_reference.  So, remove it.

BUG=chromium:789276
BRANCH=none
TEST=emerge-reef coreboot

Change-Id: Ie0b37ae3d2f979f79060a15ca3f7157f49c89785
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Signed-off-by: Randall Spangler <randall@spanglers.com>
Reviewed-on: https://review.coreboot.org/22733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-07 01:20:51 +00:00
Julius Werner 4177679a84 google/gru: Add SKU ID for Scarlet
Scarlet has SKU detection strapping pins now. This patch adds the code
to read them.

BUG=b:69373077

Change-Id: I8d889a845950923bc7b5be9b79792cf3c8b6b8ad
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22697
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-07 01:19:46 +00:00
Julius Werner b7e1557355 rockchip/rk3399: Select GENERIC_GPIO_LIB Kconfig
This option should've been selected by RK3399 the whole time since the
SoC supports the <soc/gpio.h> interface. It wasn't really a big deal
until now where I'm trying to use a the base2 read helper, though.

Change-Id: Ib7a5f00a6680163105fc0598ce77d03f3645f05a
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22744
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-07 01:19:42 +00:00
Julius Werner f38a10f8d2 libpayload: Add SKU ID coreboot table support
This patch adds support to read the SKU ID entry from the coreboot table
that was recently added in coreboot.

Change-Id: I1c3b375da6119a4f8e8e7e25a11644becb90f927
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22743
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-07 01:19:38 +00:00
Julius Werner 96ed92d49d boardid: Add helpers to read sku_id strapping into coreboot tables
On many recent Chrome OS boards, the desire to unite more configurations
under the same image has led to the need of a "SKU ID" that identifies
different configurations of the same board (e.g. with certain optional
components stuffed or not stuffed, or replaced with a comparable
component). This is markedly different from the existing "board ID",
because that is reserved to count "revisions" -- changes made to the
same configuration over time during the development process. This patch
adds support to have a mainboard define this SKU ID and pass it through
the coreboot table like we already have for board IDs.

Change-Id: I8aabffe8e1003b0d6fb70d689ae513ca4b46aeda
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22696
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-07 01:19:32 +00:00
Julius Werner 4ec3d9d69e boardid: Switch from Kconfig to weak functions
This patch switches the board_id and ram_code helper framework to use
weak functions rather than Kconfigs to determine whether the board
supplies these IDs. This cuts down on the amount of boilerplate Kconfigs
many boards have to set and also gives them more flexibility, such as
being able to determine at runtime whether a given ID is present.

Change-Id: I97d6d1103ebb2a2a7cf1ecfc45709c7e8c1a5cb0
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22695
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-07 01:19:27 +00:00
Julius Werner 2e029ac6a6 libpayload: Minor board ID / RAM code cleanups
This patch mirrors recent cleanups in coreboot regarding the strapping
ID entries in the coreboot table.

Change-Id: Ia5c3728daf2cb317f8e2bc72c6f1714d6cb4d080
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07 01:18:30 +00:00