Commit Graph

20335 Commits

Author SHA1 Message Date
Lee Leahy 6d71a43af5 src/include: Fix space between type, * and variable name
Fix the following errors detected by checkpatch.pl:

ERROR: "foo * bar" should be "foo *bar"
ERROR: "foo* bar" should be "foo *bar"
ERROR: "foo*bar" should be "foo *bar"

TEST=Build and run on Galileo Gen2

Change-Id: I5a3ff8b92e3ceecb4ddf45d8840454d5310fc6b3
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18655
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2017-03-13 17:18:37 +01:00
Lee Leahy 35af5c47b0 src/lib: Fix spacing
Fix the following errors and warnings detected by checkpatch.pl:

ERROR: spaces required around that '?' (ctx:WxV)
ERROR: spaces required around that '=' (ctx:VxV)
ERROR: spaces required around that '<' (ctx:VxV)
ERROR: spaces required around that '+=' (ctx:VxV)
ERROR: space required after that ',' (ctx:VxV)
ERROR: space required before the open brace '{'
ERROR: space required after that close brace '}'
ERROR: need consistent spacing around '+' (ctx:WxV)
ERROR: need consistent spacing around '*' (ctx:WxV)
ERROR: need consistent spacing around '&' (ctx:VxW)
ERROR: spaces required around that '?' (ctx:VxW)
ERROR: spaces required around that ':' (ctx:VxW)
ERROR: trailing whitespace
ERROR: space prohibited before that '++' (ctx:WxO)
ERROR: space prohibited before that ',' (ctx:WxW)
ERROR: space prohibited after that '!' (ctx:BxW)
ERROR: spaces prohibited around that '->' (ctx:VxW)
ERROR: space prohibited after that '-' (ctx:WxW)
WARNING: space prohibited before semicolon
WARNING: unnecessary whitespace before a quoted newline
WARNING: missing space after return type

Note that lib/libgcov.c and lib/lzmadecode.c are providing false
positives for ERROR: need consistent spacing around '*' (ctx:WxV)
An example is:
void __gcov_merge_add(gcov_type *counters  __attribute__ ((unused)),
      unsigned int n_counters __attribute__ ((unused))) {}

TEST=Build and run on Galileo Gen2

Change-Id: I0016327a5754018eaeb25bedf42338291632c7c1
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18733
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13 17:16:08 +01:00
Nicola Corna fece39baa5 nvramcui: Add USB support
Enable the USB during the initialization of nvramcui. Without it
the USB keyboards don't work, which makes this payload pointless
on the systems where a PS/2 keyboard port isn't available.

Based on https://review.coreboot.org/#/c/17507/

Change-Id: I04697c5f582b41e6f6ffe98955bf59f4fe57f66e
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/18765
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-03-13 17:11:12 +01:00
Nicola Corna 4fbd1aab33 util/superiotool: Add support for Fintek F71808A
Default values taken from the datasheet and from the dump of
an uninitialized F71808A on a Sapphire Pure Platinum H61.

Both the control registers and the HWM configuration registers
are added.

Change-Id: Ia6e2a7c13a5086d19ebdb426f2f975b43220a273
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/18562
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2017-03-13 17:10:02 +01:00
Lee Leahy 8fbd953ffb soc/intel/common: Remove parenthesis
Fix the following error detected by checkpatch.pl:

ERROR: return is not a function, parentheses are not required

TEST=Build and run on Galileo Gen2

Change-Id: Idf7723d4fd48124a26bbb626afc310820f859f66
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18757
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-13 17:09:02 +01:00
Lee Leahy 20727813bb soc/intel/common: Fix unsigned warnings
Fix the following warning detected by checkpatach.pl:

WARNING: Prefer 'unsigned int' to bare use of 'unsigned'

TEST=Build and run on Galileo Gen2

Change-Id: Ic266c077eb115e0c7d934c15bcc4cc9b9e530a39
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18756
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-13 17:08:51 +01:00
Lee Leahy 68ab0b5d1f soc/intel/common: Fix spacing issues
Fix the following errors detected by checkpatch.pl:

ERROR: spaces required around that '=' (ctx:VxV)
ERROR: spaces required around that ':' (ctx:VxW)
ERROR: space required after that ',' (ctx:VxV)
ERROR: space required before the open parenthesis '('
ERROR: switch and case should be at the same indent
ERROR: "foo ** bar" should be "foo **bar"

TEST=Build and run on Galileo Gen2

Change-Id: I52ba2a3c1e0fffad7145eecd878aba8dc450ac0b
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18755
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-13 17:08:34 +01:00
Lee Leahy 42e605be19 soc/intel/common: Indent code with tabs
Fix the following error detected by checkpatch.pl:

ERROR: code indent should use tabs where possible

TEST=Build and run on Galileo Gen2

Change-Id: I61c4f01216cb6c788cf6da988c414bbb9648d502
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18754
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-13 17:08:22 +01:00
Lee Leahy e20a3191f5 src/lib: Use tabs instead of spaces
Fix the following errors and warnings detected by checkpatch.pl:

ERROR: code indent should use tabs where possible
ERROR: switch and case should be at the same indent
WARNING: Statements should start on a tabstop
WARNING: please, no spaces at the start of a line
WARNING: please, no space before tabs
WARNING: suspect code indent for conditional statements
WARNING: labels should not be indented

TEST=Build and run on Galileo Gen2

Change-Id: Iebcff26ad41ab6eb0027b871a1c06f3b52dd207c
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18732
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13 15:46:02 +01:00
Shobhit Srivastava cdd7686a9d google/poppy: Enable internal pull-up on PWRBTN#
Enable an internal pull-up on the power button input as short
press is resulting in power button override being asserted.

BUG=b:36111214
BRANCH=none
TEST=tested on poppy board to ensure quick power button press does
not result in a shutdown due to power button override.

Change-Id: I3a25b78562e2302b6f7575e64c87ae8142690701
Signed-off-by: Shobhit Srivastava <shobhit.srivastava@intel.com>
Reviewed-on: https://review.coreboot.org/18734
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-12 21:31:51 +01:00
Lee Leahy 38768c328a src/lib: Remove space between function name and (
Fix the following warning detected by checkpatch.pl:

WARNING: space prohibited between function name and open parenthesis '('

TEST=Build and run on Galileo Gen2

Change-Id: I8f3c79302dc5eb1861ffb245617a27addf8653ef
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18731
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-12 19:20:21 +01:00
Lee Leahy b6ee0f9d92 src/lib: Move trailing statements to next line
Fix the following error detected by checkpatch.pl:

ERROR: trailing statements should be on next line

The remaining error is a false positive in libgcov.c where the if
statement spans several lines with conditional compilation directives
intertwined.

TEST=Build and run on Galileo Gen2

Change-Id: I37fcef78e9323340bac1367ae1c5fde334f5ce10
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18730
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-12 19:19:07 +01:00
Lee Leahy bfdb8937b2 src/include: Remove braces for single statements
Fix the following warning detected by checkpatch.pl:

WARNING: braces {} are not necessary for single statement blocks

TEST=Build and run on Galileo Gen2

Change-Id: I00b59f6a27c3acb393deaa763596363b7e958efd
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18654
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-12 15:47:06 +01:00
Lee Leahy 6625ecc344 src/include: Open brace on same line as enum or struct
Fix the following errors and warning detected by checkpatch.pl:

ERROR: open brace '{' following enum go on the same line
ERROR: open brace '{' following struct go on the same line
ERROR: that open brace { should be on the previous line
WARNING: missing space after struct definition

TEST=Build and run on Galileo Gen2

Change-Id: I856235d0cc3a3e59376df52561b17b872b3416b2
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18653
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-12 15:46:23 +01:00
Lee Leahy 84d20d0eb3 src/include: Remove spaces before tabs
Fix the following warning detected by checkpatch.pl:

WARNING: please, no space before tabs

TEST=Build and run on Galileo Gen2

Change-Id: If60a58021d595289722d1d6064bea37b0b0bc039
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18652
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-12 15:45:37 +01:00
Lee Leahy 91d1e76fd1 src/include: Remove spaces before ( and after )
Fix the following error messages found by checkpatch.pl:

ERROR: space prohibited after that open parenthesis '('
ERROR: space prohibited before that close parenthesis ')'

TEST=Build and run on Galileo Gen2

Change-Id: I2a9a0df640c51ff3efa83dde852dd6ff37ac3c06
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18651
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-12 15:45:26 +01:00
Paul Menzel 4eb155cee4 lenovo/t400/dock.c: Fix issues found by checkpatch.pl
Change-Id: If7ebab8af1ae0c048cb89c2feb5f6a65848b6952
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/18767
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-03-11 17:43:17 +01:00
Kyösti Mälkki 9ab5adbde4 lenovo/t400: Rewrite dock from t60
Old dock.c copied from x201 was incorrect. Do a rewrite of t60 dock
code as pnp devices.

Fixes USB and serial on the dock, if it is already connected when
computer is powered on. DVI and ethernet worked without this patch.

Hot-plug is yet to be fixed.

Change-Id: Ib20a0eff10d0cde92dd089baf4fca28b117dc999
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18054
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-03-11 13:31:41 +01:00
Lee Leahy f3d07f274e src/include: Add space after +
Fix the following error detected by checkpatch.pl:

ERROR: need consistent spacing around '+' (ctx:WxV)

Test: Build and run on Galileo Gen2

Change-Id: Idd5f2a6d8a3c8db9c1a127ed75cec589929832e3
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18650
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-10 22:29:01 +01:00
Lee Leahy f00e446e74 src/include: Add parenthesis around macros
Fix the following error found by checkpatch.pl:

ERROR: Macros with complex values should be enclosed in parentheses

False positives are detected for attribute macros.  An example is:

ERROR: Macros with complex values should be enclosed in parentheses
+#define BOOT_STATE_INIT_ATTR  __attribute__ ((used, section
(".bs_init")))

False positive also generated for macros for linker script files.  An
example is:

ERROR: Macros with complex values should be enclosed in parentheses
+#define CBFS_CACHE(addr, size) \
+	REGION(cbfs_cache, addr, size, 4) \
+	ALIAS_REGION(cbfs_cache, preram_cbfs_cache) \
+	ALIAS_REGION(cbfs_cache, postram_cbfs_cache)

False positives generated for assembly code macros.  An example is:

ERROR: Macros with complex values should be enclosed in parentheses
+#define DECLARE_OPTIONAL_REGION(name) asm (".weak _" #name ", _e" #name
)

False positive detected when macro includes multiple comma separated
values.  The following code is from src/include/device/azalia_device.h:

#define AZALIA_SUBVENDOR(codec, val)		    \
	(((codec) << 28) | (0x01720 << 8) | ((val) & 0xff)),	\
	(((codec) << 28) | (0x01721 << 8) | (((val) >> 8) & 0xff)), \
	(((codec) << 28) | (0x01722 << 8) | (((val) >> 16) & 0xff)), \
	(((codec) << 28) | (0x01723 << 8) | (((val) >> 24) & 0xff))

TEST=Build and run on Galileo Gen2

Change-Id: I6e3b6950738e6906851a172ba3a22e3d5af1e35d
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18649
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-10 22:28:35 +01:00
Lee Leahy 86f60a9c8f src/include: Add space before (
Fix the following error detected by checkpatch.py:

ERROR: space required before the open parenthesis '('

TEST=Build and run on Galileo Gen2

Change-Id: I6969e63f750f327afff1a0efa1aab56d477af0df
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18645
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-10 22:28:14 +01:00
Lee Leahy 36d5b41e62 commonlib: Remove space after *
Fix the following error detected by checkpatch.pl:

ERROR: "foo * bar" should be "foo *bar"

TEST=Build and run on Galileo Gen2

Change-Id: If68dfa2b49c61d574f35192f94d1a6642069fa7f
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18752
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2017-03-10 22:27:51 +01:00
Lee Leahy 72c60a472b commonlib: Fix issues with { } and else
Fix the following errors and warning detected by checkpatch.pl:

ERROR: open brace '{' following struct go on the same line
ERROR: else should follow close brace '}'
WARNING: else is not generally useful after a break or return

False positives are detected for the following checkpatch.pl error.
ERROR: that open brace { should be on the previous line
These false positives are in cbfs.c for two function definitions.

TEST=Build and run Galileo Gen2

Change-Id: Ic679ff3a2e1cfc0ed52073c20165e05bf21d76f3
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18750
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2017-03-10 22:27:18 +01:00
Lee Leahy f339973d6f commonlib: Wrap lines at 80 columns
Fix the following error detected by checkpatch.pl:

ERROR: code indent should use tabs where possible

TEST=Build and run on Galileo Gen2

Change-Id: I3a44a02d4cd1be6b2bb2f52fc832e673a580e562
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18749
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2017-03-10 22:27:02 +01:00
Lee Leahy d5a2a292b0 commonlib: Fix spacing issues
Fix the following errors and warnings detected by checkpatch.pl:

ERROR: space required after that ',' (ctx:VxV)
ERROR: space required after that ';' (ctx:VxV)
ERROR: space prohibited after that open parenthesis '('
ERROR: space prohibited before that close parenthesis ')'
WARNING: please, no spaces at the start of a line
WARNING: please, no space before tabs

TEST=Build and run on Galileo Gen2

Change-Id: I54877f60eb5fdf3f6d8729711c55ff5a284d22cf
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18748
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2017-03-10 20:30:16 +01:00
Lee Leahy ce46c5b6a1 drivers/intel/fsp2_0: Switch from binary to decimal
Fix the following warning detected by checkpatch.pl:

WARNING: Avoid gcc v4.3+ binary constant extension:

TEST=Build and run on Galileo Gen2

Change-Id: Ied50b94ecae4d3bde5812f6b54bbe2421fd48588
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18747
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-10 20:08:46 +01:00
Lee Leahy 7732b35fb7 drivers/intel/fsp2_0: Wrap lines at 80 columns
Fix the following warning detected by checkpatch.pl:

WARNING: line over 80 characters

TEST=Build and run on Galileo Gen2

Change-Id: I0e5acef53d558948b7713cfe608cd346ddc5e9fe
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18746
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-10 20:08:23 +01:00
Lee Leahy e686ee8bf7 drivers/intel/fsp2_0: Remove braces for single statements
Fix the following warning detected by checkpatch.pl:

WARNING: braces {} are not necessary for single statement blocks

TEST=Build and run on Galileo Gen2

Change-Id: Ibd351703e60acebbacd6ae5b1a2fa1cb34fd3ff9
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18745
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-10 20:08:02 +01:00
Lee Leahy b2b97a5db2 drivers/intel/fsp2_0: Fix spacing issues
Fix the following errors detected by checkpatch.pl:

ERROR: space prohibited before that close parenthesis ')'
ERROR: space required before the open parenthesis '('
ERROR: space prohibited before open square bracket '['
ERROR: spaces required around that ':' (ctx:VxE)

TEST=Build and run on Galileo Gen2

Change-Id: I085aaaa9e276c60eded6edf3be0325ed2402702a
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18744
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-10 20:07:45 +01:00
Lee Leahy 27de768112 drivers/intel/fsp2_0: Add space before *
Fix the following error detected by checkpatch.pl:

ERROR: "(foo*)" should be "(foo *)"

False positives are generated by checkpatch for the following condition
which is not properly detecting the variable type:
ERROR: need consistent spacing around '*' (ctx:WxV)
The false positives are found in debug.h and upd_display.c

TEST=Build and run on Galileo Gen2

Change-Id: I0e871d64544ebf5eacbae46466cf7aefbfa701eb
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18743
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-10 20:07:08 +01:00
Lee Leahy 30bdb52e4c drivers/intel/fsp2_0: Use tabs for indent
Fix the following warning detected by checkpatch.pl:

WARNING: please, no spaces at the start of a line

TEST=Build and run on Galileo Gen2

Change-Id: I7cb35c8b5d7ff97849e666ce7f75d4e4763bb2a7
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18742
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-10 20:06:49 +01:00
Barnali Sarkar 6497cd9744 soc/intel/common: Pass the minimum possible string length for strncpy
In strncpy() function of dimm_info_fill(), the minimum possible size
of Module Part Number of DIMM is passed as argument.

BUG=chrome-os-partner:61729
BRANCH=none
TEST=Build and boot KBLRVP to verify the type 17 DIMM info coming in
SMBIOS Table from Kernel command "dmidecode".

Change-Id: Icc7667149eae9705b91e271628af1b443eb8556e
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/18617
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-10 19:59:58 +01:00
Katherine Hsieh 674c089922 google/sand: Add devicetree.cb file for sand
It is a copy from baseboard/devicetree.cb  (coreboot.org ToT)

BUG=b:35775065
BRANCH=reef
TEST=emerge-sand coreboot

Change-Id: I5ba86e54ccfbf5af7bf0e9ad8fe7bf22020e48ee
Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com>
Reviewed-on: https://review.coreboot.org/18703
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-10 19:48:48 +01:00
Tim Chen 327c5c60dd mainboard/google/reef: Modify TCPU, TSR2 and TRT table
Update the DPTF parameters based on thermal test result.
(ZHT_DPTF_EVT2_v0.5_20170306.xlsx)

1. Update DPTF TCPU critical trigger point.
   TCPU critical point: 105

2. Update DPTF TSR2 passive trigger point.
   TSR2 passive point: 58

3. Change thermal relationship table (TRT) setting.
   Change CPU Throttle Effect on CPU sample rate to 10secs.
   Change Charger Effect on Temp Sensor 2 sample rate to 30secs.
   Change CPU Effect on Temp Sensor 2 sample rate to 60secs.

BUG=b:35583586
BRANCH=master
TEST=build and boot on electro dut

Change-Id: I85564ccdaf327eeaa13bf1f31d9a933609a21582
Signed-off-by: Tim Chen <Tim-Chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/18610
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-10 19:48:08 +01:00
Nico Huber e392f414cd soc/intel/broadwell: Rework IGD's CDClk selection
CDClk selection was wrong in some corner cases (e.g. ULX SKUs) and,
for Broadwell, never took the devicetree config into account.

Rewrite the selection with the following in mind:

  o cpu_is_ult() might return `true` for ULX SKUs, too,

  o ULX and Broadwell-ULT SKUs can be `overclocked` with additional
    cooling, so leave that as devicetree option.

For Haswell, the following frequency selections are valid:

  o ULX: 337.5MHz by default, 450MHz optional
  o ULT: 450MHz only (maybe 337.5MHz too, documentation varies,
                      it wasn't selectable before either)
  o others: 540MHz by default, 450MHz optional

For Broadwell:

  o ULX: 450MHz by default, 337.5MHz / 540MHz optional
  o ULT: 540MHz by default, 337.5MHz / 450MHz / 675MHz optional
  o others: 667MHz by default, 337.5MHz / 450MHz / 540MHz optional

Side effects: A too high setting in the devicetree results in the
highest possible frequency now, Haswell non-ULT/ULX defaults to 540MHz
instead of 450MHz.

Change-Id: Iec12752f2a47bf4a5ae6077c75790eae9378c1b2
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/17768
Tested-by: build bot (Jenkins)
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-03-10 17:39:46 +01:00
Hannah Williams 589fc3473e ifdtool: Add SPI_FREQUENCY_50MHZ_30MHZ as a valid freq
Without this change, error "Unknown descriptor version: 4" will be
returned if this frequency is selected (seen on GLKRVP)

Change-Id: Ib5bfb996b85c7245d8f9c70988bfd5bbac882d74
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/18688
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2017-03-10 11:20:39 +01:00
sowmyav d448a5e98b soc/intel/skylake:Add _DSM method to reduce D3 cold delay for eMMC controller
eMMC Controller is taking over 100ms to resume during runtime which
results in I/O latency issues on the Skylake systems like Cave and Caroline.

This patch adds _DSM method for eMMC comtroller for specifying the
device readiness durations. Function index 9 returns package of five
integers to set D3 cold delay to zero and ACPI constant Ones for the
elements where overriding the default values is not desired.

BUG=b:35774937
BRANCH=none
TEST=update caroline coreboot and test i/o latency is under 100ms

Change-Id: Iacc8aa8560897da8770fe559ca8cd17aaf6ebeba
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/18532
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-03-10 11:19:04 +01:00
Patrick Rudolph 6e53ae6f5c device/dram/ddr2: Add common ddr2 spd decoder
Decode DDR2 SPD similar to DDR3 SPD decoder to ease
readability, reduce code complexity and reduce size of
maintainable code.

Rename dimm_is_registered to spd_dimm_is_registered_ddr3 to avoid
compilation errors.

Change-Id: I741f0e61ab23e3999ae9e31f57228ba034c2509e
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18273
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins)
2017-03-10 11:17:27 +01:00
Venkateswarlu Vinjamuri 7e4d12c5b1 mainboard/google/reef: Configure SDCARD card detect pin
This configures GPIO_177 as an input pin for SDCARD card
detect. This also changes the ownership of the pin from ACPI
to GPIO driver.

Assign the sdcard card detect pin in devicetree for reef variants.

CQ-DEPEND=448173
BUG=chrome-os-partner:63070
TEST=None

Change-Id: Ia8aef60bd7d0ea36afb39f76fab051aa46a2ed64
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/18497
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-10 11:12:08 +01:00
Venkateswarlu Vinjamuri 6dd7b402d5 soc/intel/apollolake: Add PM methods to power gate SD card
This implements dynamic generation of sdcard GpioInt in SSDT.
GpioInt in SSDT generation is based on the card detect GPIO if
it is provided by the mainboard in devicetree.

This implements GNVS variable to store the address of sdcard cd pin.
GNVS used to store rxstate of the sdcard cd pin to get card presence.

Add _PS0/_PS3 methods to power gate the sd card controller in
S0ix and runtime PM.

CQ-DEPEND=448173
BUG=chrome-os-partner:63070
TEST=Suspend and resume using 'echo freeze > /sys/power/state'.
System should enter S0ix and resume with no issue.

Change-Id: Id2c42fc66062f0431385607cff1a83563eaeef87
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/18496
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
2017-03-10 11:11:13 +01:00
Paul Menzel d4f92fa603 asus/m2v: Make _CRS methods serialized
Address the iasl 20160108-64 (Ubuntu 16.04) warnings below.

```
Intel ACPI Component Architecture
ASL+ Optimizing Compiler version 20160108-64
Copyright (c) 2000 - 2016 Intel Corporation

dsdt.aml    245:      Method (_CRS, 0, NotSerialized)
Remark   2120 -                 ^ Control Method should be made Serialized (due to creation of named objects within)

dsdt.aml    262:      Method (_CRS, 0, NotSerialized)
Remark   2120 -                 ^ Control Method should be made Serialized (due to creation of named objects within)

dsdt.aml    277:      Method (_CRS, 0, NotSerialized)
Remark   2120 -                 ^ Control Method should be made Serialized (due to creation of named objects within)

dsdt.aml    295:    Method(_CRS, 0) {
Remark   2120 -              ^ Control Method should be made Serialized (due to creation of named objects within)
```

Change-Id: Id5b0f33fba8ea25e4a6aa4f01c69a69aaf5aef23
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/18323
Tested-by: build bot (Jenkins)
Reviewed-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-10 11:07:25 +01:00
Paul Menzel 22f32c723c cpu/amd/agesa: Unify init files
The init files for the AMD families using the AGESA platform
initialization code are quite similar. So reduce the differences, by
using the same comments, variable names, console messages, and blank
lines.

Change-Id: Id4a3a5c3812a34627d726cdcbe8f4781a14be724
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/18507
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-03-10 11:06:56 +01:00
Alexander Couzens dd6f75ae6e .gitignore: ignore *.swo and option *.roms
Change-Id: I7403f548bae918ca813a9295bfb095a7c4c51e21
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/15220
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-10 11:06:20 +01:00
Paul Menzel 7c414e78cc northbridge/intel/i440bx: Align code
Change-Id: Idd4127f7491524121b4b65c6fb9511e2c8159912
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/18609
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-10 11:06:04 +01:00
Aaron Durbin eeb77379e0 vboot/tpm2: enable nvmem commits on cr50 when writing firmware secdata
cr50 by default delays nvmem commits internally from the point of
reset to accumulate change state. However, the factory process can
put a board into dev mode through the recovery screen. This state
is stored in the TPM's nvmem space. When the factory process is
complete a disable_dev_request and battery_cutoff_request is performed.
This leads to disabling the dev mode in TPM, but the battery is
subsequently cut off so the nvmem contents never stick. Therefore,
whenever antirollback_write_space_firmware() is called we know there
was a change in secdata so request cr50 to immediately enable nvmem
commits going forward. This allows state changes to happen immediately.

The fallout from this is that when secdata is changed that current
boot will take longer because every transaction that writes to TPM
nvmem space will perform a write synchronously. All subsequent boots
do not have that effect.

It should also be noted that this approach to the implementation is
a pretty severe layering violation. However, the current TPM APIs
don't lend themselves well to extending commands or re-using code
outside of the current routines which inherently assume all knowledge
of every command (in conflict with vendor commands since those are
vendor-specific by definition).

BUG=b:35775104
BRANCH=reef
TEST=Confirmed disablement of dev mode sticks in the presence of:
crossystem disable_dev_request=1; crossystem
battery_cutoff_request=1; reboot;

Change-Id: I3395db9cbdfea45da1f5cb994c6570978593b944
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/18681
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
2017-03-09 19:15:03 +01:00
Aaron Durbin 1b9fc9e801 drivers/spi/tpm: provide Kconfig to indicate CR50 usage
Going forward it's important to note when a CR50 is expected
to be present in the system. Additionally, this Kconfig addition
provides symmetry with the equivalent i2c Kconfig option.

BUG=b:35775104

Change-Id: Ifbd42b8a22f407534b23459713558c77cde6935d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/18680
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2017-03-09 19:14:49 +01:00
Aaron Durbin 7c7a477c5b mainboard/google/reef: increase pre cbmem console size for Chrome OS
verstage can be pretty chatty so bump the pre cbmem console size
when building for Chrome OS so that all messages can be observed.

BUG=b:35775104
BRANCH=reef
TEST=Booted and noted no cutoff of console when sec data being saved.

Change-Id: I0ce2976572dedf976f051c74a3014d282c3c5f4c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/18679
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-09 19:14:37 +01:00
Aaron Durbin 06f12f919f lib/tpm2_marshaling: fix in correct buffer space semantics
marshal_blob() was setting an unsigned size (size_t) to a value
of -1 when an error is determined. This is wrong for the current
implementation of the code because the code assumes the buffer
space gets set to 0. Setting an unsigned value to -1 effectively
tells the library the buffer has unlimited amount of space.

BUG=b:35775104

Change-Id: I677a1fd7528bef3ea7420d0a8d0a290e9b15cea3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/18678
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2017-03-09 19:14:25 +01:00
Naresh G Solanki 3487e118d1 google/poppy: Configure SRCCLKREQ4 as No Connect
SRCCLKREQ4 is unused, so configure SRCCLKREQ4 as NC (No Connect).

Change-Id: I6e265b9c9faa0df20208bb82278cadbbbbe6c537
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/18589
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-09 19:08:32 +01:00
Furquan Shaikh 644f1dc0f3 elog: Add all EC event codes
Add the missing EC event codes in elog.h and correct the event code value for
RECOVERY_HWREINIT.

Change-Id: If9fb319cce1e4acce4b3d7c3a39365986856a9b4
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18693
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-09 18:04:50 +01:00