Add EC entries into chromeos.fmd file.
BRANCH=None
BUG=None
TEST=Flash image and confirm system can get out of reset successfully.
System will not be able to reach reset vector if flash map described in
coreboot does not match intel flash map generated from fit.
Change-Id: Ic18ce59941b4ff8171fe661d332e3e521d988341
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21526
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Setup cyan to be the baseboard for other Google Braswell
boards, to be added in subsequent commits:
- Keep code common to all Google Braswell boards in the baseboard,
and separate out the board-specific bits into the new cyan variant.
- Define the I2C ACPI devices such that they can be easily reused for
other variants.
- Switch the trackpad/touchscreen interrupts from edge to level,
for better performance/compatibility, as was done with all previous
Google boards.
- Add code to the baseboard to allow optional variant-specific
parameters to be used for both memory and silicon init.
- Remove superfluous includes, replace some hardcoded values with
variables, and correct typos/formatting errors.
Change-Id: Iabbbad16efa9cfa79338f4e94d0771779900d8d9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There are old legacy onboard devices which are too slow for a coreboot
boot with log level BIOS_ERR. In this case coreboot is so fast that these
devices do not have enough time to become visible on the PCI bus and
this in turn leads to missing resource allocation for this devices. The
most generic way to work around this problem on existing hardware is to
introduce a delay right before the PCI enumeration starts. The needed
delay time depends on the hardware and will therefore be get from
hwinfo.
Change-Id: Ia91babc81e3a347bbc498c3def97b2ea70e10922
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/21518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
All thse Option.*Install.h files are about configuring
what eventually is referenced in the final libagesa
build. It's self-contained so isolate these together
with PlatformInstall.h to hide them from rest of
the build.
Change-Id: Id9d90a3366bafc1ad01434599d2ae1302887d88c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fine tune usb 2.0 strength for port 4 to pass eye diagram.
BUG=b:65306272
TEST=build on soraka, measure usb2.0 eye diagram, and result is pass.
Change-Id: I2c79e96e2e3dea1364d7b71af19b57f4c9307fcb
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/21403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
These two boards have been boot tested with EARLY_CBMEM_INIT
and is good to go.
Change-Id: I2e69901ed83502894f6794b3c1d7bab9aab95e51
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21351
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This board uses the reset defaults for DxxIP and DxxIR.
The datasheet "Intel ® I/O Controller Hub 10 (ICH10) Family"
mistakenly says in the D31IP register that all function have INTB as
default. This is however not true as documented in the reset default
value.
This fixes the DSDT such that the SMBus device gets a route for the
INT C interrupt it uses.
Change-Id: I3dd1308fb7acec86b90ecd9d2079cf9a58702c40
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21442
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TESTED: NGI works on VGA with adapter on DVI-I port
Change-Id: I4bd9d451295d26a3e11ded9863f5d45d42c8fead
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This makes the VGA output on the DVI-I connector usable.
This reuses vendor settings.
Change-Id: Ib8b6bf33816f7e468a09ff5e2008c2cb9f7c0a8b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
For boards with cimx/sb800, mainboards defined only empty
stubs. Reset functionality is handled as BiosCallout.
For amd/inagua, the defined function was actually initial
GPIO programming.
For cimx/sb700, function had prototypes but no callers.
For cimx/sb900, everything was commented out already.
Change-Id: I936feb4fc41d903078620c919a733bb9f39c3efb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add support for BDC detection, based on the schematics for each board.
Support for boards without schematics needs further testing.
Needs test on all boards.
Change-Id: If33ef88fb808f36b050393fa83eb1b541ce936b9
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
The RO_VPD region is required for ChromeOS.
BUG=b:65408869
TEST=Build and check coreboot.rom with fmap_decode.
Change-Id: I9c475acc5e34a3a41f815990fb1f363963c7b9b9
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
APL internal UARTs are not used on this mainboard.
Change-Id: I39118262fc6f37b45785538a3f2d1d31d42cbe86
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/21406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
There is one on-board PCI device where bus master has to be enabled in
PCI configuration space. As there is no need for a complete PCI driver
for this device just set the bus master bit in mainboard_final().
Change-Id: I45202937eba11da3bea14fef6ebed70599804335
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/21405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
We've decided to move control for the 3.0V rail (technically 3.3V on
Scarlet, but who cares about millivolts) back to a GPIO on the AP for
Scarlet rev2. This patch adds the necessary code to enable it and make
ARM TF aware of its existence. Since the pin had previously not been
connected to anything, we shouldn't really need to guard this by board
ID... older Scarlets will just be twiddling an empty pin.
Change-Id: I6037aa486b50119f2c7b859b966cadc3686e3459
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/21328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
Vendorcode expects some DRAM controller registers to
be writable, but they are actually locked after soft
resets if C6 states are enabled.
Without the workaround, raminit fails on soft resets.
Change-Id: I6b9e275e11b2907d026c13341334983a4d9c8889
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It's too critical to ignore when sending the message on
SMBus fails, so allow for a fair amount of retries.
Failure here causes watchdog to do hard reset later.
Move it out of mainboard.c as we need to call this
early in romstage while we are debugging.
Change-Id: I1006b079269d6dd44de630db7a5694124af2f974
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix regression caused by commit
9e94dbf ACPI: Get S3 resume state from romstage_handoff
Boards with EARLY_CBMEM_INIT are required to provide
romstage_handoff structure to signal S3 resume path.
Change-Id: I7c9065ccc48dfbdefade698ed275756f17dff7a0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix regression caused by commit
9e94dbf ACPI: Get S3 resume state from romstage_handoff
Boards with EARLY_CBMEM_INIT are required to provide
romstage_handoff structure to signal S3 resume path.
Change-Id: I464feb1655a51a937b6cf53508dd5c7aa0d8f791
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Fix regression caused by commit:
714709f AMD fam10 ACPI: Use common fixed sleepstates.asl
Adding common sleepstates.asl got lost in rebase process.
Change-Id: I4f22ee950ae5637113db8e79ca238cb1b81002aa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This patch adds imon and vmon slot numbers for Maxim 98927 driver.
These values are used to confiure IV feedback for audio playback on speakers.
BUG=b:36724448
TEST=After boot, the register dump for Max98927 codecs should have
imon and vmon slots numbers set in 0x1e register.
Change-Id: I4382da4f984507d147751c168e8177b58c88a70f
Signed-off-by: Harsha Priya <harshapriya.n@intel.com>
Reviewed-on: https://review.coreboot.org/21196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This reverts commit 6c0f3c7ee1.
Reason for revert:
Broke master builds, this was submitted out-of-order, some
of the dependencies have not passed review with +2 yet.
Change-Id: Ib7bcb1b98623d16e074caeca839a936d71ded709
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
There is no serial port on this platform.
In addition, put the LPC serial IRQ into quiet mode.
Change-Id: I4b2c93c51e8ddb8b510f0d7f7e3072befeba5d95
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/21226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The deprecation of late (post-romstage) CBMEM initialization was
announced in this blog post:
https://blogs.coreboot.org/blog/2017/05/08/announcing-coreboot-4-6/
There are two warnings:
* In LATE_CBMEM_INIT's help text, I've added a multi-line warning, that
aims to explain the problem.
* In src/mainboard/Kconfig (just below the mainboard selection), there's
a warning which points the user at LATE_CBMEM_INIT, if such a board is
selected.
Also update the function that needs to be implemented, as pointed out by
Keith Hui and Kyösti Mälkki.
Change-Id: I2d21a6ab2fc2811d44fc4febb05841bb2f8d1857
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
08f7d1ae0d ("mainboard/via*: Drop AMD car.h file") did the same for all
Via mainboards that were in tree at that time, but the winnet/g170 was
merged a bit later.
Change-Id: Iedb33f4c2fce6fc2cf2669fee4ffb25bf793c92b
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Currently PMIC (tps68470) is in active state even when cameras are not
in use. PMIC is put into SLEEP mode only when entering S3 via
smihandler.
With this change PMIC will be put into SLEEP mode as soon as sensors &
VCM voltage outputs are turned off. This will allow run time power
saving when camera is not in use.
PMIC will be reset in first boot & across S3 & S0ix cycles.
Also, remove the smi handler for PMIC power management & handle it as
part of sensor and VCM ACPI PowerResource.
BUG=b:63903239
TEST= Build for Soraka. Check Camera probe, Capture image across
S3 & S0ix cycles.
Also checked the following & found no regression:
1. Typical camera use cases
2. Stability tests related to camera
3. Reliability tests related to camera
4. PnP tests related to camera
5. Latency related tests with camera
Change-Id: I23b0c0a887c9eb5d29b89f14aebba273b01228e0
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/20741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The Harcuvar CRB is a reference platform of Intel Atom C3000 SoC
("Denverton" and "Denverton-NS") for the communications segment/market.
The MohonPeak coreboot was used as the starting template with
additions/modifications from other Intel Apollo Lake/Skylake coreboot.
Tested with TianoCore payload (UDK2015) and Poky (Yocto
Project Reference Distro) 2.0 with kernel 4.1.8 booted from
SATA drive and external USB pendrive.
Change-Id: I088833e36e2d22d1fe1610b8dca1454092da511a
Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com>
Reviewed-on: https://review.coreboot.org/20862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
This patch adds the DPTF settings specfic to the mainboard and enables
the CPU and other thermal sensors as participant device for fizz.
It also enables the DPTF flag in the device tree for fizz.
BUG=b:64915426
BRANCH=None
TEST=emerge-fizz coreboot and run DPTF observation tool to make sure
DPTF is up and running.
Change-Id: Ic7d125a763f539158aa425fbba1d8a000a3465ca
Signed-off-by: Tsai, Gaggery <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/21147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
We have no wacom digitizer on I2C#3, so remove it.
TEST=build and boot on soraka.
Change-Id: I3f5a1b9ece6fc9a9443477c7a7aa77dbcdf6a703
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/21309
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The MPC.HPCE bit of the ExpressCard root port is not set in vendor
firmware, so autoport didn't generate the right pcie_hotplug_map to
support ExpressCard hotplug.
Also add comments for each PCIe root port.
Change-Id: Ic53e36a7192b9bfa8ff9fca57f4556e972e2611b
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/21310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Some of these will move to EARLY_CBMEM_INIT.
Change-Id: Ia969e30ad7097860180bd047eaf81859a42a747c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Keith Hui <buurin@gmail.com>
NOTE: Some code was currently left behind that may be
required for certain type of board reboots. A followup
patch will address this.
Change-Id: I8fb89fb82c3a3608bb84b29319eb793605538996
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
NOTE: Some code was currently left behind that may be
required for certain type of board reboots. A followup
patch will address this.
Change-Id: I3c1258b4e4dcf6fd04f57f5ab59cb1572a7d1fa3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Do not assert GPIO1_B3 otherwise BT would be disabled on Nefario.
Also, remove DVS support for CENTERLOGIC.
BUG=b:64702054, b:63537905
TEST=build coreboot
Change-Id: I350db2c080f2e41ae56413f5f895557978ef0ba8
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/21176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Enabling XHCI is additionally controlled with Kconfig
option HUDSON_XHCI_ENABLE. Even when it is enabled,
it EHCI debug works on the USB port next to the
DVD drive door.
Change-Id: I83738da6015f58ecd0819c553d333a176365dc78
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
