Commit Graph

44496 Commits

Author SHA1 Message Date
Eric Lai 0d6ad2638a mb/google/brya/var/felwinter: Correct SSD power sequence
M.2 spec describes PERST# should be sequenced after power enable.
Follow up commit 658d7c5

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I494e0edc135d730cf7bb437f0196cdf233d970d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-01 14:57:29 +00:00
David Wu 6c2d99f618 mb/google/brask/var/baseboard/brask: Update GPIO GPP_B5 and GPP_B6
Update GPIO GPP_B5 and GPP_B6 based on schematics.

BUG=b:197385770
TEST=build pass

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: If83e02eec7c48b9ab41d346aa8baef7c0c881df1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2021-10-01 14:08:46 +00:00
Werner Zeh b1e4a9a6c3 mb/siemens/mc_ehl: Move UART_FOR_CONSOLE switch to variant level
There are currently two variants for mc_ehl where different UARTs are
used for the console. Move the Kconfig switch UART_FOR_CONSOLE to the
Kconfig of the variant and select the matching value there.

Change-Id: I7152013a0e32ff151b92932a47953705e591dc0d
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58052
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-01 14:08:29 +00:00
Werner Zeh 264ace99e8 mb/siemens/mc_ehl: Add a new variant mc_ehl2
Add a new variant of the mc_ehl board called mc_ehl2. This patch just
copies the files and renames things where needed.
Following patches will adapt the needed features for this new variant.

Change-Id: I3ec3c091017fd66fe6a09216203cdc7c9e833846
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-10-01 14:07:41 +00:00
Werner Zeh 0bebcdb165 mb/siemens/mc_ehl1: Enable LPSS UART
Enable LPSS UART for coreboot console on mc_ehl1.

Change-Id: Id995953741d48fbbe2482ff7c0ef81cac5a31207
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-10-01 14:07:00 +00:00
David Wu 16e815fcad mb/google/brya/var/kano: Add Synaptics touchpad
Add Synaptics touchpad for kano.

BUG=None
TEST=emerge-brya coreboot and check touchpad function work.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Iec43aaa9525309d2a0e3c9822038869786f5fe66
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-01 01:38:03 +00:00
Julius Werner e55d2e13e0 arch/arm64: Remove unnecessary interfaces
<clocks.h> and smp_processor_id() aren't used anywhere anymore. Get rid
of them.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I1a8c892b066e6ac0e7cec5316633d44165344e78
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57819
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-10-01 00:02:06 +00:00
Julius Werner b5e7bd2a58 drivers/gic: Remove unnecessary code
On AArch64 platforms, GIC initialization is generally the job of Trusted
Firmware and shouldn't be necessary in coreboot. Only the ancient T210
platform (which was started before we had decided on using Trusted
Firmware) calls this code, and even there they have a comment wondering
"do we still need this?". I'm just gonna assume (without testing because
that board is ancient and I'm lazy) that they don't, and that the TF GIC
initialization[1] is sufficient here. Remove this obsolete driver.

[1] https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3ff448/plat/nvidia/tegra/soc/t210/plat_setup.c#259

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I3e9d90039dd27cb3a13f830ba21fc5cc7a70abe2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-10-01 00:01:56 +00:00
Aamir Bohra ee760b4be8 mb/amd/bilby: Use I2S TDM interface
Bilby uses I2S TDM interface for audio, instead of HDA interface.

Change-Id: I7c8ec02d0e63730cb54a27d3bea1d102e037823d
Signed-off-by: Aamir Bohra <aamirbohra@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: ritul guru <ritul.bits@gmail.com>
2021-09-30 13:54:46 +00:00
Angel Pons 5706a542e0 soc/intel/common/block/sgx: Fix typo in log message
The value printed is the EPC (Enclave Page Cache) status, but the printk
statement refers to it as `ECP status` instead. Fix the typo.

Change-Id: Iba0a6013f2c537072dd7aa8266f2be3c5b0963ed
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58038
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-30 13:46:02 +00:00
Meera Ravindranath f3c42825f3 soc/intel/alderlake: Add CPU ID 0x906a4
TEST=Build and boot brya

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I4342c7343876eb40c2955f6f4dd99d6346852dc0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
2021-09-30 13:37:57 +00:00
Selma Bensaid 4df35b6ec8 mb/intel/adlrvp_m: correct SSD power sequence
This is to fix SSD detectiong failure in warm boot observed
on ADL-M RVP. This patch implements the coreect power sequence:
SSD_PREST Low - SSD_PWR_EN High - SSD_PREST High

Signed-off-by: Selma Bensaid <selma.bensaid@intel.com>
Change-Id: If6f9fc17a30c28c2948809cdbade9919d4ddd6c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-09-30 13:37:00 +00:00
Subrata Banik 03aef28f16 soc/intel/common/../cse: Append the time units to the HECI macro names
Append `_MS` for miliseconds and `_US` for microseconds to HECI timeout
macros to improve the code readability.

Change-Id: Ic7f18f07ecaabb3e43356f372d15d18be083464b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-30 07:10:02 +00:00
Subrata Banik bee4bb5f0d soc/intel/common/cse: Late sending EOP msg if !HECI_DISABLE_USING_SMM
Pushing EOP msg post FSP notify helps to save ~30ms+ boot time across
various warm reboots.

This patch ensures late sending EOP msg when function disabling of CSE
is no longer a requirement.

BUG=b:200644229
TEST=Able to save ~30ms+ of boot time

Without this code change EOP sending timestamp as below:

943:after sending EOP to ME                     1,248,328(61,954))

With this code change EOP sending timestamp as below:

943:after sending EOP to ME                     1,231,660 (2,754)

Change-Id: I2b78a1c07803aacfb34dce9e94b2a05a2491aabc
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-30 07:08:03 +00:00
Subrata Banik a834a6eede soc/intel/alderlake: Perform `soc_finalize` at entry of BS_PAYLOAD_BOOT
This patch ensures soc_finalize() is getting called at the entry of
BS_PAYLOAD_BOOT boot state instead of BS_PAYLOAD_LOAD, BS_ON_EXIT.

The purpose of this change is to accommodate more time to push out
sending CSE EOP messages at post.

BUG=b:200644229
TEST=coreboot serial log suggests soc_finalize() is getting called
as part of the BS_PAYLOAD_BOOT entry.

Finalizing chipset.
apm_control: Finalizing SMM.
APMC done.
BS: BS_PAYLOAD_BOOT entry times (exec / console): 21 / 15 ms

Change-Id: I8632eca057255d7f4a38b64fd17c1f3d84123051
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2021-09-30 06:28:19 +00:00
Subrata Banik 37231fb2fe soc/intel/common/../cse: Perform D0I3 bit reset/set prior sending EOP
Prior to coreboot sending EOP messages during post, it's important to
ensure that CSE is not in Idle state. In case CSE is in Dev Idle
state (which means D0I3 bit is set), reset this bit before sending
EOP command.

This patch ensures coreboot has provision to send CSE EOP messages even
after the FSP Notify phase without any delays waiting for the device
to respond or timeout.

BUG=b:200644229
TEST=Able to send CSE EOP message even after FSP Notify phase.

Attempting CSE EOP msg sending post FSP notify without this code change
causes `timeout` issue as below:

BS: BS_PAYLOAD_LOAD exit times (exec / console): 171 / 0 ms
Finalizing chipset.
apm_control: Finalizing SMM.
APMC done.
HECI: Sending End-of-Post
HECI: timed out reading answer!
HECI: Failed to receive!
HECI: receive Failed
HECI: EOP send/receive fail
ERROR: Failed to send EOP to CSE, 2
cse: CSE status registers: HFSTS1: 0x90000255, HFSTS2: 0xf10516 HFSTS3:
0x20
VB2:vb2api_fail() Need recovery, reason: 0x31 / 0xc
Saving nvdata
board_reset() called!
full_reset() called!

Attempting CSE EOP msg sending post FSP notify with this code change
is `successful` as below:

BS: BS_PAYLOAD_LOAD exit times (exec / console): 170 / 0 ms
Finalizing chipset.
apm_control: Finalizing SMM.
APMC done.
HECI: Sending End-of-Post
CSE: EOP requested action: continue boot
CSE EOP successful, continuing boot

Change-Id: Iae1bc52e94b08f97004424ea0c147d6da8aca6e2
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-30 06:27:49 +00:00
Subrata Banik a219edb409 soc/intel/common/../cse: Create APIs for CSE device state transition
This patch ensures APIs that are responsible for CSE device state
transition between active to idle and vice-versa are available
publically for other modules/boot stages to consume.

BUG=b:200644229
TEST=Able to build and boot ADLRVP-P.

Change-Id: Ia480877822d343f2b4c9bf87b246812186d49ea3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-30 06:26:59 +00:00
Subrata Banik f72349d832 mb/intel/adlrvp: Update Rcomp target value for DDR4 RVP SKU
Update to recommended Rcomp drive strength value for DDR4 as per
MRC team's input.

Additionally, add space around the `targets` array.

Change-Id: Ied63913db94b2e52ab394a66c70f7edfd507d99a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-30 06:21:50 +00:00
Mark Hsieh dab8042257 mb/google/brya/variants/gimble: Correct SSD power sequence
M.2 spec describes PERST# should be sequenced after power enable.

BUG=b:201512872
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.

Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Ie164ddb29f947e190fa87b31165e3c84b07926e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58034
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-30 04:08:37 +00:00
Tim Wawrzynczak e281606720 soc/intel/cannonlake: Guard acpi_fill_ssdt assignment with HAVE_ACPI_TABLES
Change-Id: I3677b4e545599d00a4ba16464836834febc2d1a5
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58024
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-29 21:38:36 +00:00
Angel Pons 09fe826f87 soc/intel: Drop unnecessary `select REG_SCRIPT`
These platforms no longer use reg-script. Drop unneeded select.

Change-Id: I8fc4dc29d25dffbf9ed1947d0ff013b2fae0faaf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-29 21:37:35 +00:00
Angel Pons ebd43ae8a3 soc/intel/common/block/smbus: Drop reg-script usage
Using reg-script just to read-modify-write some registers makes no
sense. Replace reg-script usage with regular register operations.

Change-Id: I87d1278360a231cbe5b5f825ad9a448e59e63ea2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-29 21:36:19 +00:00
Angel Pons 72b8fd5a95 soc/intel/skylake: Drop reg-script usage
Using reg-script just to read-modify-write some registers makes no
sense. Replace reg-script usage with regular register operations.

Change-Id: Ib3c83131c30fd02c579b910cfad6843eb28ba8f1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-29 21:22:38 +00:00
Michael Niewöhner 38bf496366 soc/intel/{cnl,jsl,tgl,ehl,adl}: rename PMC device init/enable callbacks
The current names of the PMC init/enable callbacks are very confusing.
Rename them.

Change-Id: I69f54f3b4e1ea9a9b4fa5c8dd9c0d454d7cd1283
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-29 21:19:37 +00:00
Julius Werner f67f2b0d4c google/trogdor: Always initialize eDP bridge I2C QUP firmware
In CB:52662 when MIPI display support was added, we accidentally changed
the code flow for eDP displays such that i2c_init() will no longer be
called when display_init_required() is false. This is a problem because
on this platform, i2c_init() does not just prepare the I2C controller
for firmware use, it also loads firmware to the controller that makes it
behave like an I2C device in the first place -- a step that the kernel
cannot later do on its own if the firmware didn't already do it.
Skipping this initialization means the I2C controller becomes unusable
to the kernel.

This patch fixes the issue by making the i2c_init() unconditional again.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ie4546c31d87d91113eeef7dc7a18599a87e6d6eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58026
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-29 21:07:30 +00:00
Angel Pons efe57ebd40 soc/intel: Rename GNVS struct member to match ASL
Rename the `ecps` GNVS struct member to `epcs` to match the name in ASL.

Change-Id: I1f6b97309eea75e7dbb4e5e664660df05ec0845e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-29 20:40:32 +00:00
Shelley Chen ae364008a7 herobrine: Initialize SAR sensor QUP
Initializing SAR sensor (QUP2, address 0x988000)

BUG=b:198456205
BRANCH=None
TEST=Boot into kernel and make sure no i2c errors for 0x988000 in
     dmesg

Change-Id: I75b0e9173d4c49b5e7308158a678964d6637b225
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-09-29 20:20:49 +00:00
Shelley Chen 10129f81ac mb/google/herobrine: Change preprocessor to C code
BUG=b:182963902
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_HEROBRINE -x -a -c max -B

Change-Id: I10f8a9682200b883474dc385331c5dae84cbdb08
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-09-29 20:20:22 +00:00
Shelley Chen ffebd4970f herobrine: Add fingerprint power sequencing
For Herobrine variants that include a finger print sensor, we will
need to power sequence it.  We are using the same FP sensor as
trogdor, so we will follow the timings used for trogdor from
CL:2695676.

BUG=b:198474942
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_HEROBRINE -x -a -c max -B

Change-Id: Ica6eafc47cf1b95eeb8d94c6e0a8c88519665e3f
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58021
Reviewed-by: Alexandru Stan <amstan@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-29 20:16:38 +00:00
Patrick Huang 9de5d8dd39 mb/google/guybrush/var/nipperkin: Add ALC5682I and MAX98360 support
Add ID "10029836" for machine driver, "RTL5682" for ALC5682I and "MX98357A" for MAX98360.

BUG=b:198716348
TEST=Build nipperkin, codec is functional with new machine driver.

Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com>
Change-Id: Iab9d11adb7cd08effa2a9b6a627832bd89cb3cb5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-29 15:40:56 +00:00
Selma Bensaid c42d875448 Update vboot submodule to upstream main (13f601f)
Updating from commit id c5a482ed:
    2021-09-08 17:16:59 +0000 - (sign_official_build: disable gsetup for reven)

to commit id 13f601f:
    13f601f vboot: boot from miniOS recovery kernels on disk b

This brings in 14 new commits.

Signed-off-by: Selma Bensaid <selma.bensaid@intel.com>
Change-Id: I66788ea434a6000435b97ce64107f3b5da882414
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57994
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-29 15:35:28 +00:00
Stanley Wu a82fb07a52 mb/google/dedede/var/boten: Add fw_config probe for ALC5682-VD & VS
ALC5682-VD/ALC5682I-VS load different kernel driver by different hid
name. Update hid name depending on the AUDIO_CODEC_SOURCE field of
fw_config. Define SSFC bit 9-11 in coreboot for codec within ec.

ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"

BUG=b:193694180
TEST=ALC5682-VD/ALC5682I-VS audio codec can work

Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: Iba91b51cbbe7adc502372c9a026867de61d8035d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-29 15:31:38 +00:00
Karthikeyan Ramasubramanian f42fca18cb mb/google/mancomb: Delete board support
Mancomb mainboard has been cancelled. Hence delete the board support.

BUG=b:190404616
TEST=None

Cq-Depend: chromium:3188634
Change-Id: I3ce02efb1fa5ea488447099abe08da6051fb6fc6
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-29 14:14:19 +00:00
Raul E Rangel ea5c31138b arch/x86,cpu/x86: Disable the %gs and %fs segments
The %fs and %gs segment are typically used to implement thread local
storage or cpu local storage. We don't currently use these in coreboot,
so there is no reason to map them. By setting the segment index to 0,
it disables the segment. If an instruction tries to read from one of
these segments an exception will be raised.

The end goal is to make cpu_info() use the %gs segment. This will remove
the stack alignment requirements and fix smm_do_relocation.

BUG=b:194391185, b:179699789
TEST=Boot guybrush to OS

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iaa376e562acc6bd1dfffb7a23bdec82aa474c1d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-09-29 14:12:58 +00:00
Selma Bensaid 326a2c4794 soc/intel/alderlake: Add GFx Device ID 0x46c3
This CL adds support for new ADL-M graphics Device ID 0x46c3.

TEST=boot to OS

Change-Id: Ib55fb501f96fe9bcc328202511bbfe84a3122285
Signed-off-by: Selma Bensaid <selma.bensaid@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-29 10:07:41 +00:00
Tracy Wu 3e97178871 mb/intel/adlrvp, mb/google/brya: Add ADLP 242 PLx configurations
Add ADLP 242 sku PLx related settings, which follow the settings of
ADLP 282 sku (both are 15w).

BUG=b:201253904
TEST=USE='fw_debug' emerge-brya intel-adlfsp coreboot chromeos-bootimage

Change-Id: If9b60893ab3e2c4a88e7d2cf45223c5fbce6f847
Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-09-29 10:07:06 +00:00
Tracy Wu 697d6a81c2 soc/intel/alderlake: Add ADLP 242 power configurations
Add ADLP 242 sku power related settings, which follow the settings of
ADLP 282 sku (both are 15w).

BUG=b:201253904
TEST=Build and check fsp log to confirm the settings are set properly.

Change-Id: I829dd690c22d167a507b1910106da06b275cec09
Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-09-29 10:07:00 +00:00
Tim Wawrzynczak dee834aafc mb/google/brya: Update PCH power cycle related durations
The voltage rail discharge times have been measured, so therefore
the boot time on a cold boot when the CSE must go through a global reset
and thus a trip to S5 can be optimized. Select the lowest applicable
value for each PchPmSlp UPD that can be used with these measurements.

This is programmed in the baseboard because the measured discharge times
leave (what should be) plenty of margin for variants to also not violate
any power sequencing guidelines from the PDG.

BUG=b:184799383
TEST=verified time in S5 during a global reset is ~1s instead of 4s

Change-Id: Ia373c47b3967d68ddac21707c6eb4565d9d6519e
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-09-29 10:06:01 +00:00
Tim Wawrzynczak ab0e0813b6 soc/intel/alderlake: Add support for power cycle and SLP signal duration
The UPDs for PM power cycle duration and SLP_* signal durations are all
identical to Tiger Lake, so add similar support, but use enums instead
of comments to represent the durations symbolically.

BUG=b:184799383

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I4a531f042658894bcbc6a76eff453c06e90d66b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57891
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-29 10:05:51 +00:00
Karthikeyan Ramasubramanian c0534435bf mb/google/dedede: Remove drawcia_legacy board support
Support for drawcia_legacy board is cancelled. Hence remove the board
support.

BUG=b:192256341
TEST=None

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I76cd3e388439f5aee94a17fe35ae210f449cfbfc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Evan Green <evgreen@chromium.org>
2021-09-29 10:05:03 +00:00
Karthikeyan Ramasubramanian 7a595124f5 mb/google/dedede: Remove Boten_Legacy board support
Support for Boten_legacy board is cancelled. Hence remove the board
support.

BUG=b:192256341
TEST=None

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: If26dc869ff95dff70c0f83a13f6f727aa5992dbd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Evan Green <evgreen@chromium.org>
2021-09-29 10:04:59 +00:00
Karthikeyan Ramasubramanian 941cd25b1b mb/google/dedede: Remove wheelie variant board support
Wheelie variant board has been cancelled. Remove wheelie variant board
support.

BUG=b:192256341
TEST=None

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I3ad5bc1c987feb55183a663937794781c7301a48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Evan Green <evgreen@chromium.org>
2021-09-29 10:04:56 +00:00
Karthikeyan Ramasubramanian 4c79aa5412 mb/google/dedede: Remove cappy variant support
Cappy variant is cancelled. Hence delete the cappy variant support.

BUG=b:192256341
TEST=None

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: If43188a3e6bf4f4449c7e2d08be7609efe58dca1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Evan Green <evgreen@chromium.org>
2021-09-29 10:04:53 +00:00
Angel Pons 477647cef5 {sb,soc}/intel: Drop unused globalnvs.asl methods
These methods are never used in the code. Drop them.

Change-Id: If5568b494f821d2647ada5ae845bcd015708520e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-29 10:04:44 +00:00
Angel Pons 2fd1e47313 {sb,soc}/intel: Drop PRMx from GNVS
These fields are never used in the code. Drop them.

Change-Id: Icd07f2d704c19126bf6df4d740c21d5a1342061b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-29 10:04:40 +00:00
Angel Pons 286c771657 {sb,soc}/intel: Drop LCKF from GNVS
This field is never used in the code. Drop it.

Change-Id: I88207ec369ab83823ef2f3fc40f68a0980ce9663
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-29 10:04:27 +00:00
Rex-BC Chen 61be50dafb soc/mediatek/mt8195: initialize DFD
DFD (Design for Debug) is a debugging tool, which scans
flip-flops and dumps to internal RAM on the WDT reset.
After system reboots, those values could be showed for
debugging.

BUG=b:192429713

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ied63913db94b2e52ab394a66c70f7edfd507c99b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57980
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-29 06:57:15 +00:00
Ryan Chuang 98affb68f0 vc/mediatek/mt8195: Remove unused code
Remove unused drivers and some fast calibration implementations
to align with the latest MTK memory reference code.

TEST=boot to kernel

Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: I2e6be2e16c139e48c65352fe2eabf16bf9cd550a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57978
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-29 06:57:06 +00:00
Felix Singer 9af3de12f6 mb/purism/librem_skl: Clean up dsdt.asl
Move includes using library paths to the top and remove unnecessary
comments. Also, get rid of that unnecessary _SB scope. Use an absolute
path for the PCI0 device instead.

Change-Id: I2c4fb1933eda2eb75bfe9181f13e189ec66cadf9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2021-09-28 20:44:33 +00:00
Kevin Chang 836a7f92d2 mb/google/brya/variants/taeko: add NVMe GPIOs to early_gpio_table
NVMe needs extra time to run boot process, enable power and deassert
reset for NVMe earlier in the boot flow that taeko can successfully
boot into OS with non-serial coreboot.

BUG=b:199969366 & b:200711149
TEST=Build FW and test with non-serial FW reboot 20 times pass.

Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I032c5b90fb2148c4075d6ead3e4161c0cc659b20
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-28 20:08:23 +00:00