Commit graph

632 commits

Author SHA1 Message Date
Aaron Durbin
e5ab9e28a6 mb/lenovo/x131e: remove reference to non-existent file
In commit 7f5efd90e (intel/bd82x6x: Use generated ACPI PIRQ)
the default_irq_route.asl file was removed, but this mainboard
was missed. Follow suit with the original intent of the commit
and fix the build breakage.

Change-Id: Iac233b802239e4e5cfc66d9545bb637ec4f9f541
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22958
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-12-21 00:20:40 +00:00
James Ye
be6fd4c4b5 mb/lenovo: add Lenovo ThinkPad X131e (Intel)
The Intel version of ThinkPad X131e can ship with Sandy Bridge or
Ivy Bridge processors.  The mainboard uses 8MiB+4MiB flash chips, with
the 8MiB chip containing the IFD and ME, and the 4MiB chip containing
the BIOS.  The flash chips can be accessed with an external programmer.

This port was primarily created using autoport, with some parts adapted
from lenovo/x230 and google/stout.

Tested and working:
 - Machine type 3367AH5 / Intel Celeron 887 (Sandy Bridge)
 - Boots Debian GNU/Linux 9.2 (Linux 4.9.51) via SeaBIOS
 - Boot from internal SATA and USB
 - Native RAM init
 - Native VGA init
 - libgfxinit
 - VGA and HDMI display output
 - Keyboard, trackpoint, touchpad
 - Audio (speaker, headphones)
 - Ethernet (Realtek)
 - Display backlight
 - USB 3.0 ports
 - "Always on" USB port (EHCI debug)
 - SD card reader
 - Webcam
 - Fan and temperature sensors
 - ACPI S3 (Sleep)
 - CMOS
 - TPM

Not tested:
 - WLAN/Bluetooth (Broadcom)
 - WWAN/mSATA (no card)
 - Other operating systems

Not working or not implemented:
 - Fn keys
 - ACPI S4 (Hibernation) "Image mismatch: memory size"

Change-Id: If8de3a9308997e2d57aee869023ee9a43a2db872
Signed-off-by: James Ye <jye836@gmail.com>
Reviewed-on: https://review.coreboot.org/20694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-12-20 16:54:08 +00:00
Patrick Rudolph
2387f928e8 mb/lenovo/t430/acpi_tables: Don't set flvl
The current fan level should be zero at boot and only be modified by
ACPI or SMI code.

Change-Id: I72b59f05746b28cfb24c4f018aebc2befa9caba6
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/22796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-20 16:48:49 +00:00
Tobias Diedrich
7f5efd90e5 intel/bd82x6x: Use generated ACPI PIRQ
Enable change Ic6b8ce4a9db50211a9c26221ca10105c5a0829a0
(sb/intel/common: Automatically generate ACPI PIRQ) for BD82X6X.

This generates the main ACPI _PRT table automatically based on the
chipset registers.

Tested on Intel NUC DCP847SKE with Linux 4.13.14:
$ cat /proc/interrupts
           CPU0       CPU1
  0:         23          0   IO-APIC   2-edge      timer
  8:          1          0   IO-APIC   8-edge      rtc0
  9:          0          0   IO-APIC   9-fasteoi   acpi
 19:         86          0   IO-APIC  19-fasteoi   ehci_hcd:usb1
 23:          0          0   IO-APIC  23-fasteoi   i801_smbus
[...MSI and other interrupts skipped...]

Log messages:
ACPI_PIRQ_GEN PCI: 00:02.0: pin=1 pirq=1
ACPI_PIRQ_GEN PCI: 00:1b.0: pin=1 pirq=1
ACPI_PIRQ_GEN PCI: 00:1c.0: pin=1 pirq=2
ACPI_PIRQ_GEN PCI: 00:1c.1: pin=2 pirq=6
ACPI_PIRQ_GEN PCI: 00:1c.2: pin=3 pirq=4
ACPI_PIRQ_GEN PCI: 00:1d.0: pin=1 pirq=4
ACPI_PIRQ_GEN PCI: 00:1f.2: pin=1 pirq=2
ACPI_PIRQ_GEN PCI: 00:1f.3: pin=2 pirq=8
ACPI_PIRQ_GEN PCI: 00:04.0: pin=1 pirq=1

Generated _PRT:
    Scope (\_SB.PCI0)
    {
        Method (_PRT, 0, NotSerialized)  // _PRT: PCI Routing Table
        {
            If (PICM)
            {
                Return (Package (0x09)
                {
                    Package (0x04)
                    {
                        0x0002FFFF,
                        0x00000000,
                        0x00000000,
                        0x00000010
                    },

                    Package (0x04)
                    {
                        0x001BFFFF,
                        0x00000000,
                        0x00000000,
                        0x00000010
                    },

                    Package (0x04)
                    {
                        0x001CFFFF,
                        0x00000000,
                        0x00000000,
                        0x00000011
                    },

                    Package (0x04)
                    {
                        0x001CFFFF,
                        0x00000001,
                        0x00000000,
                        0x00000015
                    },

                    Package (0x04)
                    {
                        0x001CFFFF,
                        0x00000002,
                        0x00000000,
                        0x00000013
                    },

                    Package (0x04)
                    {
                        0x001DFFFF,
                        0x00000000,
                        0x00000000,
                        0x00000013
                    },

                    Package (0x04)
                    {
                        0x001FFFFF,
                        0x00000000,
                        0x00000000,
                        0x00000011
                    },

                    Package (0x04)
                    {
                        0x001FFFFF,
                        0x00000001,
                        0x00000000,
                        0x00000017
                    },

                    Package (0x04)
                    {
                        0x0004FFFF,
                        0x00000000,
                        0x00000000,
                        0x00000010
                    }
                })
            }
            Else
            {
                Return (Package (0x09)
                {
                    Package (0x04)
                    {
                        0x0002FFFF,
                        0x00000000,
                        \_SB.PCI0.LPCB.LNKA,
                        0x00000000
                    },

                    Package (0x04)
                    {
                        0x001BFFFF,
                        0x00000000,
                        \_SB.PCI0.LPCB.LNKA,
                        0x00000000
                    },

                    Package (0x04)
                    {
                        0x001CFFFF,
                        0x00000000,
                        \_SB.PCI0.LPCB.LNKB,
                        0x00000000
                    },

                    Package (0x04)
                    {
                        0x001CFFFF,
                        0x00000001,
                        \_SB.PCI0.LPCB.LNKF,
                        0x00000000
                    },

                    Package (0x04)
                    {
                        0x001CFFFF,
                        0x00000002,
                        \_SB.PCI0.LPCB.LNKD,
                        0x00000000
                    },

                    Package (0x04)
                    {
                        0x001DFFFF,
                        0x00000000,
                        \_SB.PCI0.LPCB.LNKD,
                        0x00000000
                    },

                    Package (0x04)
                    {
                        0x001FFFFF,
                        0x00000000,
                        \_SB.PCI0.LPCB.LNKB,
                        0x00000000
                    },

                    Package (0x04)
                    {
                        0x001FFFFF,
                        0x00000001,
                        \_SB.PCI0.LPCB.LNKH,
                        0x00000000
                    },

                    Package (0x04)
                    {
                        0x0004FFFF,
                        0x00000000,
                        \_SB.PCI0.LPCB.LNKA,
                        0x00000000
                    }
                })
            }
        }
    }

Change-Id: I832a86925283d61b64b8268246d9e6f11994c120
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: https://review.coreboot.org/22859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-12-20 16:48:23 +00:00
Andrey Korolyov
60d9ce3937 mainboard/lenovo: add Lenovo Z61t laptop
This platform shares most hardware components with first-gen Core
Lenovo laptops such as T60/X60, with much smaller EEPROM size as
one of notable differences. The port features Intel graphics,
ATI-based version should work with vendor VBIOS.

Tested peripherals:
 - sleep/resume,
 - USB ports,
 - ACPI Fn key bindings/volume buttons,
 - backlight control,
 - ethernet,
 - wireless (under Linux),
 - sound/beep,
 - dock handling,
 - serial via dock.

Untested peripherals:
 - IrDA,
 - parallel port,
 - PCMCIA,
 - S-Video port,
 - modem,
 - FP reader (should just work),
 - IEEE1394.

Linux 3.16 works with native gfxinit perfectly, with Intel VBIOS
console sometimes displays nothing when i915 framebuffer is used.

Windows 7 has an interrupt assignment issue with iw3945, otherwise
tested stuff is fine.

Change-Id: I84c89cc47d3db126d827f92d50270954bc42f224
Signed-off-by: Andrey Korolyov <andrey@xdel.ru>
Reviewed-on: https://review.coreboot.org/21019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-12-19 21:15:48 +00:00
Arthur Heymans
cda1c4a521 mb/lenovo/t400/blc.c: Add a new panel to the list
Also adds a comment in the code to clarify what this array is about.

Change-Id: I04b185a5dbd7a7ccb039820f19d2cb549b9a2eac
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-12-12 12:05:14 +00:00
Arthur Heymans
079455f207 mb/*/*/Kconfig: Remove default MMCONF_BASE_ADDRESS on Sandy Bridge
Change-Id: I6f0d6d7fefc77fb05cdb629d09de8cb72496a9cc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-12-06 20:26:36 +00:00
Arthur Heymans
f1c8ede1a5 sb/intel/i82801ix: fetch initial timestamp in bootblock
TESTED on Thinkpad x200

Change-Id: I3cd286709f8734793dc6ae303215433eff29d25b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-11-23 04:59:26 +00:00
Kevin Keijzer
6d941bad78 mb/lenovo/t400/blc.c: Add LTN154P2-L05 to whitelist
TESTED on Lenovo T500

Change-Id: I5546641cb34264e29ccb3398dd68f6144dafe524
Signed-off-by: Kevin Keijzer <kevin@quietlife.nl>
Reviewed-on: https://review.coreboot.org/22367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-17 15:06:15 +00:00
Kevin Keijzer
15af281744 mb/lenovo/t400: Add LTN154X3-L02 to list of known displays
TESTED on Lenovo T500

Change-Id: I9c9fef82ca4af99c7d4813e0ab0e315fde93b972
Signed-off-by: Kevin Keijzer <kevin@quietlife.nl>
Reviewed-on: https://review.coreboot.org/22475
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-11-17 11:32:16 +00:00
Kyösti Mälkki
9fee35c6c4 AGESA: Split long lines in OemCustomize.c
Change-Id: I907f55622e6aaba401471239f706ab24cd26319f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-19 11:24:09 +00:00
Paul Menzel
c81bb2cd36 amd/agesa: Remove redundant UDELAY_LAPIC selection
This is already selected in `src/cpu/amd/agesa/Kconfig`.

Change-Id: I691a2ade10ee461b6bc34ea24d57a911281791f3
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/22011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-17 01:40:08 +00:00
Kyösti Mälkki
6287a69530 AGESA: Re-enable HAVE_ACPI_RESUME
Note: For some of the boards affected ACPI S3 support
was never tested but feature was just copy-paste from
reference design.

Change-Id: I2a54d605fa267a7501f57efd79a16b3bfa49891e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Damien Zammit <damien@zamaudio.com>
2017-10-05 13:23:14 +00:00
Kyösti Mälkki
87df26731e AGESA: Remove heap allocations from OemCustomize.c
We can simply declare these structures const.

Change-Id: I637c60cc2f83e682bd5e415b674f6e27c705ac91
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-26 09:22:03 +00:00
Kyösti Mälkki
e52738b428 AGESA binaryPI boards: Fix some whitespace
Change-Id: I150d4a71536137a725f43d900d483e7e35592bb3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-09-26 08:36:05 +00:00
Patrick Rudolph
df27690df3 mb/lenovo/x2?0/devicetree: Fix regression of BDC detection
The x220 and x230 do have BDC detection, but it's broken.
Disable BDC detection on those two boards, and add a comment
why it doesn't work.

The issue has been reported and tested on Lenovo X220.

Change-Id: Id1ccc2c4387370e284ff8964e1c41d945cefe74c
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-25 16:18:38 +00:00
Arthur Heymans
b29078e401 mb/*/*: Remove rtc nvram configurable baud rate
There have been discussions about removing this since it does not seem
to be used much and only creates troubles for boards without defaults,
not to mention that it was configurable on many boards that do not
even feature uart.

It is still possible to configure the baudrate through the Kconfig
option.

Change-Id: I71698d9b188eeac73670b18b757dff5fcea0df41
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-23 11:06:25 +00:00
Kyösti Mälkki
d082b6ae84 AGESA binaryPI: Clean up amdfamXX.h include
Change-Id: Iba8b8d33e1f10e28745234988d97d4fafd04c798
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-09-19 18:38:58 +00:00
Kyösti Mälkki
c8e4742f91 AGESA vendorcode: Move PlatformInstall.h
All thse Option.*Install.h files are about configuring
what eventually is referenced in the final libagesa
build. It's self-contained so isolate these together
with PlatformInstall.h to hide them from rest of
the build.

Change-Id: Id9d90a3366bafc1ad01434599d2ae1302887d88c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-13 22:51:15 +00:00
Kyösti Mälkki
a257efcfcc AGESA boards: Clean up Ids.h and Filecode.h includes
Change-Id: I9cb63ff58900a39d7cd8e3da2b9a9a95c2a41a69
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-12 17:24:00 +00:00
Kyösti Mälkki
f7ca672118 AGESA boards: Clean up some includes
Change-Id: I84c70aa04ab556a3898d3525f7b9aab85812f61d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-12 16:09:31 +00:00
Patrick Rudolph
b77eec82f3 mb/lenovo/*/devicetree: Add BDC detection support
Add support for BDC detection, based on the schematics for each board.
Support for boards without schematics needs further testing.

Needs test on all boards.

Change-Id: If33ef88fb808f36b050393fa83eb1b541ce936b9
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-09-11 23:14:26 +00:00
Kyösti Mälkki
662cf7f8a6 lenovo/g505s: Switch away from AGESA_LEGACY_WRAPPER
Change-Id: Ia65f9ecb62767424744e399a43e4728666fd28b3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-31 16:30:36 +00:00
Kyösti Mälkki
1b526621c9 lenovo/g505s: Enable XHCI device in devicetree
Enabling XHCI is additionally controlled with Kconfig
option HUDSON_XHCI_ENABLE. Even when it is enabled,
it EHCI debug works on the USB port next to the
DVD drive door.

Change-Id: I83738da6015f58ecd0819c553d333a176365dc78
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-31 16:29:12 +00:00
Kyösti Mälkki
3754cda835 lenovo/g505s: Switch from f15rl to f15tn
Support code for Trinity and Richland is identical now.

I have also come across a unit with Trinity model CPU,
whose CPUID was not listed in f15rl while f15tn already
had support for f15rl.

Change-Id: Ia869429b75a9b308b4d4a84f16914ca629b1b1b5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-08-31 16:28:41 +00:00
Arthur Heymans
24231aceac drivers/i2c/ck505: Add generic driver to configure clockgen
Replaces the ics/954309 driver with a more generic version to
accommodate clockgens with a different amount of registers.

It also features a mask to only touch certain bits of the clockgen.

TODO: set appropriate mask for X60/T60 since the datasheets for their
clockgens can be found.

Change-Id: Ie43c4de7891a39f2f443e78213ecd688134e68d7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-08-30 15:46:55 +00:00
Kevin Keijzer
7bb0325884 mb/lenovo/t400/blc.c: Add B141EW05 V3 to whitelist
TESTED on Lenovo T400

Change-Id: I365aeb7e997def225c23d3287558bdc4eefa4298
Signed-off-by: Kevin Keijzer <kevin@quietlife.nl>
Reviewed-on: https://review.coreboot.org/21230
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-28 20:05:00 +00:00
Patrick Rudolph
afa627db2e mb/lenovo/*/acpi_tables: Add critical and passive threshold
Add critical and passive threshold to be advertised in thermal zone 0.

Change-Id: Ic75a80994b27ac19651ed52b7fc3c00c65cd9c01
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-27 13:07:21 +00:00
Marshall Dawson
6dd620bf10 AGESA mainboards: Clean up IS_ENABLED fan control
Remove all checks for #if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) around
the imc.h includes.  Convert all #if to if() for fan control setup.

Change-Id: I04a9fbbf6f64f45e1a0b544267bfe840ce7fa1d9
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-08-24 11:47:36 +00:00
Bill XIE
a0d31d8d7d mb/lenovo/t430s: Enable libgfxinit
Tested on T430s with an external screen connected to every one of the
DP ports (miniDP on mainboard, two DP ports on dock), the GRUB payload
can display on both the external screen and the internal LVDS screen.

This is a copy-paste of I8f270d55 "mb/lenovo/x230: Enable libgfxinit".

Change-Id: Ifb1471ecb18927c30c61c64011cbb0e20a465558
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/21070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-23 08:36:55 +00:00
Kyösti Mälkki
390ba044dc AGESA binaryPI: Consolidate and fix sleep states
SSFG was meant to be used as a mask to enable sleep states
_S1 thru _S4. However as a logical instead of bitwise 'and'
operation was used, all the states were enabled if only
one was marked available.

State _S3 is now set conditionally if HAVE_ACPI_RESUME=y.
For pi/hudson this had been fixed already preprocessor.

Note that all boards had SSFG == 0x0D that previously
enabled ACPI S3 sleep state even when it was not available.
States _S1 and _S2 still appear enabled in ASL/AML
but may not actually work.

TEST: 'cat /sys/power/state' and notice choice 'mem' was
removed from the list of available sleep states.

Change-Id: I27d616871c1771f0c87d8fba23d4ce1569607765
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-08-23 03:35:58 +00:00
Patrick Rudolph
b794a69ce9 nb/intel/sandybridge/raminit: Add Kconfig option for fuses
Add a new Kconfig option to ignore memory fuses that limit the
maximum DRAM frequency to be used. The option is disabled by
default and should only enabled by experienced users as it
might decrease system stability or prevent a successful RAM
training.

Remove conflicting devicetree settings.

Change-Id: I35dd78a02bcaafce8ba522d253c795d7835bacae
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nicola Corna <nicola@corna.info>
2017-08-10 16:09:01 +00:00
Patrick Rudolph
db27e3384a mb/lenovo/t*00/romstage: Switch to new hybrid driver
Get rid of old hybrid graphics driver and use the new one.

1. Disable IGD and PEG in early romstage.
 The PEG port will get disabled on devices that do not have a
 discrete GPU. The power savings are around ~1Watt.

 The disabled IGD does no longer waste GFX stolen memory.

2. Get rid of PCI driver
 The Nvidia GPU can be handled by the generic PCI driver and allows
 to use the ACPI _ROM generator for Switchable graphics.

3. Settings are stored in devicetree.
 One driver for all Lenovo hybrid graphics capable devices.

4. Add support for Thinker1 GPU power handling.
 Only boards that do use reference design 2012 are known to be
 supported. Needs test on boards that do you use reference design 2013.
 Should reduce idle power consumption when using IGD by ~5Watt.

Tested on Lenovo T430 without DGPU. PEG port is disabled.
Needs test on all devices.

Change-Id: Ibf18b75e8afe2568de8498b39a608dac8db3ba73
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-10 16:06:26 +00:00
Patrick Rudolph
24680d0902 mb/lenovo/t400: Switch to new hybrid graphics driver
Use new hybrid graphics driver to get device state.
Move remaining code to romstage.c.

Tested on Lenovo T500:
* Linux 4.11.4 on Fedora 25
* Integrated (using NGI)
* Discrete (using VGA OpROM)
* Switchable (using NGI and VGA OpROM), tested with DRI_PRIME

No regressions found.

Change-Id: Iad2eccaab19c71f11308853ba9326d8186e67c93
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-10 16:06:19 +00:00
Alexander Couzens
de0326b96c mb/lenovo/x1_carbon_gen1: add missing '+' in spd/Makefile
Each line of spd config overwriting the slot 0 instead
of appending it.

Change-Id: I0124aa34f1d4fcb30810fb7eef03d4828a7ac430
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Tested-on: lenovo x1 carbon gen 1 with elpida 8GB
Fixes: e9787ff61f ("mb/lenovo/x1_carbon_gen1: Add 4GiB SPD index 2")
Reviewed-on: https://review.coreboot.org/20918
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-08-09 19:49:56 +00:00
Nico Huber
e9787ff61f mb/lenovo/x1_carbon_gen1: Add 4GiB SPD index 2
Change-Id: I218fd48c8e29563ef089d60ebde7bc36ac8ab189
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-08-08 18:19:54 +00:00
Patrick Rudolph
189909ea76 mb/lenovo/l520/Kconfig: Remove hybrid graphics driver support
The schematics isn't available for the board, but other L*00 series boards
seem to use a different, compared to T*00 series, GPIO layout.

As it has never been tested, remove the broken driver.

Change-Id: I4bfa02fdbc5da5b556010c2f300faaf6dc845b80
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-08 12:24:47 +00:00
Kyösti Mälkki
28c4d2f7e0 AGESA: Introduce AGESA_LEGACY_WRAPPER and its counterpart
We define AGESA_LEGACY_WRAPPER a method of calling AGESA
via functions in agesawrapper.c file. The approach implemented
there makes it very inconvenient to do board-specific
customisation or present common platform-specific features.
Seems like it also causes assertion errors on AGESA side.
The flag is applied here to all boards and then individually
removed one at a time, as things get tested.

New method is not to call AGESA internal functions directly,
but via the dispatcher. AGESA call parameters are routed to
hooks in both platform and board -directories, to allow for
easy capture or modification as needed.

For each AGESA dispatcher call made, eventlog entries are
replayed to the console log. Also relocations of AGESA heap
that took place are recorded.

New method is expected to be compatible with binaryPI.

Change-Id: Iac3d7f8b0354e9f02c2625576f36fe06b05eb4ce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02 04:46:29 +00:00
Nico Huber
23b93dd7d8 intel/sandybridge: Clean VGA BIOS ids up a little
Sync map_oprom_vendev() and autoport with the list of PCI ids in the
`gma.c` driver, remove one obsolete Kconfig default override.

Change-Id: I12f24f415b695c516fbb947114e09c873af2e439
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-07-30 00:07:01 +00:00
Nico Huber
2b5c021431 intel/sandybridge: Gather MMCONF_BASE_ADDRESS defaults
All affected boards did the same USE_NATIVE_RAMINIT distinction or
actually selected USE_NATIVE_RAMINIT. Also update autoport.

Change-Id: I924c43cec1e36e84db40e4b8e1dd0e05cad2b978
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20813
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-07-30 00:06:51 +00:00
Patrick Rudolph
0cce14341a mb/lenovo/t430: Disable usb_always_on by default in CMOS
Fix regression introduced by commit 7ffb329f.

The default value for usb_always_on is no longer sane and is replaced
by the same default that is used on all other boards (disabled).

Change-Id: Ia8854a8491bc56507d01e08e1ca1e195a1d62bfc
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-24 16:49:12 +00:00
Martin Roth
b4560cd523 Update files with no newline at the end
Change-Id: I8febb8d74e2463622cab0313c543ceebec71fdf4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-24 15:08:16 +00:00
Martin Roth
467a87abce Fix files with multiple newlines at the end.
Change-Id: Iaab26033e947cb9cf299faf1ce6d40a90a9facbe
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20704
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-24 15:08:08 +00:00
Patrick Rudolph
7ffb329f27 mb/lenovo/*/cmos: Port USB Always On
Port commit f1395d82: "ec/lenovo/h8: Add USB Always On"
to other Thinkpad boards, as it seems to work fine on all
generations.

Change-Id: I6dcbfaae2a444d9a679ecb64a87dc2a59b8fd281
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2017-07-07 17:20:09 +00:00
Patrick Rudolph
b21f5d708a ec/lenovo/h8/smm: Support USB always on AC only
Add support for UAO AC only mode.
Needs tests on all platforms.

Change-Id: Ib52aab427ff687b00129024cde65b78060d21e32
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2017-07-07 17:19:09 +00:00
Martin Roth
356b519049 mainboard/[g-l]: add IS_ENABLED() around Kconfig symbol references
Change-Id: I1f906c8c465108017bc4d08534653233078ef32d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-07-06 00:19:56 +00:00
Patrick Rudolph
cfc73952b8 mb/lenovo/t400/dock: Control LEDs
Toggle LEDs after successful dock and undock.

On boot the LED will light up and on undock button
press the LED will turn off again.

Tested on Lenovo T500.

Change-Id: Ib5851f4abcedf4041faae6b3b810102012f488cd
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-07-02 18:40:44 +00:00
Alexander Couzens
18437c46bd mainboard/lenovo/x220: allow to use libgfxinit
Change-Id: I8b02596b116c0b164e83e7b02449c547224a50a6
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/20330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-27 16:51:02 +00:00
Patrick Rudolph
ea6f700632 mb/lenovo/t430: Enable libgfxinit
Enable libgfxinit.

Tested on Lenovo T430:
* LVDS
* VGA
* DP (using DP->HDMI adapter)

All three ports are working. The LVDS port is garbled under linux
when VGA or DP is connected, likely due to missing VBT.

Change-Id: I665661e93724072d1e8412cfcc0e818f824c8cb0
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-06-16 16:14:36 +02:00
Arthur Heymans
d65ff22988 nb/intel/gm45: Don't allow too low values for gfx_uma_size
Too low gfx_uma_size can result in problems if the framebuffer
does not fit.

This partially reverts: 7afcfe0 "gm45: enable setting all vram sizes
from cmos"

Change-Id: I485d24198cb784db5d2cfce0a8646e861a4a1695
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-06-15 00:35:35 +02:00