commit ce0e2a0140 (drivers/intel/fsp2_0:
use FSP to allocate APEI BERT memory region) adds a mechanism to reserve
the BERT region inside the coreboot code, so we can get rid of the
workaround to reserve it in the FSP and return the location in a HOB.
mcfg->bert_size defaults to 0 which makes the FSP not generate the
corresponding HOB, but that field is planned to be removed at least on
Cezanne, so don't explicitly set it to 0.
BUG=b:169934025
TEST=BERT table that gets generated in a follow-up patch for Picasso
points to expected BERT region and Linux is able to access, decode and
display it.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iaca89b47793bf9982181560f026459a18e7db134
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52584
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since this enum is only used for the devicetree settings and not for the
hardware itself, move it from the southbridge header to the chip one.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0907fc5cba9315fec5fabff67d279c6d95d1c9f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54684
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PSP_SOFTFUSE_BITS used to be like this:
15 0 29 "28 6"
It causes internal shell report error:
/bin/sh: -c: line 0: unexpected EOF while looking for matching `"'
/bin/sh: -c: line 1: syntax error: unexpected end of file
/bin/sh: -c: line 0: unexpected EOF while looking for matching `"'
/bin/sh: -c: line 1: syntax error: unexpected end of file
Change-Id: I716f19d37fb57b9ef3fc7259c6dcca7d21022d32
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Also drop unneeded intermediate cast to void * before casting the
address of the struct dptc_input type variables to uint8_t *.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie1e2aa1ec728a4e16d3a587d7400cdfc8962f443
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This will change the names of the GPP bridges, but this ok since there
is no hand written ASL that references these names.
BUG=b:184766519
TEST=Boot picasso and dump ACPI
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic09200156e8a37bd1a29ca95a17c8f8ae2b92bd3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54028
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is still causing boot errors on zork:
coreboot-4.13-3659-g269e03d5c42f Fri May 7 22:03:11 UTC 2021 bootblock starting (log level: 8)...
Family_Model: 00820f01
PSP boot mode: Development
Silicon level: Pre-Production
Set power off after power failure.
PMxC0 STATUS: 0x800 BIT11
I2C bus 3 version 0x3132322a
DW I2C bus 3 at 0xfedc5000 (400 KHz)
FMAP: area COREBOOT found @ 875000 (7909376 bytes)
ASSERTION ERROR: file 'src/commonlib/bsd/cbfs_mcache.c', line 106
BUG=b:177323348
TEST=Boot ezkinil to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I68b4b73670e750207414f0d85ff96f21481be8ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53933
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
AMDFW tool stores bios dir entry to bios1_entry in picasso but
bios3_entry in cezanne. Separate getting bios_dir_addr into a function
and implement it on each platforms.
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Ie18ed7979a04319c074b9b251130d419dc7f22dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52964
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move all platform-specific code except direct svc calls to chipset.c.
There will be differences between each platforms and we can't put
everything into svc.c.
TEST=build firmware for zork
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Ie7a71d1632800072a17c26591e13e09e0269cf75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52963
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We can now delete the picasso specific version.
BUG=b:184766519
TEST=Build zork and verify SSDT has not changed
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic79014e83c9ff63cc7a6757b16764ae23b36984f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53935
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The method now dynamically allocates the pirq structure and uses the
get_pci_routing_table method.
BUG=b:184766519
TEST=Build guybrush and verify picasso SSDT has not changed.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I297fc3ca7227fb4794ac70bd046ce2f93da8b869
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This allows us to use the common get_pci_routing_info and
pci_calculate_irq. The IRQ field in the struct was also filled in from
the PPR.
BUG=b:184766519
TEST=Boot ezkinil and verify SSDT table is identical.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I16d90d8c89bfcf48878c0741154290ebc52a4120
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53923
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TEST=Mandolin still boots into Linux and there's no ACPI warning in
dmesg.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7e6d38ebeae5e55a4a65930b989838532ab9c446
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53920
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Also add an alib_ prefix to avoid possible name collisions.
TEST=Timeless build for Mandolin results in identical binary.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib0f220a4cde6da764bb8bc589b5f44ae16496bd7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53918
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These parameter IDs are defined in the AGESA Interface specification
#55483. This patch also adds a ALIB_DPTC_ prefix to the IDs and makes
the names more consistent.
TEST=Timeless build for Mandolin results in identical binary.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I75e0504f6274ad50c53faa8fcbde4d6821d85a04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53917
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The other enum entries are control IDs for the
ALIB_FUNCTION_DYNAMIC_POWER_THERMAL_CONFIG ALIB function while
DPTC_TOTAL_UPDATE_PARAMS is the total number of configuration settings
that will get passed as parameter in the ALIB call, so it shouldn't be
part of that enum.
TEST=Timeless build for Mandolin results in identical binary.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0cb9e9d2ba579a74d916011b4ead71cc86d69a24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53916
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The ACPI ALIB function numbers are defined in the AMD Generic
Encapsulated Software Architecture (AGESA™) Interface Specification
(document #55483).
TEST=Timeless build stays the same for Mandolin (Picasso) and Gardenia
(Stoneyridge).
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I290ef0db32c65ebb2bbbe4f65db4df772b884161
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53915
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We can share this with cezanne.
BUG=b:184766519
TEST=Build picasso
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: If746d55345f6b7c828376b64adc5532d20413f68
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52916
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This method signature will also be used by cezanne, so move it to
common.
BUG=b:184766519
TEST=Build picasso
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I421bdad51776278f83148174e6f72bdc38249e54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This function will be reused in Cezanne, so move it from the Picasso
directory to the common FSP integration code.
TEST=On Mandolin Linux finds the AMD SSDT that contains ALIB.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7b256de712fe60d1c021cb875aaadec1d331584b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
For CRBs without Google EC with CONFIG_CHROMEOS=y we will get a build
error as google_chromeec_cbi_get_dram_part_num() is not defined. Use
EC_GOOGLE_CHROMEEC instead of CHROMEOS to gate the call.
BUG=b:184124605
Change-Id: I2b200f4fb11513c6fc17a2f0af3e12e5a3e3e5a1
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52748
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The usage of external oscillator has got nothing to do with Audio
Co-processor (ACP). Hence move it out of common config and put it into
the SoC config where it is being used.
BUG=None
TEST=Build Dalboz and Vilboz mainboards.
Change-Id: I8c5d98addfba750f9ddb87a846599541b4a8340a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
From cezanne we have enough space in PSP so we don't have to worry about
workbuf size. Hence the function only exists in picasso and deprecated
for later platforms.
So wrap svc_get_max_workbuf_size and provide default weak function so
future platforms don't have to implement dumb function for it.
TEST=build and boot zork, check weak function is not called in zork
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I16e8edf8070aaacb3a6a6a8adc92b44a230c3139
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
These addresses will be changed in cezanne. Before start working on
cezanne, move these out to separate header as a clean-up.
TEST=emerge-zork coreboot
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I2499281d250aae701f86bfcc87c7681e5b684b6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Audio Co-processor driver is similar for both Picasso and Cezanne SoCs.
Hence move it to the common location.
BUG=None.
TEST=Builds Dalboz, Trembyle, Vilboz, Mandolin and Bilby mainboards.
Change-Id: I91470ff68d1c183df9a2927d71b03371b535186a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
hdmi2_disable bit0~3 is used to disable HDMI 2.0 function in DDI0~3
BUG=b:179170193
BRANCH=none
TEST=Build; Verify the UPD was passed to system integrated table
Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com>
Change-Id: I383bfd04e01f5202db093105662344869e475746
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Currently, some of the PSP Soft Fuse bits are hardcoded in the Cezanne
and Picasso makefiles.
This makes it impossible for platforms to change them. This change puts
the hardcoded bits in Kconfig, allowing them to be modified by the
platform.
BUG=b:185514903
TEST=Verify that the correct Soft Fuse bits are set.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I190ebf47cb7ae46983733dc6541776bf19a2382f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52422
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
MC0_CTL_MASK is no longer available in fam 17h and newer and will result
in a general protection fault when accessed. This register was moved, so
use the one that is correct for this CPU generation.
BUG=b:186038401
TEST=Mandolin no longer crashes in the machine check error handling path
with a general protection fault.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibb042635d917dfcb2121849e2913aa62eca09dd0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Trying to limit the number of available cores by setting the MAX_CPUS
Kconfig option to a lower value than the SoC's default might result in
cores being enabled in the FSP-S, but not fully initialized in coreboot
which will cause some malfunction. Add a static assert to make sure
that this option isn't changed from the default. To limit the maximum
number of cores, use the downcore_mode and disable_smt devicetree
settings instead.
TEST=Build fails if MAX_CPUS isn't the expected default.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3cfe09f8bb89a2154d37a37398df982828c824f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52611
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Clean up Kconfig and psp_trasfer.h files before copying over to cezanne.
TEST=build, flash and boot on jelboz360
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Ib370d93e23c15a2fe4c46051ed3647d2d067bb10
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52563
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
bl_syscall_public.h is a header file for PSP app, but was used for x86
code to get the definition of PSP_INFO. Move the definition into
psp_transfer.h and do not include bl_syscall_public.h from x86 code.
BUG=none
TEST=build psp_verstage on zork
BRANCH=none
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I0fe011652a47d0ba2939dc31ee3b83f0718a61dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52537
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Clarify that the downcoring is about deactivating physical cores.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib8a9d1cedff995c507c3be72e7665953e1659238
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52554
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Even though the UPD field this information is finally written to is an 8
bit value, the smt_disable option is only a boolean.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iaac49944993a28ffb98a80201effe1238ec60875
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52553
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since the next patch will use a boolean, replace the stddef.h and
stdint.h includes with types.h to have all that we'll need.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0d062c8de29aa3688a911d7887faf592020b33c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52552
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The name of the and_mask parameter was a bit misleading, due to the
function inverting the value. Renaming this into clear and set makes it
more obvious what those parameters will actually do.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If307ab4858541861e22f8ff24ed178d47ba70fe5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52524
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since there are some differences between picasso PSP svc and cezanne PSP
svc, each platform should have their own svc wrapper.
Moreover cezanne PSP will drop unused parameters from
update_psp_bios_dir and save_uapp_data so make wrapper around it.
BUG=b:182477057
BRANCH=none
TEST=build psp_verstage and boot on zork
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I69f998865fc3184ea8900a431924a315c5ee9133
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52307
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
psp_verstage is not specific to picasso. There might be picasso-specific
code but move everything into common as a first step. While developing
psp_verstage for cezanne picasso-specific code will move back to picasso
directory.
BUG=b:182477057
BRANCH=none
TEST=build psp_verstage on zork
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Ifb1df0d82b972f28be2ffebd476c2553cbda9810
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The functionality to restore the previous power state after power was
lost that could previously be enabled by selecting
MAINBOARD_POWER_RESTORE in the mainboard's Kconfig can now be achieved
by selecting POWER_STATE_PREVIOUS_AFTER_FAILURE in the mainboard's
Kconfig instead.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iab9578ebea89651dc2389bf6ca93ca3f3507eb47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The prototype of gpio_add_events() is provided by that header file.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia384c9297ac1e24bf0b1bcce048012a247406f39
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52274
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since Cezanne needs the exact same code, move it to the common directory
and add a Kconfig option to add this functionality to the build.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I04c4295071a3df7afcb4dfd5435b11fb0bf6963f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Add GRXS and GTXS support. Move the gpio method into common place.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I8ba377179d6976cf26ed0dc521d8e4eff051dc85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This override was added to have the SCI mapping configured if GPIO was
used as WAKE_L pin. This however didn't set up the SCI level and trigger
information, so it likely never worked as intended.
Change-Id: I44661f05c8f517ece88714c625603579731d174b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This is only ever called after espi_setup.
55861 - AMD System Peripheral Bus Overview also says that io ranges
should be configured before enabling the BUS_MASTER bit.
BUG=b:183524609
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I074e487d8768a578ee889a125b9948e3aa6c7269
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
