GNUBoot/coreboot-kgpe-d16
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82 commits

Author SHA1 Message Date
Ronald G. Minnich
31101c9201 add the btest mainboard 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2459 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-10-18 15:23:28 +00:00
Ronald G. Minnich
984371554b add irq for keyboard and mouse 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2432 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-09-21 20:55:58 +00:00
Carl-Daniel Hailfinger
cba07dd682 additions and mods for lzma. 
Signed-off-by: Carl-Daniel Hailfinger
Signed-off-by: Ronald G. Minnich


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2413 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-09-14 15:12:36 +00:00
Ronald G. Minnich
e361efd7d7 Add DCON support. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2409 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-09-13 19:29:31 +00:00
Ronald G. Minnich
b59906c1e9 remove dangerous call to normal image; no backup on OLPC 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2399 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-09-07 15:31:27 +00:00
Richard Smith
59ba228f92 - Added suport for enabling USB P4 on the olpc 
USB P4 is disabled by default and we need to setup the mux bits proper
to make it work.  This is the frame work for that.  All thats needed
is the right address values



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2387 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-08-25 05:01:30 +00:00
Ronald G. Minnich
af9cd4d0cf change from AMD for the IRQ10 problem. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2370 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-08-10 03:23:48 +00:00
Stefan Reinauer
8ad7c06535 slightly changed C.D. Hailfinger's precompressed rom stream patch 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2359 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-08-03 16:19:27 +00:00
Ronald G. Minnich
da7ee9fa07 These changes incorporate steve goodrich'es fixes, and one bug that is 
disabled. 

cs5536: add new entires for SB  control etc. 
cs5536.c: chip_enabled function moved to chip_init, so it only gets run
once.
IRQ setup improved
gx2def.h: new defines added
vr.h: new file, with new def's for virtual register control. 
mainboard config.lb: new entries added for nb and sb control.
chipsetinit.c: new controls added -- I forget all the details :-)
grphinit.c: new function added
northbridge.c: new IRQ control added. FlashChipSetup added, controlled
by chip info setupflash struct member. Currently, if enabled, this hangs
OLPC in linux PCI scan.
chip.h: new struct members added for unwanted device enable, flash setup 


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2345 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-07-21 19:21:38 +00:00
Ronald G. Minnich
707097fc1c fix interrupt for f5 (ehci) 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2335 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-06-27 02:26:06 +00:00
Ronald G. Minnich
92e8b809b4 fix typo on duplicate line. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2331 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-06-24 14:46:26 +00:00
Ronald G. Minnich
88fb1a6c37 set up interrupt values for the southbridge, and add a function to 
manage them. Make pci_level_irq global. Add value settings for OLPC
rev_a board. Comment out no-longer-needed code in olpc mainboard.c 
-- it is replaced by the settings in Config.lb, and the support
in cs5536.c


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2328 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-06-22 04:37:27 +00:00
Ronald G. Minnich
2d7bb59018 fix idiiot typo I did not catch. 
add support for conditional enable of uarta interrupt.



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2324 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-06-18 02:28:07 +00:00
Ronald G. Minnich
48415d5cf6 add irq mapper support for OLPC and other boards that need this mapping 
done for the gx2 north. tested on OLPC. 


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2323 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-06-18 01:29:42 +00:00
Ronald G. Minnich
fb93749642 changes from AMD for making OLPC video work. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2316 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-06-10 22:57:15 +00:00
Ronald G. Minnich
890ee09a32 further development of OLPC. Set vsm size to 35k. add PCI IRQ for USB. 
Set linuxbios size to 28k. Drop debug level to 8.



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2315 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-06-08 14:19:49 +00:00
Ronald G. Minnich
bad9d105cf cleanup some of the compressed rom stream ugliness -- more to do! 
olpc and rumba can now boot linux out of flash. vsa was resized to 64K. 
olpc and rumba now used compressed payload -- thanks stefan!


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2307 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-05-18 03:07:16 +00:00
Ronald G. Minnich
5d573c28e7 Commit for IDE NAND FLASH 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2306 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-05-16 02:51:16 +00:00
Ronald G. Minnich
b9a335cb9b correct it, finally. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2304 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-05-12 20:05:08 +00:00
Ronald G. Minnich
6084160f2d memory size in cf07 
goodrich pll code
disable havedmi


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2303 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-05-12 18:42:34 +00:00
Ronald G. Minnich
1656c18d76 reorder early startup so that it might work. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2298 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-05-05 03:54:31 +00:00
Ronald G. Minnich
c01fe5d1b6 more changes; rumba enet works fine now. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2290 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-05-03 03:30:23 +00:00
Ronald G. Minnich
d3ba4aaa24 Fall back to pre-broken settings and setup for GX2. 
We lost a few things, but this is still worth it.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2287 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-05-02 03:07:11 +00:00
Ronald G. Minnich
3716427e7f we don't need msr_init 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2281 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-27 15:10:55 +00:00
Ronald G. Minnich
5ee2bbb90c fix the msr.lo for olpc 0x20000019 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2275 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-25 04:07:44 +00:00
Ronald G. Minnich
2f19800268 fix so that olpc uarts come up enabled. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2272 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-23 19:21:12 +00:00
Li-Ta Lo
bbdaeaf55c change to 5536 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2268 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-20 21:40:20 +00:00
Li-Ta Lo
05c0869fac boot to kernel 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2264 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-20 21:26:01 +00:00
Ronald G. Minnich
61083dad0f add back in missing line 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2258 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-18 21:34:32 +00:00
Ronald G. Minnich
55e10fe3a4 set up timing 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2257 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-18 21:21:10 +00:00
Ronald G. Minnich
170ce333ca add ram resources 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2256 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-18 20:42:58 +00:00
Ronald G. Minnich
df46cb205d added the olpc target and support 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2255 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-18 16:36:58 +00:00