Commit Graph

26815 Commits

Author SHA1 Message Date
Xiang Wang 7db270c25c riscv: fix bug of sifive-gpt.py
The GPT version must be "00 00 01 00" and the little endian should be
represented as 0x10000.

Please refer to: https://en.wikipedia.org/wiki/GUID_Partition_Table

Change-Id: Ib025197fc96f32823e687a89de0cee51c952b031
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/c/29767
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-22 14:48:43 +00:00
Nick Vaccaro 5df5ade696 mb/google/poppy/variant/nocturne: enable USB acpi
Main objective for this change is to export the bluetooth reset
gpio to the kernel for use in an rf-kill operation.
To do so, we enable USB acpi and define all of the USB2 devices,
which includes bluetooth's reset gpio information.

This change produces the following nodes in the SSDT :
    Scope (\_SB.PCI0.XHCI.RHUB.HS01)
    {
        Name (_DDN, "USB Type C Port 1")  // _DDN: DOS Device Name
        Name (_UPC, Package (0x04)  // _UPC: USB Port Capabilities
        {
            0xFF,
            0x09,
            Zero,
            Zero
        })
        Name (_PLD, ToPLD (
            PLD_Revision           = 0x2,
            PLD_IgnoreColor        = 0x1,
            PLD_Red                = 0x0,
            PLD_Green              = 0x0,
            PLD_Blue               = 0x0,
            PLD_Width              = 0x0,
            PLD_Height             = 0x0,
            PLD_UserVisible        = 0x1,
            PLD_Dock               = 0x0,
            PLD_Lid                = 0x0,
            PLD_Panel              = "UNKNOWN",
            PLD_VerticalPosition   = "CENTER",
            PLD_HorizontalPosition = "CENTER",
            PLD_Shape              = "OVAL",
            PLD_GroupOrientation   = 0x0,
            PLD_GroupToken         = 0x0,
            PLD_GroupPosition      = 0x0,
            PLD_Bay                = 0x0,
            PLD_Ejectable          = 0x0,
            PLD_EjectRequired      = 0x0,
            PLD_CabinetNumber      = 0x0,
            PLD_CardCageNumber     = 0x0,
            PLD_Reference          = 0x0,
            PLD_Rotation           = 0x0,
            PLD_Order              = 0x0,
            PLD_VerticalOffset     = 0x0,
            PLD_HorizontalOffset   = 0x0)
        )  // _PLD: Physical Location of Device
    }

    Scope (\_SB.PCI0.XHCI.RHUB.HS03)
    {
        Name (_DDN, "Bluetooth")  // _DDN: DOS Device Name
        Name (_UPC, Package (0x04)  // _UPC: USB Port Capabilities
        {
            0xFF,
            0xFF,
            Zero,
            Zero
        })
        Name (_PLD, ToPLD (
            PLD_Revision           = 0x2,
            PLD_IgnoreColor        = 0x1,
            PLD_Red                = 0x0,
            PLD_Green              = 0x0,
            PLD_Blue               = 0x0,
            PLD_Width              = 0x0,
            PLD_Height             = 0x0,
            PLD_UserVisible        = 0x0,
            PLD_Dock               = 0x0,
            PLD_Lid                = 0x0,
            PLD_Panel              = "UNKNOWN",
            PLD_VerticalPosition   = "CENTER",
            PLD_HorizontalPosition = "CENTER",
            PLD_Shape              = "UNKNOWN",
            PLD_GroupOrientation   = 0x0,
            PLD_GroupToken         = 0x0,
            PLD_GroupPosition      = 0x0,
            PLD_Bay                = 0x0,
            PLD_Ejectable          = 0x0,
            PLD_EjectRequired      = 0x0,
            PLD_CabinetNumber      = 0x0,
            PLD_CardCageNumber     = 0x0,
            PLD_Reference          = 0x0,
            PLD_Rotation           = 0x0,
            PLD_Order              = 0x0,
            PLD_VerticalOffset     = 0x0,
            PLD_HorizontalOffset   = 0x0)
        )  // _PLD: Physical Location of Device
        Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
        {
            GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly,
                "\\_SB.PCI0.GPIO", 0x00, ResourceConsumer, ,
                )
                {   // Pin list
                    0x0062
                }
        })
        Name (_DSD, Package (0x02)  // _DSD: Device-Specific Data
        {
            ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
            Package (0x01)
            {
                Package (0x02)
                {
                    "reset-gpio",
                    Package (0x04)
                    {
                        \_SB.PCI0.XHCI.RHUB.HS03,
                        Zero,
                        Zero,
                        One
                    }
                }
            }
        })
    }

    Scope (\_SB.PCI0.XHCI.RHUB.HS05)
    {
        Name (_DDN, "USB Type C Port 2")  // _DDN: DOS Device Name
        Name (_UPC, Package (0x04)  // _UPC: USB Port Capabilities
        {
            0xFF,
            0x09,
            Zero,
            Zero
        })
        Name (_PLD, ToPLD (
            PLD_Revision           = 0x2,
            PLD_IgnoreColor        = 0x1,
            PLD_Red                = 0x0,
            PLD_Green              = 0x0,
            PLD_Blue               = 0x0,
            PLD_Width              = 0x0,
            PLD_Height             = 0x0,
            PLD_UserVisible        = 0x1,
            PLD_Dock               = 0x0,
            PLD_Lid                = 0x0,
            PLD_Panel              = "UNKNOWN",
            PLD_VerticalPosition   = "CENTER",
            PLD_HorizontalPosition = "CENTER",
            PLD_Shape              = "OVAL",
            PLD_GroupOrientation   = 0x0,
            PLD_GroupToken         = 0x0,
            PLD_GroupPosition      = 0x0,
            PLD_Bay                = 0x0,
            PLD_Ejectable          = 0x0,
            PLD_EjectRequired      = 0x0,
            PLD_CabinetNumber      = 0x0,
            PLD_CardCageNumber     = 0x0,
            PLD_Reference          = 0x0,
            PLD_Rotation           = 0x0,
            PLD_Order              = 0x0,
            PLD_VerticalOffset     = 0x0,
            PLD_HorizontalOffset   = 0x0)
        )  // _PLD: Physical Location of Device
    }

    Scope (\_SB.PCI0.XHCI.RHUB.HS07)
    {
        Name (_DDN, "POGO")  // _DDN: DOS Device Name
        Name (_UPC, Package (0x04)  // _UPC: USB Port Capabilities
        {
            0xFF,
            0xFF,
            Zero,
            Zero
        })
        Name (_PLD, ToPLD (
            PLD_Revision           = 0x2,
            PLD_IgnoreColor        = 0x1,
            PLD_Red                = 0x0,
            PLD_Green              = 0x0,
            PLD_Blue               = 0x0,
            PLD_Width              = 0x0,
            PLD_Height             = 0x0,
            PLD_UserVisible        = 0x0,
            PLD_Dock               = 0x0,
            PLD_Lid                = 0x0,
            PLD_Panel              = "UNKNOWN",
            PLD_VerticalPosition   = "CENTER",
            PLD_HorizontalPosition = "CENTER",
            PLD_Shape              = "UNKNOWN",
            PLD_GroupOrientation   = 0x0,
            PLD_GroupToken         = 0x0,
            PLD_GroupPosition      = 0x0,
            PLD_Bay                = 0x0,
            PLD_Ejectable          = 0x0,
            PLD_EjectRequired      = 0x0,
            PLD_CabinetNumber      = 0x0,
            PLD_CardCageNumber     = 0x0,
            PLD_Reference          = 0x0,
            PLD_Rotation           = 0x0,
            PLD_Order              = 0x0,
            PLD_VerticalOffset     = 0x0,
            PLD_HorizontalOffset   = 0x0)
        )  // _PLD: Physical Location of Device
    }

BUG=b:119275094
TEST=build and flash to nocturne, log into nocturne and
'cat /sys/firmware/acpi/tables/SSDT > /tmp/ssdt.dml', copy
that ssdt.dsml to /tmp/ssdt.dml on host machine,
'iasl -d /tmp/ssdt.dml', then verify that "reset gpio"
shows up in the HS03 node's _DSD package in the table.

Change-Id: I65d9b580fd69fd0a2c84f14b78a8e8b5e9217b16
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/29622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rajat Jain <rajatja@google.com>
2018-11-22 14:48:15 +00:00
Nick Vaccaro 0a495eb658 drivers/usb/acpi: add reset gpio to usb acpi driver
Add ability to define a reset gpio in acpi for a USB device.

BUG=b:119275094

Change-Id: Ife3ea43a1eadf2548aa52b8fbd792e691d7cc7f2
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/29615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rajat Jain <rajatja@google.com>
2018-11-22 14:47:52 +00:00
Werner Zeh f13a6f9e05 sb/intel/common: Reset Pre-OP after atomic SPI cycle is finished
Make sure that the Pre-Op register is cleared when an atomic cycle has
been finished without errors.

Change-Id: Ied88337125b125474b411e2f39f668171d15bfac
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-11-22 14:47:21 +00:00
Subrata Banik 26d706bb33 soc/intel/icelake: Create macros for FSP consumption
1. Modify PCIEXBAR to accomodate Type-C Root Port
2. LPSS device mode selection

Change-Id: Ib7e4bc304f93e4b63ac2d7f194ca441dd96dd943
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/29697
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-22 02:26:33 +00:00
Shelley Chen dd4ef173f1 mb/google/poppy/variants/nami: Split FP MCU Wake and IRQ GPIOS
We are seeing problems (interrupt storm) with using the same gpio for
FP MCU wake and irq signals.  Reverting back to using separate gpios
for wake and irq until we resolve the issue.

BUG=b:119447525, b:115706071
BRANCH=Nami
TEST=Run powerd_dbus_suspend from kernel and make sure see DUT drop
     into S0ix in the EC console.  Also, unlock from lock screen with
     fingerprint.

Change-Id: Id7987f28526256808b8ed49e66f66298f7cdbcee
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/29665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Vincent Wang <vwang@google.com>
2018-11-22 01:38:57 +00:00
Nico Huber 755db95d1a (console,drivers/uart)/Kconfig: Fix dependencies
The dependencies of CONSOLE_SERIAL and DRIVERS_UART were somehow
backwards. Fix that. Now, CONSOLE_SERIAL depends on DRIVERS_UART,
because it's using its interface. The individual UART drivers
select DRIVERS_UART, because they implement the interface and
depend on the common UART code.

Some guards had to be fixed (using CONSOLE_SERIAL now instead of
DRIVERS_UART). Some other guards that were only about compilation
of units were removed. We want to build test as much as possible,
right?

Change-Id: I0ea73a8909f07202b23c88db93df74cf9dc8abf9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-11-21 22:49:48 +00:00
Philipp Deppenwiese 7470c902d8 mainboard/ocp/wedge100s: Add vboot support
* Add RO only FMAP.
* Add kconfig options.

Tested=OCP Wedge100s

Change-Id: I1979e0263e41f21c01c407ac81ad1198a53741e8
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-21 16:03:31 +00:00
Philipp Deppenwiese c14ad8a84d soc/intel/fsp_broadwell_de: Add vboot support
Enable vboot2 in romstage.

Change-Id: I7f1a1e8538999c5e4e54f3a4aa0cdf6d8a309c4f
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-21 16:03:06 +00:00
Piotr Król ef676b143e payloads/tianocore: rebase patches to UDK2018 release
Patches should be applied against edk2 release instead of arbitrary
commit. This aims to simplify Tianocore payload support by other
platforms.

Change-Id: Ib409f6f93eb64d7a9a2f09a75f8e637ab8689410
Signed-off-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/27615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-11-21 15:51:07 +00:00
Nico Huber 3a903426de soc/intel/.../Kconfig: Drop SOC_INTEL_COMMON_BLOCK_I2C_DEBUG
It's dead.

Change-Id: I1fc051937a36878eab23f6022bc42028d5606c83
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-11-21 14:55:42 +00:00
Aamir Bohra 1018be2852 util/ifdtool: Add IceLake platform support under IFDv2
Change-Id: Ib69a2cbc3d8ab9f35c940e95b0edb4b04b50b716
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/1162995
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/29696
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-21 13:45:52 +00:00
Elyes HAOUAS 0cca6e24b7 ACPI: Fix DSDT's revision field
DSDT revision is =1 for ACPI v1 and =2 for greater ACPI version.
This will cause the AML interpreter to use 32-bit integers and math
if the version is 1, and 64-bit if the version is >=2.
Current spec version is 2 for ACPI 6.2-a.

Change-Id: I77372882d5c77b7ed52dcdd88028403df6f6fa7f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29626
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-21 12:12:04 +00:00
Sumeet Pawnikar 15209ce39a mb/google/octopus: Update TSR1 threshold settings
Update passive temperature threshold value from 50C to 52C and
critical temperature threshold from 90C to 80C for TSR1 sensor.

BUG=b:79779737
TEST=Build and verified on Bobba/Bobba360/Sparky/Sparky360 boards

Change-Id: Iffef8afe0f1c6c80a6ae8ecb831aaf749443980e
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/29264
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-21 12:10:53 +00:00
Elyes HAOUAS 5ba184000b src/cpu/intel/Kconfig: Remove dead source
fsp_model_206ax was removed in Change-Id: I7b6bc4bfd

Change-Id: If77426fcb9f30f3e8b79d7c134053276701a5ecc
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-11-21 12:10:19 +00:00
Frans Hendriks f2af702df9 soc/intel/braswell: Disable OS use of HPET
The timer interrupts don't appear when HPET is enabled. This
result in Linux reporting 'MP-BIOS bug: 8254 timer not connected
to IO-APIC'
Enabling CONFIG_DISABLE_HPET disables OS use of HPET.
Intel issue 4800413 (doc #5965535) reports Windows7/Ubuntu Installation
Hang or Slow Boot Issue.

BUG=Intel #4800413
TEST=Portwell PQ7-M107

Change-Id: Ie9a78dcc736eb057c040a0a303c812adb1f76f3c
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2018-11-21 12:08:45 +00:00
Elyes HAOUAS ef169d6cc6 nb/intel/haswell: Move MMCONF_BASE_ADDRESS to northbridge Kconfig
Change-Id: I44f27405fc8ccbe54c7d19b70327da866390a156
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/28603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2018-11-21 12:08:22 +00:00
Duncan Laurie 2aef7f3cec soc/intel/cannonlake: Fix IO decode setup
This change makes the early IO decode setup mirror that of other
Intel SOCs and fixes issues with COM1 not being enabled properly.

Tested by successfully successfully receiving serial output from
an 8250IO UART device at the standard 0x3f8 base address.

Change-Id: I9bd894fea62b78b81e5c80b5e88a539ebddac2df
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2018-11-21 01:34:58 +00:00
Nico Huber 3eb720c36e drivers/uart/Kconfig: Be smarter about DRIVERS_UART_8250IO
It defaults to y to avoid having to select it per mainboard. But that
makes a mess because it results in linker conflicts unless other UART
drivers disable it explicitly.

We try to be smarter about the default value for now. The real solu-
tion would be to hardcode it per mainboard. But who knows which boards
actually have it?

Change-Id: I7e755fe0e4f6d1c31ef2854603a5510c3cdc4967
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29571
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-20 17:48:30 +00:00
Subrata Banik 87ca3898f9 soc/intel/{common, skylake}: Make ASPM enabling as common PCH feature
This patch moves required Kconfig selection for enabling ASPM feature
(like clk_pm, L1 state etc) from soc code  to intel common pch base code.

TEST=Run lspci -vvv | grep ASPM
The output shows the ASPM L1 is enable for pci devices

Change-Id: Ic77602a75f0c9ccf28ebfd57e53433dc90985a16
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/29653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-19 19:42:06 +00:00
Elyes HAOUAS c1fa44091e mb/pcengines/apu2: Use IS_ENABLED(CONFIG_APU2_PINMUX_{GPIO*,UART_*})
Change-Id: Ie5f73453a8cc12be5f18d8e7f0462ce3f38bb9d8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29585
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-19 16:39:00 +00:00
Ivy Jian 977778f9f0 mb/google/kahlee/variants/delan: Enable Weida touchscreen device
This change adds ACPI properties for WDT8752A device.

BUG=b:117174180
BRANCH=master
TEST=Verify touchscreen on delan works with this change

Change-Id: Id1484a482de6282c97f3aac329f217bbcb7dbd18
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2018-11-19 16:38:40 +00:00
zaolin 3313a78e36 northbridge/intel/fsp_*: Remove legacy SoCs
* Remove FSP Sandy/Ivybrige which are unused.
* Open Source implementation isn't final but
  good enough to replace FSP version.
* For new ports use NORTHBRIDGE_INTEL_IVYBRIDGE
  and NORTHBRIDGE_INTEL_SANDYBRIDGE

Change-Id: I7b6bc4bfdd0481c8fe5b2b3d8f8b2eb9aa3c3b9e
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/29402
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-19 15:43:37 +00:00
Patrick Rudolph 0b8aefc656 Documentation: Add W530 / T530
Change-Id: Ib253308737f8c7a497c6ca13eab88220b1ac27ad
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/29685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-11-19 09:34:38 +00:00
Arthur Heymans a29498f599 util/bucts: Add tool to manipulate BUC.TS bit on Intel targets
The purpose of this tool is to manipulate and get information about the
`Back Up Control, Top Swap` mechanism present on most Intel Southbridges.

This tool is initially written by Peter Stuge.

This tool makes it possible to have a backup mechanism for the
bootblock by using the southbridges Back Up Control Top Swap.

Sometimes it is also possible to circumvent vendor write protection mechanisms
in order to flash coreboot. An example of where this would be useful would be
the Lenovo Thinkpad X60 and T60.

Change-Id: I12cc2e91396f096fc979e23848e1929cb6c44fc5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18224
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-19 08:19:16 +00:00
Elyes HAOUAS 0ce41f1a11 src: Add required space after "switch"
Change-Id: I85cf93e30606bc7838852bd300a369e79370629a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-19 08:17:06 +00:00
Elyes HAOUAS 16f9bf83e0 cpu/intel/socket_mFCPGA478/Kconfig: Add MODEL_6{9,D}X
Makefile.inc uses already model_6{9,d}x subdirs.

Change-Id: I0bfc179a83fab85e5b924751e026d906d01b3fb6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-19 08:13:49 +00:00
Nico Huber 371a6674ac soc/intel/.../Kconfig: Move GPIO debug option into debug menu
Rename DEBUG_SOC_COMMON_BLOCK_GPIO to DEBUG_GPIO and move it into the
Debugging menu.

Change-Id: I737d0ee7fb5423b6d16d611a144d43fd3f168a2c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-11-18 21:20:58 +00:00
Nico Huber b2b3ab7c43 soc/intel/common/*/Kconfig: Remove redundant comments
Change-Id: Ide9608e487793fa4a8b0e291ba168126e0484355
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-11-18 20:57:28 +00:00
Subrata Banik 47df66d765 soc/intel/{cnl, icl}: Remove unnecessary __SIMPLE_DEVICE__ check
soc_pch_pirq_init() function is only getting compiled for RAMSTAGE
hence remove unused __SIMPLE_DEVICE__ check.

Change-Id: I7f0ca62170f0af12a251c8c97155de8433a31854
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/29643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-18 20:57:11 +00:00
Angel Pons d4b89091d2 mb/asus/p5qc: Add p5ql_pro mainboard as variant
Working:
 - SATA on southbridge ports
 - SATA on Marvell IDE controller ports
 - USB
 - COM1
 - PS/2 keyboard
 - DDR2 DIMMs
 - PCIe x16 PEG port
 - PCIe x1 ports
 - PCI ports
 - NIC (MAC address needs to be set in Kconfig or in a CBFS file)
 - S3 resume
 - Green audio line out connector (the rest is untested)

Not working:
 - Floppy port. Does not seem to be mainboard-specific, though.

Untested:
 - EHCI debug

TODO:
 - Add documentation

Change-Id: I6ed434a691e8ef2a61e0acb1f986a59b8e1ad818
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/25691
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-18 17:44:44 +00:00
Patrick Georgi 94b761c8ed util/board_status: run dmesg with sudo
Newer kernels only allow root to access the kernel log buffer.
In another case (cbmem) we use sudo to get past that, so we can
expect sudo to be available here, too.

Change-Id: I654422992e5ba1e98a786f65d50289efbcd46602
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/29670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-11-18 17:12:17 +00:00
Elyes HAOUAS 1abbf0e91d sb/amd/{agesa,pi}/hudson/Kconfig: Remove unused HUDSON_FWM
Change-Id: Ib621fe01a1d1d026153124a9d46f26e31df6d818
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-18 09:13:55 +00:00
David Wu 54788655f7 mb/google/fizz/variants/karma: Increase Pmax to 151 for all SKUs
Needs to increase ROPmax to 80W (includes both panel and audio),
hence the Pmax = 71W (PL4) + 80W (ROPmax) = 151W.

BUG=b:119644629
BRANCH=master
TEST=USE=fw_debug emerge-kalista chromeos-mrc coreboot chromeos-bootimage
         & ensure the Pmax value is passed to FSP-S.

Change-Id: I504ff66a218bf4e385270c2cb385a83dca312a81
Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-18 09:13:37 +00:00
Mario Scheithauer 5716b4c358 siemens/mc_apl5: Add new mainboard variant mc_apl5
This mainboard is based on mc_apl1. In a first step, it contains a copy
of mc_apl1 directory with minimum changes. Special adaptations for
mc_apl5 mainboard will follow in separate commits.

Change-Id: Icdbb116a822ffa7a3bfb7026a5d1164db56a0c46
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-18 09:13:06 +00:00
Angel Pons 7ec15c82f4 util: Fix shebang for python2 scripts
Python 3 is the default Python interpreter on most modern systems.
Python 2 scripts must specify they should be run with Python 2 in their
shebang. Solves issue raised in CB:28953.

Change-Id: I9ace4afd668539c05e7ace30e255af50c7a069c2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/29666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-18 09:12:22 +00:00
Patrick Rudolph 5a61cc5d22 cpu/qemu-x86: Fix CPU driver
There's a typo in the cpu driver causing it to always use the weak
implementation defined in the devicetree instead of the real
implementation.

Tested on qemu-q35, the CPU driver contains valid values.

Change-Id: I4a6bb447bfdb3df6053c0df8be9d7c6aa8f689be
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/29675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-18 09:12:15 +00:00
Arthur Heymans 0115606286 mb/intel/dg43gt: Add documentation
Change-Id: I4e9dc67e66f719d440679b11332e2c8a764024f4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-11-17 16:51:43 +00:00
Angel Pons e0e98eb11d src/mb/asus/p5qc/gpio.c: Allow specifying a gpio.c in Kconfig
Even though these two mainboards use the same gpio.c file, other boards
such as the p5ql_pro do not.

Change-Id: I2f7c8c12cb1bdcf47f3b4d4cef0b11e44a5b8863
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/29447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-17 15:28:36 +00:00
Patrick Georgi 68aed91eb9 intel/i945: Fix booting on a dual channel configuration
The register values in dram width programming changed in
commit a4fc7bef7f which broke booting on getac/p470.

TEST=getac/p470 with 2 X8DDS DRAM boots again

Change-Id: I8b3eedc8c5234e8a28948d4dc58bf565024f62ce
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/29663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr>
2018-11-17 13:27:43 +00:00
Subrata Banik 8ad5a62de9 soc/intel/icelake: Make static IRQ mapping for PIC mode
This patch makes static PIRQ->IRQ mapping, where IRQ10 is mapped
to PBRC and IRQ11 is mapped for PARC/PCRC/PDRC/PERC/PFRC/PGRC/PHRC.

Change-Id: I9693f2a52529961e6b611b69e389f01f77f77d63
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/29509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-17 09:37:19 +00:00
Subrata Banik 990db2213f soc/intel/icelake: Make static IRQ mapping for ICP PCH pci devices
Since PIRQ->IRQ mapping registers PxRC are not available after FSP-S call
due to PCH requirement change from CNP PCH onwards, hence making static IRQ
mapping for pci_irqs.asl and pcie.asl

Also remove unused irqlinks.asl from soc/intel/icelake/acpi/

Change-Id: Idec00c3b8a97cb5aa7b4000840aba914aea478c9
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/29508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-17 09:37:09 +00:00
Yegor Timoshenko c2e4941367 treewide: use /usr/bin/env where appropriate
Some Unix systems (GuixSD, NixOS) do not install programs like
Bash and Python to /usr/bin, and /usr/bin/env has to be used to
locate these instead.

Change-Id: I7546bcb881c532adc984577ecb0ee2ec4f2efe00
Signed-off-by: Yegor Timoshenko <yegortimoshenko@riseup.net>
Reviewed-on: https://review.coreboot.org/28953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-17 07:32:03 +00:00
Shelley Chen 15316e2321 mb/google/poppy/variants/nami: Invert FP MCU wake signal
GPP_D6 needs to be inverted to enter S0ix because FPMCU_INT_L is
active low.  Keeps device awake otherwise.

BUG=b:119447525, b:115706071
BRANCH=Nami
TEST=Run powerd_dbus_suspend from kernel and make sure see DUT drop into
     S0ix in the EC console.

Change-Id: Iad5df124e2439bbdc078d6a33f8d0510d25ecf6f
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/29650
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-17 07:30:15 +00:00
Duncan Laurie bf2710e849 mb/google/sarien: Set SMBIOS mainboard SKU
Setting sku_id() is not enough to get a value to show up in the SMBIOS
tables, it also needs to be returned as a string for the table creation
to consume.  This change defines the smbios_mainboard_sku() function
and returns a string constant of "sku#" as expected.

Change-Id: I03013bab89d53d1eba969c6ffb7e95fcbb315a81
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Trent Begin <tbegin@google.com>
2018-11-17 07:26:49 +00:00
Lijian Zhao 79152f3c81 soc/intel/cannonlake: Add options for pcie ltr
FSP can support enable/disable Pci express LTR (Latency Tolerance
Reporting) mechanism through upd interface. Include that into coreboot
side.

BUG=N/A
TEST=N/A

Change-Id: I69b423afa4f81a2d58375734bba07792e08931d5
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/29642
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-17 07:25:54 +00:00
Elyes HAOUAS 28114ae71b SMBIOS: Remove duplicated smbios_memory_type enum
Change-Id: I49554d13f1b6371b85a58cc1263608ad9e99130e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-11-16 15:48:04 +00:00
Elyes HAOUAS 0acb28a9c0 {soc,sb}/amd: Remove unused SOUTHBRIDGE_AMD_*_SKIP_ISA_DMA_INIT
Change-Id: Ic9bca9a56663926a153b93c298f69ba7d26f6e5e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-16 14:25:10 +00:00
Vadim Bendebury 98485de881 util/cbsftool: allow enabling verbose make output
Sometimes it is necessary to be able to see exact command lines used
when compiling and linking. Use the same scheme as some other
Makefile's - enable verbose output when variable V is set to 1.

TEST=tried building cbfstool with V=1, observed verbose output.

Change-Id: Iff25439aabff79e69d1d94a2c51c60bb0e0d7b80
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/29431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16 12:59:09 +00:00
Sumeet Pawnikar 36c1719143 mb/google/octopus/variants/bobba: Set tcc offset for bobba
Change tcc offset from 0 to 10 degree celsius for bobba.

BUG=b:118099582
TEST=Cross verified the value using TAT UI.

Change-Id: I68527c27635844f4edb0dda5f6018589d7bae297
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/29636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-11-16 12:56:50 +00:00