The NPCD378 can be found on at least:
* HP Compaq 8200
* HP Compaq 8300
The datasheet is not publicly available, as HP implements lots of
custom hardware. Add basic support for it, based on HP Compaq 8200.
The first eight LDNs seem to be standard nuvoton compatible, except for
LDN4, which is used to control front LED and power in ACPI S3.
LDN8 provides access to HP's proprietary HWM which is accessiable at the LDN's
IOBASE with a size of 0x100 bytes.
The HWM consists of 16 pages with each holding 0xff bytes. The pages can be
selected by writing the page index to IOBASE + 0xff.
TODO:
Reverse engineer the HWM to support fan control.
WARNING:
The remaining LDNs have been guessed and might be wrong!
The serial has been tested and is working.
Change-Id: Ib497fd41b88e9c159eeeffa69bc2bfdccee9cb38
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/25384
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch ensures that user can pass a function with given argument
list to execute over APs.
BUG=b:74436746
BRANCH=none
TEST=Able to run functions over APs with argument.
Change-Id: I668b36752f6b21cb99cd1416c385d53e96117213
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
In order to extend the MP callback infrastructure prepare for
easier changes by making the AP callback get signalled by a
single pointer to a local variable on the signaller's stack.
When the APs see the callback they will copy the structure
to a local variable and then set the acknowledgement by
clearing out the slot.
The reading and writing to the slots were implemented using inline
assembly which forces a memory access and a compiler barrier.
BUG=b:74436746
Change-Id: Ia46133a49c03ce3ce0e73ae3d30547316c7ec43c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/26043
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adapt the programming of initial DLL values for DDR3.
Change-Id: I67e48b4ae6f2076399133ba7b98ab1dfc0e0ab08
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Also throws in some minor fixes like the wrong conditional for
bankmod and using real CAS when programming MCHBAR(0x248).
Change-Id: Ia2494684ec66d84d4dc27c6a6b425a33ace6e827
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19873
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Adds nmode to the sysinfo struct as it is needed later on.
Change-Id: Ia2ca4a200a1c813b2133eb1004fbe248fa3de9ce
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19872
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A few values were wrong, but it does not seem to matter all that
much.
Change-Id: I86b70e06c81817854994b7feddf9f3638fd16198
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19871
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This memory controller supports both DDR2 and DDR3 memory, yet many
functions have ddr2 in their name while not being ddr2 specific.
This patch renames those to avoid confusion.
Change-Id: Ib3d10014f530905155e56fc52706edb4ab9f5630
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Since this memory controller supports both DDR2 and DDR3 allow it to
decode both while making the dram type mutually exclusive.
Change-Id: I8dba19ca1e6e6b0a03b56c8de9633f9c1a2eb7d7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Some things in programming registers related to dual channel
interleaved operation were wrong.
This also adds some code that could in the future be used when me is
active and claims some memory for its UMA.
This also uses some more sensible variable names to clarify at least
some of the magic.
This fixes memtest86+ failing with some assymetric DIMM configuration.
TESTED on DG43GT: memtest86+ now succeeds on many more different DIMM
configuration setups (would instantly fail at addresses above 4G on
many configurations).
Change-Id: If84099d27100e57437bf214dc4cf975f67c2ea1f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add an lpc_acpi_name function to report its namespace as "LIBR"
rather than some fallback value which seems to vary. This repair
is required for the LPC TPM device to register its presence
without blowing up the table and preventing the payload from
seeing the SATA device.
Before change (but after other similar change to PCI0), the
TPM device reported itself as:
\_SB.PCI0.LPC0.TPM
After change, the TPM device reports as:
\_SB.PCI0.LIBR.TPM
which is consistent with the tables AGESA generates.
Change-Id: Ifa3a0e386cc00062855331e5f9d1c00d6541c238
Signed-off-by: Kevin Cody-Little <kcodyjr@gmail.com>
Reviewed-on: https://review.coreboot.org/26205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add a function domain_acpi_name to return "PCI0", rather than
falling back to the parent' device's "\_SB" label. This repair is
required for the LPC TPM device to register its presence without
blowing up the table and preventing the payload from finding SATA.
Before change, the TPM device reported as:
\_SB.\_SB.LPC0.TPM
After change, the TPM device reports as:
\_SB.PCI0.LPC0.TPM
A separate change submission will correct "LPC0" as well.
Change-Id: I5e8d4715c9b42f50c84dd65818e4b0fdfc9d54f9
Signed-off-by: Kevin Cody-Little <kcodyjr@gmail.com>
Reviewed-on: https://review.coreboot.org/26204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
I'm increasing the max because when AGESA tracing is enabled it will use
over 120 entries. I added some padding to the number incase more probes
are added. This only affects ramstage so the extra ram shouldn't matter.
BUG=b:64549506
TEST=boot on grunt and ran cbmem -t
Change-Id: I7a3d2d09c91c9e302d139e7f65fa9c85c4594de4
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/26234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This will allow loading of programs that are more than one type,
e.g. ramstage type might now be a stage or payload.
Further, unknown types of 0 are dangerous, make it a real value.
Change-Id: Ieb4eeb7c5934bddd9046ece8326342db0d76363c
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/26242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Had 0x2e hardcoded, which is often the SuperIO chip. Instead,
pull the port from the PNP tree generated from devicetree.cb,
where either 0x4e or 0x2e will be specified.
Change-Id: I4a92693f8acd3a1618cefcdf6b25eb22a727e20f
Signed-off-by: Kevin Cody-Little <kcodyjr@gmail.com>
Reviewed-on: https://review.coreboot.org/26203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
If the timestamp entries are added out of order, the duration
calculation will be wrong.
AGESA collects timestamp data through all the stages. Then in AmdInitPost
it asks for a buffer to write TP_Perf_STRUCT into. agesawrapper will then
take the data and call timestamp_add on each entry. This results in
the entries being out of order.
TEST=Built firmware for grunt that manually added entries and then ran
cbmem -t/-T to verify the entries were in the correct order.
Change-Id: I6946a844b71d714141b3372e4c43807cfe3528ad
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/26168
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is based on the code from the 8470p port. Tested on the quad
core/quad SODIMM version. This laptop uses discrete MXM 3.0b graphics
cards. Tested working with both Quadro K3000M and GTX 980M 8GB. The
laptop must be completely disassembled down to the motherboard to
perform the initial flash, subsequent flashes can be done internally
via flashrom. There is a simple mod that can be performed to make
subsequent external flashes easier in case of a brick, I'll put more
information on this on the wiki later. The lack of an MXM structure
built in to the firmware causes the GPU to enter a mode with nerfed
performance, there is a workaround though, I'll add this to the wiki
as well. I have no info on EHCI debugging.
Tested and working:
- memory: 4G+4G, 4G+4G+4G+4G
- Linux (Debian Stretch with kernel 4.9.0) booted from SeaBIOS payload
with graphics init disabled in coreboot. I allowed SeaBIOS to load the
VBIOS from the MXM.
- WLAN
- keyboard, trackpoint and touchpad
- USB
- serial port on dock
- fan control
- VGA
- DisplayPort
- Audio
- Both HDD SATA ports, ODD SATA, eSATA
- S3 with SeaBIOS 1.11, SERCON must be disabled
- Brightness and volume FN keys
- Mute and calculator hotkeys
- Status LEDs
- Bluetooth
Not working:
- GRUB2 as payload will freeze. Has something to do with at_keyboard
module. The built in keyboard requires this module to function though.
- Sleep FN key
- WiFi toggle and internet browser hotkeys
- S3 fails to resume (restarts) if the laptop is removed from AC power,
or gets unplugged and then plugged back in while suspended. Sleep
status LEDs remain normal during this process.
Change-Id: Ic4ff64e9cf0c7a51ac48ca2fe6fe8beab02e9f9a
Signed-off-by: Robert Reeves <xiinc37@gmail.com>
Reviewed-on: https://review.coreboot.org/23651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
The VIA CPUs allow setting the CPUID vendor, which is best read as
a character string.
Change-Id: I67f77ca75f7d77e47b3ba09bad904df5805e373a
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/18257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
VIA c3 & C7 use the the family of 0x6 and model 10, but are not quite
Pentium III.
Change-Id: I85e9853b42cfd20db46db0bd244620d6813bc826
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/18256
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Copies the common/env_ctrl support code from the it8728f driver.
Tested on an ASUS AM1I-A using Linux 4.16.7-gentoo as payload,
and booting userspace without a kexec call.
Prior to this change, an error was given during boot:
it87 it87.656: Detected broken BIOS defaults, disabling PWM interface
After this change, the message is gone, and PWM fan control works
through the /sys/class/hwmon interface.
Change-Id: Id97c4ec19562e7c78308c5afe6ff7c938922c9e7
Signed-off-by: Kevin Cody-Little <kcodyjr@gmail.com>
Reviewed-on: https://review.coreboot.org/26224
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 0ff9daac45.
It points to a stale commit under review; i.e. not to a commit on
blob.git's master branch like it's supposed to.
Change-Id: I19cb8a32b3971c3104e381673ca08ae4d3979128
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This change adds board-specific implementation of
mainboard_vbt_filename which returns "vbt.bin" by default. This is in
preparation to allow multiple vbt binaries to be added to single
image. More sku_id specific names will be added in follow-up CLs.
BUG=b:79396300
Change-Id: I3821d55bfbe9e5773bd2eb0b0003045a80158d8c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
My bad, it seems the acronym for Broadwell is BDW, and not BDL, so
I'm renaming librem_bdl into librem_bdw and changing the KConfig
options accordingly.
Change-Id: I8e992aa3474863236adf8893fcbe37c1b801fa25
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/26237
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In 4a3956d7 (drivers/intel/gma, soc/intel/common: improve
cooperation) the vbt_size parameter was not honored leading to
the use of unitialized variables from the caller. Instead, keep
track of if the vbt is already loaded by using the size returned
from the load. If it's non-zero the vbt has been loaded.
BUG=b:79562868
Change-Id: Ia1c47f0d982fae74e0223922f83943c68a846aa9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/26236
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Current VBT setting for T8 is only 1ms which is under Innolux
N116BCA-EA1 panel's spec.
Modify T8 to 100ms.
(Innolux's panel's spec requires T8 needs to be greater than 80ms
BUG=b:78541692
BRANCH=master
TEST=emerge-coral depthcharge coreboot chromeos-bootimage
Run on DUT and check panel sequence meets spec.
Change-Id: I5f9103aca7871095a828a74cd6a97e1951adb81f
Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com>
Reviewed-on: https://review.coreboot.org/26214
Reviewed-by: Ren Kuo <ren.kuo@quantatw.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Without it the PS/2 keyboard doesn't work after booting into the OS.
Change-Id: Idcb0ea0779fcd5dfd6e0fbf33a532ecf0caec420
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/26131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Adding new librem_bdl variant for the Librem 15 v2, which is very similar
to Librem 13 v1, with the following differences:
- SATA ports 0 and 1 instead of 0 and 3
- SATA DTLE IOBP value is 7 instead of 9 for port 0
- There is no LAN device
- There are two SODIMM slots, and DQs are interleaved
- USB ports are different
Change-Id: Ifaca382a540d085e6c919daa992a0fbd52643a5b
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/26184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Convert the purism/librem13v1 to a variant setup, in
preparation for adding the librem15v2 board as a new variant.
The Librem 13 v1 and Librem 15 v2 are nearly identical, so
this minimizes new code to add support for the latter.
Also update the URL in board_info to an archive.org link.
Change-Id: I00bb82b9e895e2464ddaa92915c01ce0e35933a2
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/26183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Use of device_t has been abandoned in ramstage.
Change-Id: I69c8b95ff1937c0b08147d9e26a3118c58129cf5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit adds support for writing ACPI _PLD structures that
describe the physical location of a device to the OS.
This can be used by any device with a physical connector, but is
required when defining USB ports for the OS.
A simple function is provided that generates a generic _PLD
structure for USB ports based on the USB port type.
Change-Id: Ic9cf1fd158eca80ead21b4725b37ab3c36b000f3
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit adds support for writing ACPI _UPC structures that
help describe USB ports for the OS.
This is a simple structure format which indicates what type of
port it is and whether it is connectable. It should be paired
with an ACPI _PLD structure to define USB ports for the OS.
Change-Id: Ide3768f60f96e9ad7f919ad3fb11d91045dc174a
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit adds support for describing USB ports in devicetree.cb.
It allows a USB port location to be described in the tree with
configuration information, and ACPI code to be generated that
provides this information to the OS.
A new scan_usb_bus() is added that will scan bridges for devices so
a tree of ports and hubs can be created.
The device address is computed with a 'port type' and a 'port id'
which is flexible for SOC to handle depending on their specific USB
setup and allows USB2 and USB3 ports to be described separately.
For example a board may have devices on two ports, one with a USB2
device and one with a USB3 device, both of which are connected to an
xHCI controller with a root hub:
xHCI
|
RootHub
| |
USB2[0] USB3[2]
device pci 14.0 on
chip drivers/usb/acpi
register "name" = ""Root Hub""
device usb 0.0 on
chip drivers/usb/acpi
register "name" = ""USB 2.0 Port 0""
device usb 2.0 on end
end
chip drivers/usb/acpi
register "name" = ""USB 3.0 Port 2""
device usb 3.2 on end
end
end
end
end
Change-Id: I64e6eba503cdab49be393465b535e139a8c90ef4
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
* This feature embedds RST into markdown for
table generation.
For more information, see
http://recommonmark.readthedocs.io/en/latest/index.html#autostructify
Change-Id: Iefebb3b7857bc98818e345f7d0e95fbf987305a8
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/26190
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds a new SPD entry for samsung's new 4GB memory and updates
atlas to use it instead of the previous gen memory.
BUG=b:79444337
TEST=booted on atlas
Change-Id: I19567736c45a1321586378c3d964c2cbebe24755
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/26185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This keeps Audio clock and data pins ON in S0ix to support
Wake on Voice.
BUG=b:77605180
BRANCH=none
TEST=Checked that S0ix suspend/resume works. Validation of WoV
was done on glkrvp previously. For Yorp, audio topology firmware
updates are required for testing WoV.
Change-Id: Idafe4e7d24fe16f8e8ff3dd86e299776ea860d03
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/26202
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This moves the blobs submodule marker forward to include the following:
b45abbd cpu/intel: microcode: add license agreement
1d37962 cpu/intel: add microcode updates 20180312 for new CPU models
8b8bbce cpu/intel: apply microcode updates 20180312 to currently tracked models
in short: bump Intel's microcode updates to the latest version. This
includes Spectre/Meltdown mitigations.
Change-Id: I4ab74ae0bdcf2a109b0697ad233fbb812b5c4544
Signed-off-by: Martin Kepplinger <martink@posteo.de>
Reviewed-on: https://review.coreboot.org/25505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Was never used for the boards in our tree.
Change-Id: Ib9e9ab25ccb8d1d556fdeb8bb4c6558f25bb81b6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The patch series ending in 64049be (lib/bootmem: Add method to walk OS
POV memory tables) expanded the bootmem framework to also keep track of
memory regions that are only relevant while coreboot is still executing,
such as the ramstage code and data. Mixing this into the exsting bootmem
ranges has already caused an issue on CONFIG_RELOCATEABLE_RAMSTAGE
boards, because the ramstage code in CBMEM is marked as BM_RAMSTAGE
which ends up getting translated back to LB_RAM in the OS tables. This
was fixed in 1ecec5f (lib/bootmem: ensure ramstage memory isn't given to
OS) for this specific case, but unfortunately Arm boards can have a
similar problem where their stack space is sometimes located in an SRAM
region that should not be made available as RAM to the OS.
Since both the resources made available to the OS and the regions
reserved for coreboot can be different for each platform, we should find
a generic solution to this rather than trying to deal with each issue
individually. This patch solves the problem by keeping the OS point of
view and the coreboot-specific ranges separate from the start, rather
than cloning it out later. Ranges only relevant to the coreboot view
will never touch the OS-specific layout, to avoid the problem of losing
information about the original memory type of the underlying region that
needs to be restored for the OS view. This both supersedes the
RELOCATABLE_RAMSTAGE fix and resolves the problems on Arm boards.
Change-Id: I7bb018456b58ad9b0cfb0b8da8c26b791b487fbb
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/26182
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to ACPI 6.1 spec 19.6.44, External informs compiler that
object is external to this TABLE, no necessary for object in same DSDT
tables.
A name cannot be defined and declared external in the same table (GPID)
A name cannot be defined and declared external in the same table (CTOK)
Change-Id: Ica80b59ad6a8af865bf1551ac4e014ec5f4e7d08
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26122
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch updates the below:
1)
Nocturne board has only Max98373 speaker amp.
Update both NHLT and DT entries to include only Max98373
and not include DA7219.
2) I2S2 is used for Boot Beep.
So, update GPP_F0 ~ F2 pins accordingly.
3) Include DMIC-4ch configuration.
BUG=b:79362472
TEST=None [Waiting for HW to verify]
Change-Id: I0e9b3a564c22de6e84e96e5e937a3aca4ae73d75
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/26143
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the Video Bios Table to improve user experience when running
coreboot's blob free graphics init.
As it's not a binary blob it should not be added to the blobs repo.
This is taken from vendor BIOS and contains purely documented
configuration data, so it should not be subjected to copyright.
Extracted using intelvbttool with applied patch
I8cbde042c7f5632f36648419becd23e248ba6f76 "util/intelvbttool: Rewrite tool"
Change-Id: I15573ddd37ee9738df1f7178f967131687a50f48
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/25926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Patrick Rudolph