Rename soc_validate_fsp_version to soc_validate_fspm_header, since it
can not only be used to check the version info in the FSP-M binary's
header, but also to check every other field in the binary's header. This
is a preparation for a follow-up patch that implements this function to
check the FSP-M binary's size.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ifadcfd1869bea0774dc17b69c5d1e1c241a45de1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The FSP-M binary needs to fit into the memory region that starts at
FSP_M_ADDR and is FSP_M_SIZE bytes large, so error out during build time
if the uncompressed FSP-M file is larger than the size of the region it
will be copied into.
BUG=b:186149011
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ice4a59e5a723c3c0a40b1f3f3227aee6b9dcb39a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Sounds like we prefer to have this under drivers/ instead of device/.
Also move all MIPI-related headers out from device/ into their own
directory.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ib3e66954b8f0cf85b28d8d186b09d7846707559d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Create the dewatt variant of the guybrush reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0.)
BUG=b:196460993
BRANCH=None
TEST=util/abuild/abuild -p none -t google/guybrush -x -a
make sure the build includes GOOGLE_DEWATT
Signed-off-by: Bhanu Prakash Maiya <bhanumaiya@google.com>
Change-Id: I57860a7cad1bf202bd3ef3eed5f498fbf1d29af8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57108
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
clang seems to like to do some aggressive optimizations that break our
approach of mocking functions for test by using objcopy to turn them
weak after the fact on individual compiled object files. For example, in
CB:56601 the function cbfs_get_boot_device() is mocked this way. When
compiling the cbfs_boot_lookup() function in src/lib/cbfs.c with clang,
it will generate a normal callq instruction to a relocation for
cbfs_boot_lookup(), which can then later be pointed to the mocked
version of that function. However, it will also somehow infer that the
version of cbfs_boot_lookup() in that file can only ever return a
pointer to the static local `ro` variable (because CONFIG_VBOOT is
disabled in the environment for that particular test), and instead
generate instructions that directly load the address of a relocation for
that variable into %rdi for the following call to cbfs_lookup(), rather
than using the real function return value. (Why it would do that is
anyone's guess because this seems unlikely to be faster than just moving
the function return value from %rax into %rdi like a normal compiler.)
Long story short, this optimization breaks our tests because
cbfs_lookup() will be called with the wrong pointer. clang doesn't
provide many options to disable individual optimizations, so the only
solution seems to be to make clang aware that the function is weak
during the compilation stage already, so it can be aware that it may get
replaced. This patch implements that by marking the mocked functions
weak via #pragma weak lines in the per-test autogenerated config header.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I1f9011f444248544de7a71bbefc54edc006ae0cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Cannon Point PCH-H does not implement the eMMC, I2C4 and I2C5 devices.
Guard the IRQ constraints for these devices to prevent FSP assertions.
Tested on Prodrive Hermes, debug FSP builds no longer fail to boot.
Change-Id: I58674d1c3c5fe4535c022020674d48d6a5315bf9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
1. According to the Maxim's comment and schematic diagram of proto, Modify I2C slave address to 0x38, 0x3c.
2. According to the schematic diagram of proto, Change GPD11 to NC.
BUG=b:191811888, b:1191213263
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Ibf8adf2ed8dda9ae6da06e7e995bef9395cdee35
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57059
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Touchscreen will be no function with R93-14092.19.0 image or be later.
It just happened to work because elants_i2c driver would bind
to the device first based on "ELAN0001" HID ID
BUG=b:195994810
TEST= verify only update RW FW can fix touchscreen no function issue
1.Build test firmware
2.prepare DUT enviroment (R93 image + update RW to test firmware)
3.verify touchscreen function normally
Signed-off-by: FrankChu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Ie9e0fe726854d0128ad1bb430544640dc8f034ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Primus has MX98360A, which Linux kernel 5.10 currently does not support
and, therefore, audio does not work. As the device is compatible with
the MX98357A, use that until Linux’ SoF driver supports the new version
(https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/3070268).
BUG=b:194749863
BRANCH=none
TEST=build coreboot and audio function works
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I893d9a31dc2c7726599c150be01b9585fb6c8a47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Commit e7f3e6a055 added PL4 limits for brya0, but the units were mW,
whereas the `tdp_pl4` field is expected to be in whole Watts, therefore
divide all of the settings by 1000.
BUG=b:197468828
TEST=boot brya0 to OS
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I6da6bae4eb8c83188d813828cdc4f7c1e20f1b5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
This patch enabled the SaGv support for brya0 baseboard.
BUG=b:187446498
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I2a71e159fa49f677660af8279f2b582a3916eee2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add the support RAM parts for felwinter.
Here is the ram part number list:
DRAM Part Name ID to assign
K4U6E3S4AA-MGCR 0 (0000)
K4UBE3D4AA-MGCR 1 (0001)
H9HCNNNBKMMLXR-NEE 0 (0000)
MT53E1G32D2NP-046 WT:A 2 (0010)
BUG=b:197308861
BRANCH=None
TEST=emerge-brya coreboot
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I76febefc251b02a047819242e23c02dc50891c2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Prepare to confine all `pei_data` references in raminit.c and refcode.c
so that mainboards don't need to know about its existence.
Change-Id: I55793fa274f8100643855466b6cca486896fb2c4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55801
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Do early ME init before adding the "start of raminit" timestamp.
Change-Id: If8b27a9d4eb3b801e3e05dc2f2b95bf748985707
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55800
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on the base TGL devicetree, add one specific to TGL-H that adds
the additional supported devices.
Introduces a new Kconfig for selecting the PCH support.
Reference:
- Intel doc 615985
Change-Id: Icc130461edcecc4a3e1f6544ccb905608881d2f7
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Convert the power limit defines to an enum and add TGL-H entries.
Change-Id: I6fa7c7338b3157b29ff72769238597e3c528aedb
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This reverts commit 34bd6ba979.
Reason for revert: Device NVS is expected by mainboard samus
in payload depthcharge:
932c6ba270/src/board/samus/board.c (60)
Not reverted:
* ACPI_HAS_DEVICE_NVS does not exist anymore in ToT and hence it's
selection in broadwell is not required.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ic31d7ae62c5df72708b724160e96e10b46002eb1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Create the moonbuggy variant of the puff reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=191356135
BRANCH=None
TEST=util/abuild/abuild -p none -t google/hatch -x -a
make sure the build includes GOOGLE_MOONBUGGY
Signed-off-by: Rehan Ghori <rehang@google.com>
Change-Id: Iaf545dcd5ff537afdf029f510553d16a1239763e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
gooey is the same design as boten, and differs only in replacing Cr50
with discrete TPM.
BUG=b:193366710, 197247706
TEST=FW_NAME=gooey emerge-keeby coreboot
Signed-off-by: stanley.wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I2a54f872a7d5c0bee76a9e6e309613d9357b380b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Move bcd2bin() / bin2bcd() functions to commonlib/bsd/include/
Also, the license is changed from GPL to BSD.
This is because it is needed from "utils" (see CL in the chain).
For reference bin2bcd() & bcd2bin() are very simple functions.
There are already BSD implementations, like these ones (just to
name a few):
https://chromium.googlesource.com/chromiumos/platform/mosys/+/refs/heads/main/include/lib/math.h#67http://web.mit.edu/freebsd/head/sys/contrib/octeon-sdk/cvmx-cn3010-evb-hs5.c
BUG=b:172210863
TEST=make (everything compiled Ok).
Change-Id: If2eba82da35838799bcbcf38303de6bd53f7eb72
Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56904
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change enables L1.1 and L1.2 on all real Guybrush PCIe devices.
BUG=b:188123142
TEST=Boot to ChromeOS and verify L1SS are functional by dumping the
settings with "lspci -vv". Leave system on for 20 minutes and no hang.
Also perform 20 reboots and suspend operations
Cq-Depend: chrome-internal:4012927
Change-Id: I40d19be78bfcb9a30fb59f48530a4413dadbefbc
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Override GPIO pad configurations based on the latest bugzzy schematics.
BUG=b:192521391
BRANCH=None
TEST=Built test coreboot image and boot on bugzzy board
Change-Id: I7c3580e7eb34efed0441ead243343d2d7875d50f
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
To reduce suspend power consumption,
1. Disable unused CLKSQ2.
2. Set CLKSQ_EN to sleep control for SPM 26M sleep control.
No bus clock when enter 26m sleep control, and only control
clock square by side band.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Change-Id: Ia9a1735d6f508ce35b9af2d67831a3474255198b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57043
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
IDS (Integrated Debug Services) options are meant to be enabled when one
wants to debug AGESA. Since they are compile-time options, using Kconfig
is the logical choice. Currently, none of the options builds.
Tested with BUILD_TIMELESS=1 without adding the configuration options
into the binary, and Asus A88XM-E does not change.
Change-Id: I465627c19c9856e58ca94aa0efedbddb6baaf3f6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
The `ASSERT` macro is already defined in `src/include/assert.h`, and
AGESA's definition is never used. On Asus A88XM-E, toggling the value of
the `IDSOPT_ASSERT_ENABLED` macro does not change the resulting binary
when using reproducible builds. Attempting to use AGESA's definition of
the `ASSERT` macro results in build errors:
In file included from src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuDmi.c:56:
src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuDmi.c: In function 'GetType4Type7Info':
src/vendorcode/amd/agesa/f15tn/Include/Ids.h:371:33: error: statement with no effect [-Werror=unused-value]
#define ASSERT(conditional) ((conditional) ? 0 : IdsAssert (STOP_CODE));
Given that coreboot's definition of `ASSERT` is more useful, drop
AGESA's broken definition and the useless `IDSOPT_ASSERT_ENABLED` macro.
Also remove the `IdsAssert` function, as it is no longer used anywhere.
Tested with BUILD_TIMELESS=1, Asus A88XM-E remains identical.
Change-Id: Ia4e5dbfd3d2e5cec979b8b16fbc11d1ca8a0661e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
In preparation to replace OptionsIds.h with Kconfig options, use the
same settings on all AGESA f15tn boards. The only difference this makes
is that the `IDS_LATE_RUN_AP_TASK` macro no longer expands to nothing.
It is expected that the impact this difference makes is minimal.
Note that the `IDSOPT_TRACING_ENABLED` option currently fails to build.
Tested on asus/f2a85-m, still boots.
Change-Id: Iedd4d1f255650012f3efd9a27718e18c1c904dc1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53982
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch changes the sc7180 boards to use the new common MIPI panel
framework, which allows more flexible initialization command packing and
sharing panel definitions between boards. (I'm taking the lane count
control back out again for now, since it seems we only ever want 4 for
now anyway, and if we ever have a need for a different lane count it's
not clear whether that should be a property of the board or the panel or
both. Better to leave that decision until we have a real use case.)
Also, the code was not written to deal with DCS commands that were not a
length divisible by 4 (it would read over the end of the command
buffer). The corresponding kernel driver seems to pad the command with
0xff instead, let's do the same here. (Also increase the maximum allowed
command length to 256 bytes, as per Qualcomm's recommendation.)
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I78f6efbaa9da88a3574d5c6a51061e308412340e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56966
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add ALC1019_NAU88L25B DB support.
BUG=b:195891240
TEST=audio is functional when playing youtube.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I9209c4cab00fc03b2a6107b5c32804786cd2e242
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Felix Held