Commit Graph

49969 Commits

Author SHA1 Message Date
Martin Roth 815c3634e3 util/scripts: Add script to run abuild on specific SOCs
This finds all the boards using a specified Kconfig option and runs both
CrOS and non-CrOS abuilds on them to make sure they're working.

Nobody wants to run the full what-jenkins-does build on their host
machine.  Hopefully this can help get some tests run locally before
pushing to coreboot.org.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ifc71c28bf64a805f203a815a9468ff9fe882aad3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-11-10 00:19:55 +00:00
Arthur Heymans f158c9c961 cpu/x86/lapic.h: Fix CONFIG_X2APIC_RUNTIME
The deadlock prevention is also needed with CONFIG_X2APIC_RUNTIME when
the cpu is in x2apic mode.

TESTED: Fixes SMI generation on xeon_sp hardware with
CONFIG_X2APIC_RUNTIME.

Change-Id: I6a71204fcff35e11613fc8363ce061b348e73496
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-10 00:19:03 +00:00
Robert Zieba a23aa1ca90 device/xhci: Factor out `struct xhci_usb_info`
This commit factors out `struct xhci_usb_info` from intel specific code
as it will be useful on other platforms.

BUG=b:186792595
TEST=Builds for volteer

Change-Id: I5b4cc6268f072c6948f11c7498a564d7a5c0a190
Signed-off-by: Robert Zieba <robertzieba@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-11-09 23:58:03 +00:00
Robert Zieba 4428195692 device/xhci: Factor out common PORTSC code
This commit factors out some code for XHCI port status values.

BUG=b:186792595
TEST=Built coreboot for volteer device

Change-Id: I045405ed224aa8f48f6f628b7d49ec6bafb450d7
Signed-off-by: Robert Zieba <robertzieba@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-09 23:57:49 +00:00
EricKY Cheng 065c5870e4 ec/google/chromec: Expand EC share memory for DTTS
DTTS is Dynamic Thermal Table Switching Proposal.
DTTS needs one bit to save the body detection result from EC.
Define mode change STTB bit for Desktop (1) and laptop (0).
This bit is Switch thermal table by body detection status.

BUG=b:232946420
TEST=emerge-skyrim coreboot

Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: I37b3a0d8f6546361c8d5501e98e3e1b0d814fce3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68077
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-09 22:35:27 +00:00
Kyösti Mälkki 7b73e85283 Revert "mb/aopen/dxplplusu: Remove board"
This reverts commit eb76a455cd
and applies minor fixes to make it build again.

PARALLEL_MP was working prior to board removal and no
relevant SMI handlers were implemented. So NO_SMM choice
is now selected.

Change-Id: Ia1cd02278240d1b5d006fb2a7730d3d86390f85b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-09 18:10:54 +00:00
Arthur Heymans c8a20b9d3b cpu/*: Drop PARALLEL_MP leftovers
These symbols and codepaths are unused now so drop them.

Change-Id: I7c46c36390f116f8f8920c06e539075e60c7118c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69361
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-09 18:05:55 +00:00
Felix Held 753827ef33 soc/amd/picasso/acpi: include pci_int_defs.asl from soc.asl
Instead of including pci_int_defs.asl in each board's DSDT, include it
in the common soc.asl. This moves the PRQM OperationRegion and the PRQI
IndexField defined in pci_int_defs.asl into the \_SB scope, but those
are defined inside the \_SB scope both in the Picasso reference code and
for the AMD SoCs from Cezanne on.

TEST=Both Linux and Windows still boot and don't show ACPI errors on
Mandolin after moving this inside the \_SB scope

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib4e7bfb15de184cc43cd17c8249be0f59405793f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
2022-11-09 15:47:31 +00:00
Felix Held d92bb3c3f1 soc/amd/picasso/acpi: rename pcie.asl to pci_int_defs.asl
This aligns Picasso more with the newer AMD SoCs and also makes it a bit
clearer what this file does. Also remove the unneeded tabs at the
beginning of each line.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie6e5ee815e4346004bc864a6111a255dc689eae8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
2022-11-09 15:47:04 +00:00
Arthur Heymans 600fa266bd nb/intel/haswell: Hook up PCI domain and CPU cluster ops to devicetree
Change-Id: I955274bc6bda587201f130762c0735c36f5501d1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69289
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-09 14:30:12 +00:00
Arthur Heymans 58955be0aa soc/intel/common/xhci: Fix building for 64bit
Tested with clang on prodrive/hermes: Boots to payload

Change-Id: I66392bcb4ed94c97dde43342dd29dab15d1dd9ea
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69234
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-09 14:27:44 +00:00
Arthur Heymans e0fc3da747 mb/intel/harcuvar: Fix strict prototype warning
Clang warns on both the declaration and the definction.

Change-Id: I94d979fcdbe41349c59248656066615bffd215b6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-09 14:27:08 +00:00
Arthur Heymans 2a86ef5bb8 superio/nuvoton/nct6687d: Fix unexpected expression
Expression after a case statement are not allowed.

This fixes building with clang.

Change-Id: Ie369454f10b515aa5601a5e78330e12f4b7a5e4c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-09 14:26:03 +00:00
Arthur Heymans 2dc59e6e08 mb/prodrive/hermes: Fix format mismatch
Change-Id: I2a6947c1a39b115a7c7f5da1c9becfd51f45fad9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69239
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-09 14:25:27 +00:00
Arthur Heymans f874fc2717 cpu/x86/smm/module_loader: Fix ASEG loading
This code was never tested with SSE enabled. Now qemu enables it and
FX_SAVE encroaches on the save states. Without SSE enabled the handler
just happened to be aligned downwards enough to have the save states
fit. With SSE enabled that's not the case. The proper fix is to give the
code setting up stubs the right base address, which is the same as for
the TSEG codepath.

Change-Id: I45355efb274c6ddd09a6fb57743d2f6a5b53d209
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69233
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-11-09 14:25:03 +00:00
Werner Zeh cc7634fd69 mb/siemens/mc_ehl2: Provide I2C timing parameter for SSDT
Provide timing parameter for SSDT generation to achieve the requested
100 kHz speed with a high accuracy.

Test: Measure I2C bus clock, high and low times during I2C access from
Linux and confirm they match the specification.

Change-Id: Ifb6019421b612133b8f25c076519bc0e7200dad8
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-09 14:20:09 +00:00
Werner Zeh eda13db4e9 mb/siemens/mc_ehl2: Add dummy I2C devices to limit the I2C speed in OS
In Linux, the I2C speed defaults to 400 kHz if there is no device
registered in ACPI which requests a different speed. Due to board
limitations (layout, bus load), 400 kHz are too fast which results in a
timing violation. Therefore, add a dummy I2C device to both used I2C
buses (I2C1 and I2C2) with a speed of 100 kHz. This will limit the bus
speed in Linux accordingly.

Change-Id: I507c53c9ec7f763cef18903609231b1a66ed98fa
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2022-11-09 14:19:40 +00:00
Werner Zeh 14612f698c soc/intel/elkhartlake: Correct I2C base clock to 100 MHz
According to measurements Elkhart Lake seems to drive the internal I2C
controllers with 100 MHz instead of the common 133 MHz. The datasheet
itself is quite vague on this definition, just one place mentions that
it is 100 MHz (register description for offset 0x94).

This patch changes the I2C controller base frequency to 100 MHz. The
verification was done by measuring the set up resulting I2C clock for
both 100 and 400 kHz.

Change-Id: I7c826bbb01b53e3661746e49f25441565068d1c2
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-09 14:19:15 +00:00
Werner Zeh 6b4a1ab82a drivers/i2c/designware: Add 100 MHz controller base clock
There are SoCs (for instance Intel Elkhart Lake) that do use 100 MHz as
the base clock for I2C controllers. To support them properly add a
frequency setting for 100 MHz to the designware I2C controller driver.

Change-Id: I9ea11c6a41fd3758b771a416251e108cbe722769
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2022-11-09 14:18:56 +00:00
Tyler Wang 8ec4024ab8 mb/google/nissa/var/craask: Add wifi sar table
Add wifi sar table for craask/craaskbowl.
Use fw_config to separate different project settings.

BUG=b:247652032,b:251287099,b:251287101
Test=emerge-nissa coreboot

Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I5c92f0ab53ece12a97068f09241e5298909116aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-09 14:18:01 +00:00
Karthikeyan Ramasubramanian 5717ce6e99 soc/amd/common/block/spi: Mainboard to override SPI Read Mode
On certain mainboards due to hardware design limitations, certain SPI
Read Modes eg. (Dual I/O 1-2-2) cannot be supported. Add ability to
override SPI read modes in boards which do not have hardware
limitations. Currently there is an API to override SPI fast speeds.
Update this API for mainboards to override SPI read mode as well.

BUG=b:225213679
TEST=Build and boot to OS in Skyrim. Observe a boot time improvement of
~25 ms with 100 MHz SPI speeds.
Before:
  11:start of bootblock                                688,046
  14:finished loading romstage                         30,865
  16:FSP-M finished LZMA decompress (ignore for x86)   91,049
Total Time: 1,972,625

After:
  11:start of bootblock                                667,642
  14:finished loading romstage                         29,798
  16:FSP-M finished LZMA decompress (ignore for x86)   87,743
Total Time: 1,943,924

Change-Id: I160b56f6201a798ce59e977ca40301e23ab63805
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-11-09 13:40:02 +00:00
Ian Feng d08deaabe1 mb/google/nissa/var/xivu: Add Hynix new memory support
Add new ram_id:0 (0000) for memory part H9JCNNNCP3MLYR-N6E.

DRAM Part Name                 ID to assign
H9JCNNNCP3MLYR-N6E             0 (0000)

BUG=b:257867226
TEST=Use part_id_gen to generate related settings and
emerge-nissa coreboot

Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: If663afbcd2e0457636f4a1c7475f1e3e40f0dd96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-11-09 07:56:03 +00:00
Victor Ding 20265b09dc drivers/i2c/sx9324: Add support for Linux's SX9324 driver
SX9324 driver is updated per Linux's documentation found at
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/iio/proximity/semtech,sx9324.yaml

Supporting logic for the deprecated SX932x driver is hence guarded by
DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER

This patch by itself does not introduce functional changes to any board.
The legacy SX932x Linux driver never reached upstream Linux and is only
available in ChromeOS kernel fork of 4.4 and 5.4. Linux later accepted
a different implementation named SX9324 and has been available since
5.4. Ideally all variants should adopt the new driver; however, during
the transition phase, coreboot must support both drivers. It is better
to have a single firmware build that can work with both Linux kernel
drivers by specifying both sets of properties. Legacy driver support
should be deleted once all variants finish migration.

BUG=b:242662878
TEST=Dump ACPI SSDT then verify _DSD entries related to the legacy
     SX932x driver are identical w/ and w/o this patch
     (Tested on Craask and Nivviks)

Change-Id: I42cd6841c3a270c242ed2e739db245e858eadb3b
Signed-off-by: Victor Ding <victording@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69192
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-09 07:51:57 +00:00
Eran Mitrani b4d71e1ab2 mb/google/rex: Add fingerprint SPI
Add Fingerprint SPI, and power-off FPMCU during romstage.
For reference see CL:66915 for a similar change to Brya's power sequence
SHA: 2b523ce631 ("Invoke power cycle of
FPMCU on startup")

TEST=Tested on Rex - setup and logged in using fingerprint

Change-Id: I4e6be24e72a8232ae2c958a01cf8ea9a272d7365
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66992
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-09 03:36:14 +00:00
Shaik Shahina 425413c35f cbfstool: Fix possible memory leak
Handle the possible memory leak scenario.

Foundby=klocwork
BUG=NONE
TEST=Boot to OS on Nivviks

Change-Id: I01c4643d1e671d9bd9971ac6db8031634fffd61e
Signed-off-by: Shaik Shahina <shahina.shaik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69220
Reviewed-by: Shahina Shaik <shahina.shaik@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-11-09 00:26:30 +00:00
Jonathan Zhang 5c1dcd57ee drivers/ipmi/ocp: add functions to get board configuration
These functions are added for ramstage:
* add IPMI OEM command to get board configuration.
* add function to get blade index in the sled.

Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com>
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Change-Id: I85ec7ba68d580c13e368e7d656dba47ea043d33e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68779
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-09 00:25:33 +00:00
Jonathan Zhang 830fec3fbb drivers/ipmi/ocp: add PCIe SEL support
Add Kconfig SOC_RAS_BMS_SEL and corresponding support for
generating PCIe error SEL records and sending them to BMC.

Add PCIe error definitions.

This is needed for SMM, so build the ipmi kcs driver in SMM.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Signed-off-by: Rocky Phagura <rphagura@fb.com>
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Change-Id: I1ee46c8da7dbccbe1e2cc00bfe62e5df2f072d65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68758
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-09 00:19:17 +00:00
Jakub Czapiga 967a76bd81 vboot: Add VBOOT_CBFS_INTEGRATION support
This patch introduces support signing and verification of firmware
slots using CBFS metadata hash verification method for faster initial
verification. To have complete verification, CBFS_VERIFICATION should
also be enabled, as metadata hash covers only files metadata, not their
contents.

This patch also adapts mainboards and SoCs to new vboot reset
requirements.

TEST=Google Volteer/Voxel boots with VBOOT_CBFS_INTEGRATION enabled

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I40ae01c477c4e4f7a1c90e4026a8a868ae64b5ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66909
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-08 23:03:49 +00:00
Jonathan Zhang fe17a7d4d4 soc/intel/xeon_sp: accomodate xeon_sp FSPX_CONFIG definitions
Intel FSPs of XEON server platforms define FSPX_CONFIG
instead of FSP_X_CONFIG, which is expected by coreboot.

Re-define in the common code.

Update coreboot code to use FSP_X_CONFIG consistently.

Tested=On OCP Delta Lake, boot up OS successfully.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>

Change-Id: Ifa0e1efa1618fbec84f1e1f23d9e49f3b1057b32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-08 22:55:20 +00:00
Solomon Alan-Dei a2503fa2e9 util/cbfstool/bpdt_formats: Fix memory leak issues
The functions create_bpdt_hdr and create_cse_layout
in bpdt_1_6.c are defined to return pointers but
not integers as was previouly implemented.

Reported-by: Coverity(CID:1469323)
Reported-by: Coverity(CID:1469353)

Signed-off-by: Solomon Alan-Dei <alandei.solomon@gmail.com>
Change-Id: Idb78d94be7a75a25ad954f062e9e52b1f0b921dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-08 22:51:36 +00:00
Martin Roth 37ccb2ce82 arch/x86 & commonlib: Add macros for postcodes used in x86/tables
The 0x9a, 0x9b, and 0x9c postcodes are not used anywhere else in the
coreboot tree other than in arch/x86/tables.c.  Add macros to
standardize these postcodes.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I16be65ffa3f0b253fe4a9bb7bfb97597a760ad3f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-11-08 14:51:02 +00:00
Jakub Czapiga 605f793af8 vboot: Introduce handy vboot reboot functions
This patch groups vboot context, recovery reason and subcode saving, and
reboot calls into two handy functions:
- vboot_save_and_reboot() - save context and reboot
- vboot_fail_and_reboot() - store recovery reason and call function
  above

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Ie29410e8985e7cf19bd8d4cccc393b050ca1f1c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69208
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-11-08 14:44:54 +00:00
Elyes Haouas 699b833bd7 /: Remove unused <inttypes.h>
Change-Id: I16aa756039973e164c887ff5237bda69d042a235
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-08 14:43:00 +00:00
Elyes HAOUAS 8fe9e541ad soc/ti/am335x/cbmem.c: Use MiB macro
Use "* MiB" instead of "<< 20".

Change-Id: Iab6592804961a34fae6dc8012bfbc70023421a49
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-08 14:39:29 +00:00
Elyes Haouas ad65e8c041 cpu: Include <cpu/cpu.h> instead of <arch/cpu.h>
Also sort includes.

Change-Id: Ia4a3807e45777e2a596878fe09e3c80b1fd2704d
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-08 14:38:28 +00:00
Ravi Sarawadi df1aea1f2a soc/intel/meteorlake: Remove PM Energy Report WA
Disable Pch PM Energy Report WA was added to enhance boot time
with HFPGA only. SoC needs reporting enabled.

BUG=None
TEST=Build and Boot Google, Rex and Intel, MTLRVP without any boot time regression..

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: If5f1f9c6ab31652977d436a49a3531edffbd60c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69042
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-11-08 14:13:17 +00:00
Ricky Chang feab4a4dff mb/google/brask: Disable PCH USB2 phy power gating for brask
The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for moli board. Please refer Intel doc#723158 for
more information.

BUG=b:257415959
TEST=Verify the build for brask board

Change-Id: I518e90e9032e8f2186300b6b907cc9d84a1682e4
Signed-off-by: Ricky Chang <rickytlchang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-08 14:12:47 +00:00
Subrata Banik c8b9608154 soc/intel: Use `PWRMBASE` over static `Index 0` for PMC
This patch replaces static index 0 for PMC read resources with PCI
configuration offset 0x10 (PWRMBASE).

TEST=Able to build and boot Google, Rex to OS.

Without this change:
[SPEW ]     PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran
0 limit 0 flags f0000200 index 0

With this change:
[SPEW ]     PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran
0 limit 0 flags f0000200 index 10

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iee2523876a8045e70effd5824afc327d1113038b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-11-08 14:12:27 +00:00
Tyler Wang c3d5b9d74f mb/google/nissa/var/craask: Add ambient thermal sensor settings
BUG=b:239495499
TEST=emerge-nissa coreboot

Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I026a8b3e1a27bedc3e0082e15e80a74a2f8adfda
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69197
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
2022-11-08 14:11:06 +00:00
David Wu 4a7a0e9979 mb/google/brya/var/kano: Add mipi hi556 camera support
This patch supports multiple camera modules based on FW_CONFIG.

BUG=b:251235140
TEST=Test the changes with ov2740/hi556 camera.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I34dbf67634ecd364c40c6e934217af3d8efe1689
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jim Lai <jim.lai@intel.com>
Reviewed-by: Ricardo Ribalda <ribalda@google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-11-08 14:10:31 +00:00
Dtrain Hsu f5ead3f029 mb/google/brya/var/kinox: Disable PCH USB2 phy power gating
The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for kinox board. Please refer Intel doc#723158 for more
information.

BUG=b:257373738
TEST=Verify the build for kinox board

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ifcf4f89ea4c61ec4f9a31edba069d2111ca06010
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-08 14:09:44 +00:00
Kevin Chiu 9429844f81 mb/google/brya/var/lisbon: Disable thunderbolt ports
Lisbon doesn't support thunderbolt.

BUG=b:246657849
TEST=FW_NAME=lisbon emerge-brask coreboot

Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: Iac44315d000c3c0c572efb00e877d039e0308455
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68916
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-08 00:27:58 +00:00
Jamie Ryu 4d23b9f18b mb/intel/mtlrvp: Enable ACPI and add ACPI table
This enables ACPI configuration and add ACPI table.

BUG=b:224325352
TEST=util/abuild/abuild -p none -t intel/mtlrvp -a -c max

Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: I8264197fd0acdd7e19b9a36fb22822447b013202
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66100
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-08 00:26:17 +00:00
Ravi Mistry d92745bb98 util/superiotool/fintek.c: Fix F71808A hardware monitor readouts
Fix readouts from the hardware monitor on Fintek F71808A Super I/O.
The HWM port is +5 to the base address stored in LDN 0x4 at index 0x60/0x61.

Referred to util/superiotool/winbond.c and the Linux kernel driver f71882fg.

Tested on a HP 500-319na (Memphis-S / IPM87-MP).

Signed-off-by: Ravi Mistry <rvstry@protonmail.com>
Change-Id: I2b2b98c62f9305c6f4885c2ce3b1444801dcb9d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07 23:20:08 +00:00
Selma Bensaid 67ce1f251a vendorcode/intel/fsp: Add Raptor Lake FSP headers for FSP RPL.3361.07
The headers added are generated as per FSP v3361.07

In the future, when Alder Lake and Raptor Lake fsp align, Raptor Lake
fsp headers can be deleted and Raptor Lake soc will also use headers
from alderlake/ folder.

BUG=b:254054169
BRANCH=firmware-brya-14505.B
TEST=Boot to OS

Signed-off-by: Selma Bensaid <selma.bensaid@intel.com>
Change-Id: If486867477c88ad3e2ec5041ef94a0c364f5dfd6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-11-07 20:45:00 +00:00
Sudheer Kumar Amrabadi 9620ddc8f2 soc/qualcomm/sc7280: Move AOP load and reset handle to Romstage
As AOP takes 500 msec delay to get up, moving aop load and reset to
romstage improves the performance.

BUG=b:218406702
TEST=reboot from AP console (on CRD3)
     prior to fix (from cbmem dump):
         1000:depthcharge start 1,139,809 (152,679)
     after fix (from cbmem dump):
         1000:depthcharge start 1,041,109 (46,353)

Signed-off-by: Sudheer Kumar Amrabadi <samrabad@codeaurora.org>
Change-Id: Iabc8ee8f6e7b14d237b0aeaae42da8077f9dafc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2022-11-07 18:06:36 +00:00
Karthikeyan Ramasubramanian 06d5b8b7fe soc/amd/mendocino: Enable x86 SHA accelerator
Enable x86 SHA accelerator for use by VBOOT library. This is useful when
CBFS verification verifies the hash of the file being loaded in x86.

BUG=b:227809919
TEST=Build and boot to OS in Skyrim. Observe a boot time improvement of
~10 ms with CBFS verification enabled.

Change-Id: I14efe7be66f28f348330580d2e5733e11603a023
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68954
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-07 14:57:16 +00:00
Karthikeyan Ramasubramanian 4f9853a9a5 security/vboot: Update build rules using x86 SHA extension
Currently build rules allow using x86 SHA extensions for all coreboot
stages when enabled. On some SoCs where verstage can run in non-x86
environment, x86 SHA extension cannot be used. Update build rules
accordingly such that x86 SHA extensions can be used in AMD SoCs. This
is particularly useful when CBFS verificiation is enabled which verifies
the hash of the CBFS file being loaded.

BUG=b:227809919
TEST=Build and boot to OS in Skyrim. Observe that hardware acceleration
is used when a CBFS file is loaded and observe an overall improvement of
10 ms.

Change-Id: I4f388e963eb82990cda41d3880e66ad937334908
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68953
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-11-07 14:57:01 +00:00
Maximilian Brune 2f548e597b drivers/intel/fsp2_0/memory_init.c: clean code
No need to call a function that just instantly returns.
It greatly enhances readability to just check before calling a funtion
and it also removes an extra argument.

Change-Id: I4d57c45ede520160ef615725c023b7e92289a995
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07 14:39:32 +00:00
Jamie Ryu 0e7a52a138 mb/intel/mtlrvp: Add MTL reference mainboard for MTLRVP-P
This adds an initial mainboard code for mtlrvp, Intel Meteorlake
reference platform.

BUG=b:224325352
TEST=util/abuild/abuild -p none -t intel/mtlrvp -a -c max

Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I097db4de9734ff81283cf470aabf3eb23b63aab8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66097
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Balaji Manigandan <balaji.manigandan@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-07 14:36:35 +00:00