Commit Graph

16575 Commits

Author SHA1 Message Date
Patrick Georgi 85bb946362 crossgcc: Use acpica-unix2 over acpica-unix
Apparently acpica-unix is shipped under
"A non-open source license (the 'Intel license')" while acpica-unix2
comes under GPLv2/BSD dual license. (see https://acpica.org/Licensing)

So go with unix2.

Change-Id: I412812187bbf488eb4ad6d7fb8d2840f2f5e06d4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13686
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-13 16:59:59 +01:00
Vladimir Serbinenko bd82d18ee5 sandybridge: Always include MRC if not using native RAM init.
Otherwise the image is simply unusable.

Change-Id: I1e2562ba17279d14dc73b05e4f8fa493e06fbcd2
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13699
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-13 08:25:25 +01:00
Aaron Durbin c370fe37ad soc/intel/apollolake: add assert for pad constraints
Ensure the pads passed into the gpio functions are within
range.

Change-Id: Ic523cbfaf60a46709080347af3a36d6330f9a07c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13694
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-13 01:16:27 +01:00
Aaron Durbin c65b8f128e soc/intel/apollolake: pre-evaluate gpio number values
To allow sharing macros in ASL as well as C the macros can't
have complex expression because the ASL compiler does not
evaluate those expressions. To that end, just pre-calculate
the values. Lastly, add N_OFFSET and utilize it for symmetry.

Change-Id: I546d71008e776b27ce8bcd24d2cbd2ee1b2d8020
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13693
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-13 01:16:00 +01:00
Aaron Durbin ada13ed4cb soc/intel/apollolake: limit bootblock size to 32KiB
The CSE places the bootblock (IBBL in Intel parlance) below 4GiB
at top of the address space. However, it's size is limited to
32KiB. For now, just limit all of bootblock to 32KiB.

Change-Id: I8f84138fb81027eae1712b7af3943942c35cf0ea
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13692
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-13 01:15:51 +01:00
Aaron Durbin 65ac3d862f x86: make bootblock size for C_ENVIRONMENT_BOOTBLOCK configurable
Certain platforms may need to limit their bootblock size to within
a given size because specific constraints. Allow the size to be
provided by the mainboard or chipset by way of the arch Kconfig
being processed after those.

Change-Id: I46cc6315918cde575070fa2d3e2514f28008f575
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13691
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-02-13 01:15:36 +01:00
Vladimir Serbinenko a50478f151 ktqm77: Support native raminit
Change-Id: Ic90d3aa714e5681c5021e2b05275d57dce428de0
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13664
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-02-12 22:18:10 +01:00
Julius Werner a25b5d257d lzma: Port size-checking ulzman() version to coreboot
We've had a second version of ulzma() that would check the input and
output buffer sizes in libpayload for a while now. Since it's generally
never a bad idea to double-check for overruns, let's port it to coreboot
and use it where applicable. (This requires a small fix in the four byte
at a time read optimization we only have in coreboot, since it made the
stream counter hit the end a little earlier than the algorithm liked and
could trigger an assertion.)

BRANCH=None
BUG=None
TEST=Booted Oak, Jerry and Falco.

Change-Id: Id566b31dfa896ea1b991badf5a6ad9d075aef987
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13637
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-12 22:00:55 +01:00
Julius Werner d189987fc9 tegra132/pistachio: Increase romstage size in memlayout.ld
These SoCs have come within a kilobyte of their romstage limit, so let's
expand that a little to make room for future core code contributions.
(In the Tegra case just by copying the layout from Tegra210, because
why not? Keeps things simple.)

BRANCH=None
BUG=None
TEST=Ran abuild with and without --chromeos for Foster, Rush, Ryu, Smaug
and Urara.

Change-Id: If8c1ea81cf9827412c78d67a09d54e7a2dc044ac
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13668
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-12 22:00:08 +01:00
Julius Werner ce8c4bfc71 tegra132/210: Remove memlayout_vboot2.ld
Having two separate memlayouts is an unnecessary complication.
Contributors need to make sure that their code fits into the vboot one
(with smaller stage sizes) either way, and the Tegras have plenty of
SRAM anyway. Let's just make the vboot layout the default (as it was
done on other SoCs) to keep things easier to maintain. The empty SRAM
holes on non-vboot systems where the verstage and work buffer would've
been won't hurt them.

BRANCH=None
BUG=None
TEST=Ran abuild with and without --chromeos on Foster, Rush, Ryu and
Smaug.

Change-Id: If37228facb4de1459cc720dca10bf03e04eb9930
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13667
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-12 21:58:34 +01:00
Julius Werner 8c09377dea timestamp: Remove HAS_PRECBMEM_TIMESTAMP_REGION Kconfig
This patch generalizes the approach previously used for ARM32
TTB_SUBTABLES to "auto-detect" whether a certain region was defined in
memlayout.ld. This allows us to get rid of the explicit Kconfig for the
TIMESTAMP region, reducing configuration redundancy and avoiding
confusion when setting up future boards.

(Removing armv4/bootblock_simple.c because it references this Kconfig
and it is a dead file that I just forgot to remove in CL:12076.)

BRANCH=None
BUG=None
TEST=Booted Oak and confirmed that all pre-RAM timestamps are still
there. Built Nyan and Falco.

Change-Id: I557a4b263018511d17baa4177963130a97ea310a
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13652
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-12 21:54:52 +01:00
Patrick Georgi 4b13c7c61e samsung/*umpy: fix Kconfig formatting
Some spaces crept in where there should be tabs.

Change-Id: Ie70469f5a16e8a2d5933ac632d13551b19761064
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13698
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2016-02-12 19:53:59 +01:00
Patrick Georgi 343ea08388 util/cbfstool: Improve heuristic for cbfs header pointer protection
cbfstool has a routine to deal with old images that may encourage it to
overwrite the master header. That routine is triggered for
"cbfstool add-master-header" prepared images even though these are not
at risk, and - worse - destroys the chain structure (through a negative
file length), so avoid touching such images.

Change-Id: I9d0bbe3e6300b9b9f3e50347737d1850f83ddad8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13672
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-12 19:23:08 +01:00
Vladimir Serbinenko 0a07c5c4a0 lumpy: Support native raminit
Change-Id: Id695fb6e759b90cd91bb9760bb4fe2a459480b21
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13663
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-02-12 19:15:56 +01:00
Vladimir Serbinenko d2990c90fd stumpy: Add native raminit support
Change-Id: Ibbb056ae209a16533757af925c8c833c94803834
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13662
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-02-12 19:15:47 +01:00
Vladimir Serbinenko b2ad8108ab link: Support native raminit
Change-Id: I95173c06d334a340fa2157511a1d69f38877b264
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13665
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-02-12 19:10:04 +01:00
Vladimir Serbinenko cf0e9021da emeraldlake2: Support native raminit.
Change-Id: I808a739c91cb52782db46fd4897b6b913224d93f
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13666
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2016-02-12 19:09:19 +01:00
Patrick Georgi a0f6abcada chromebooks: Define GBB hardware IDs
This makes the test IDs the default, taken from depthcharge
master (board/*/fmap.dts, hwid property).

Change-Id: I25793962ac16f451f204dbba6ede6a64c847cfd5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13634
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2016-02-12 18:09:22 +01:00
Vladimir Serbinenko 421b340993 butterfly: Make configurable MRC vs non-MRC.
Change-Id: I7b1e046d5895750d350dfa851a6f51c3a3a1613f
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13659
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2016-02-12 18:03:49 +01:00
Vladimir Serbinenko f004b6b927 stout: Support native raminit
Change-Id: If64607d40a64ada8cfe4c3ad054be9d6571fc221
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13660
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-02-12 18:03:08 +01:00
Vladimir Serbinenko 144eea0697 Make MRC vs native a config rather than making a separate chipset for it.
Tested by making lenovo x230 configurable despite pretty MRC bugs.

Change-Id: Ia2a123f24334f5cd5f42473b7ce7f3d77c0e65b7
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13658
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-12 17:09:05 +01:00
Martin Roth c37c7c8b1f util/kconfig: Ignore extra symbols in configs instead of failing
When updating an old .config file that has a symbol that has been
removed from the current Kconfig tree, kconfig will generate a warning
and fail to save the updated file.  This is incredibly annoying, and
not the goal when trying to eliminate Kconfig warnings.

Instead of generating a warning, just print a message that it's being
ignored.  This will remove the offending symbol, while allowing the
updated config file to be saved.

Split the change from 1 line to 3 lines to keep it at 80 characters.

Change-Id: I09d5775c9ed14bde80077b51b862a7f41bee098a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13674
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-12 17:03:36 +01:00
Patrick Georgi 5cde0cb0a7 mainboards: Drop remaining references to vboot indexes
Those aren't used anymore.

Change-Id: If7baf2d03c47bcc6f69d63a349bbf9d5e749aeac
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13685
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-12 11:07:56 +01:00
Vladimir Serbinenko 4a84e47211 Fix butterfly usb map.
This was copied from mrc structure despite them having fields in different
order.

Change-Id: If10ffa3316c5fdc538a6fabf2409512bc8c3e676
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13661
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-02-12 09:06:39 +01:00
Stefan Reinauer 0544b31a49 bimgtool: Fix printf warning for off_t
off_t wants to be printed with %zd, not %d.

Change-Id: I3f6e1988bb306f4a7738f1f3ccb2093518e4ceb3
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13655
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-12 04:47:37 +01:00
Stefan Reinauer f0d0d91868 bimgtool: Match CRC code guards
Make sure that the statically defined CRC functions are
enabled by the same conditionals as the code using them.

Change-Id: Ic24e2ed1a80b8e5f6623881b08d86f7b608a206e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13654
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-12 04:47:20 +01:00
Stefan Reinauer 3740d77020 bimgtool: Drop unused targets and variables from Makefile
dep has not been defined (and will hence break the build)
LDFLAGS is not used.

Change-Id: I4f91e1e7a176367aa4e1a1c63a2afc0b3186767e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13653
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-12 04:47:04 +01:00
Vladimir Serbinenko 613d3ad208 Move gpio.h to gpio.c on sandy and ivy.
Change-Id: Ic9d8c2a4e5125eca20eb692ac7ed070fda6cbe32
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13657
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-12 04:22:00 +01:00
Vladimir Serbinenko ffbb3c0b8a Merge sandy/ivybridge romstage flow for MRC and non-MRC.
Change-Id: I11e09804ed1d8a7ae8b8d4502bd18f6be933f9fa
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13656
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-12 04:20:57 +01:00
Aaron Durbin 622eea7e81 arches: lib: add main_decl.h for main() declaration
It is silly to have a single header to declare the main()
symbol, however some of the arches provided it while
lib/bootblock.c relied on the arch headers to declare it. Just
move the declaration into its own header file and utilize it.

Change-Id: I743b4c286956ae047c17fe46241b699feca73628
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13681
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2016-02-11 23:29:08 +01:00
Aaron Durbin 711455f244 arch/{arm64,riscv}: remove jmp_to_elf_entry() declaration
jmp_to_elf_entry() is not defined anywhere. Remove it.

Change-Id: I68f996a735f2ef3dd60cf69f9b72c3f1481cbb55
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13680
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-11 23:28:52 +01:00
Aaron Durbin ae4b854080 lib/prog_loaders.c: remove arch/stages.h include
There's no delcaration used. Remove the include.

Change-Id: I6fa7de6362ca0e92f0d5a7d07f3a224b9f77f709
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13679
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-11 23:12:12 +01:00
Aaron Durbin ae3f3024d9 arch: remove stage_exit()
It's no longer used. Remove it.

Change-Id: Id6f4084ab9d671e94f0eee76bf36fad9a174ef14
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13678
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-11 23:12:06 +01:00
Julius Werner 69d20c45ec timestamp: Bump CBMEM timestamp count, make full use of pre-RAM regions
Since we're reaching the timestamp limit on certain platforms (both for
the pre-RAM cache and the final CBMEM region), this patch increases the
amount of space for both. In the pre-RAM case, it achieves this by
always utilizing the full size of the TIMESTAMP() region allocated in
memlayout.ld, rather than arbitrarily limiting it to some constant.

BRANCH=None
BUG=None
TEST=Booted Oak and confirmed that I can once again see all pre-RAM
timestamps after picking in the LZ4 patch series.

Change-Id: Iabb075a48d8d1e3e1811afeaad5ab47e7846c972
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13651
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-11 22:05:19 +01:00
Andrey Petrov 87fb1a6cdb soc/apollolake: Add early serial driver for BOOTBLOCK_CONSOLE
Early UART driver is for bootblock and romstage. It is supposed to be used
when BOOTBLOCK_CONSOLE is enabled. This also adds few configuration bits
in bootblock requiered for serial to be set up.

Change-Id: I15520d566f107797e68d618885d4379e73d0fa45
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13677
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-11 21:16:45 +01:00
Andrey Petrov 57799dcdd1 soc/apollolake: Add minimal GPIO driver
This adds the minimal functionality needed to configure SoC pads.

Change-Id: I2e2268eee2b8c822b42a48a95604b0fab86c9833
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13676
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2016-02-11 21:10:47 +01:00
Alexandru Gagniuc 86f6a135a1 mainboard/intel: Add skeleton for Apollolake RVP board family
RVP1 board comes with DDR3 SODIMMs and discrete VRs.
RVP2 board uses LPDDR3 and PMIC.

Change-Id: I3e47c157c49ad55ff1ba824672ac2630a64a6037
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13298
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-02-11 21:10:30 +01:00
Alexandru Gagniuc dfc2b31517 soc/apollolake: Add initial cache-as-ram setup for bootblock
This is the minimum setup needed to both get cache-as-ram setup and a
C environment working. On apollolake, we only get 32 KiB of data
loaded into an SRAM that is readonly to the main CPU. Due to this
restriction we have to set CAR and a C environment very early on.

Change-Id: I65c51f972580609d2c1f03dfe2a86bc5d45d1e46
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13301
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-02-11 21:00:07 +01:00
Patrick Georgi 9f428137b7 git modules: rename git submodules to avoid hierarchies
Having a git module named "3rdparty" and another one in
"3rdparty/chrome-ec" led to git failures when the latter was initialized
before the former (because of git being stupid, but then it says so on
the box, right?)

Rename modules so there's no such hierarchy (3rdparty ->
3rdparty/blobs). While at it, also rename the culprit to match the path
name (3rdparty/chrome-ec to 3rdparty/chromeec).

git will resolve this on the next git submodule update invocation (eg.
the next coreboot build).

Change-Id: Ief79074d73abeefff36a47b2e58ac6b1c047e3a7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/13675
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
2016-02-11 20:55:55 +01:00
Patrick Georgi 1509c908aa 3rdparty/chromeec: fix build with paths containing "@"
Move submodule forward to a newer upstream master to fix the build on
paths containing "@", as can happen on jenkins.

Change-Id: Ie74012725c379909d5bf631f9cc9969106ca52b8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13673
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-11 20:52:26 +01:00
Alexandru Gagniuc 0492c8cf26 cpu/x86/tsc: Compile delay_tsc.c for the bootblock as well
This is needed in a follow-on patch to enable udelay() handling on
apollolake, which is a dependency for the console code.

Change-Id: I7da6a060a91b83f3b32c5c5d269c102ce7ae3b8a
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/13302
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-11 19:21:24 +01:00
Ruilin Hao c52d4f5745 util/marvell: Add Marvell doimage utility and dependency in relevant Makefile
- Add the doimage sources in util/marvell
- Add dependency in root makefile
- Add dependency in makefile for armada38x soc

BUG=chrome-os-partner:47462
TEST=emerge-cyclone coreboot
BRANCH=tot

Change-Id: I81b30e0865cbd619a41659c3f2819ad3bafc5f24
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4b2a990150580e0b879a346ed8b71b3765b66bab
Original-Change-Id: I7e89b5e96206fde97ce69c296850122fd6c858f9
Original-Signed-off-by: Kefei Yao <kfyao@marvell.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/318046
Original-Commit-Ready: Kan Yan <kyan@google.com>
Original-Tested-by: Kan Yan <kyan@google.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Kan Yan <kyan@google.com>
Original-Reviewed-by: Yuji Sasaki <sasakiy@chromium.org>
Reviewed-on: https://review.coreboot.org/13137
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-11 14:16:08 +01:00
Andrey Petrov 3bc543a5c3 arch/x86: Change how BOOTBLOCK_CUSTOM is selected by default
Currently x86s select BOOTBLOCK_CUSTOM by default. With this
change BOOTBLOCK_CUSTOM is selected only if C bootblock isn't.

Change-Id: I218f3b4044175b89697790c82c384b0f85a27ade
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13642
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-02-11 06:22:08 +01:00
Andrey Petrov 6a1219cfe0 arch/x86: Allow bootblock code to use CAR_GLOBAL variables
Since cbmem is not initialized in bootblock, CAR_GLOBAL variables
can only be accessed directly similar to verstage.

Change-Id: Ifc705016290807c49dc8c49b581864cac2ad3f80
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13641
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-02-11 06:21:58 +01:00
Andrey Petrov ee9e4ae5bf arch/x86: Reserve space for stack in CAR layout
Some platforms may want to use C code in bootblock so they need
writable memory and CAR can be used for it. This change reserves
memory in CAR that can be used by bootblock and other CAR stages.

Change-Id: I8dec768cf8763dbe235f0ba1339079ebc49cbd9a
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13640
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-02-11 06:21:46 +01:00
Aaron Durbin a02bb653fd cpu/intel/microcode: allow microcode to be loaded in romstage
The previous usage of the intel microcode support supported using
the library under ROMCC and ramstage. Allow for microcode support
to be used in normal C-based romstage as well by:

1. Only using walkcbfs when ROMCC is defined.
2. Only using spinlocks if !__PRE_RAM__

The header file now unconditionally exposes the declarations
of the supporting functions.

Change-Id: I903578bcb4422b4c050903c53b60372b64b79af1
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13611
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-10 18:08:28 +01:00
Martin Roth 5a70d6bdf2 kconfig_lint: update kconfig lint shell scripts
- Add lint-stable script with just error checking
- Enable warnings in addition to errors in non-stable test.
- Use git grep if the code is in a git repo now that exclusions are
working.
- Check for perl, and ask the user to install it if it isn't
available.

Change-Id: Ie60d21f4ef8a61d879f116eb2056eb805b0a55f2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13542
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2016-02-10 17:17:56 +01:00
Martin Roth 9e620eaff4 chromeos/Kconfig: Remove dependency on GBB_HAVE_BMPFV
This symbol is not defined.

Change-Id: I2b0a3fca82d85962fc882f237b70702cab0400db
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/13647
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2016-02-10 16:53:55 +01:00
Martin Roth 59ff3400b0 Kconfig: Move defaults for CBFS_SIZE
We want the question for CBFS size to be next to the rom size in the
mainboard directory, but that doesn't seem to work for how people
want to set the defaults.  Instead of having the list of exceptions
to the size, just set the defaults at the end of kconfig.

- Move the defaults for chipsets not setting HAVE_INTEL_FIRMWARE into
the chipset Kconfigs (gm45, nehalem, sandybridge, x4x)
- Override the default for HAVE_INTEL_FIRMWARE on skylake.
- Move the HAVE_INTEL_FIRMWARE default setting into the firmware
Kconfig file
- Move the location of the default CBFS_SIZE=ROM_SIZE to the end of
the top level kconfig file, while leaving the question where it is.

Test=rebuild Kconfig files before and after the change, verify that
they are how they were intended to be.

Note: the Skylake boards actually changed value, because they were
picking up the 0x100000 from HAVE_INTEL_FIRMWARE instead of the
0x200000 desired.  This was due to the SOC_INTEL_SKYLAKE being after
the HAVE_INTEL_FIRMWARE default.  Affected boards were:
Google chell, glados, & lars and Intel kunimitsu.

Change-Id: I2963a7a7eab037955558d401f5573533674a664f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13645
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-10 16:27:50 +01:00
Ben Gardner a3e4833e5d intel/fsp1_0: Allow the MRC cache to live in a FMAP region
The new option CONFIG_MRC_CACHE_FMAP will cause fastboot_cache.c to
look in the FMAP for a region named "RW_MRC_CACHE" and prevents adding
a CBFS file named "mrc.cache".

Tested on a fsp_baytail-based board.

Change-Id: I248f469c7e3447ac4ec7be32229fbb5584cfd2ed
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/13632
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: York Yang <york.yang@intel.com>
2016-02-10 16:27:12 +01:00