Configure I2C high / low time in the device tree to ensure I2C
CLK runs accurately between 380 kHz and 400 kHz.
Measured I2C frequency just as below after tuning:
touchpad:390kHz
codec:395.8kHz
BUG=b:199481261
BRANCH=dedede
TEST=Build and check after tuning I2C clock is between 380 kHz and 400 kHz
Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com>
Change-Id: Ifadc3d19eb57fe6f67504be154c30df7bc0fee71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
All variants originally had been changed to start with an arrow with
two spaces following it to line up with the platform name. A number
of recent platforms were added only using a single space. This change
updates them all to have two spaces so they line up again.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Iab9e6207fff5a7d2f6d76e5ca33eeaca721a224f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch selects SOC_INTEL_COMMON_BLOCK_TCSS from Alder Lake SoC
Kconfig and drops SOC_INTEL_COMMON_BLOCK_TCSS Kconfig selection from
specific mainboard (brya) to ensure all Alder Lake mainboards can make
use of common TCSS block.
BUG=b:187385592
TEST=Type-C pendrive/Gen-2 SSD detected as Super speed.
Change-Id: I85f6a967eb34ea760418131a9586bfdeb13c9b5d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
copy existing QUP driver from /soc/qualcomm/sc7180 to common folder.
This QUP common driver provide QUP configurations, GPI and SE
firmware loading and initializations.
BUG=b:182963902
TEST=Validated on qualcomm sc7180 and sc7280 development board.
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: I95a0fcf97b3b3a6ed26e62b3084feb4a2369cdc9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
SPI NOR size should match with coreboot ROM size. On QCOM Piglin board SPI
NOR size is 64MB and the default coreboot ROM size is 8MB. So, update the
coreboot ROM size to match with SPI NOR size.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board and checked
basic boot up.
Change-Id: I78f3f402b383bbad303f26c31d3d973c5f20d172
Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Buggzy's panel is oriented with its "right" side facing upwards, therefore
the firmware screens in depthcharge were incorrectly rotated. This patch
changes the orientation of the framebuffer provided by the FSP.
BUG=b:194967458
BRANCH=dedede
Change-Id: I4a5fbfcfc1c362da1bddd23c7d132416db3691c9
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
CB:57324 moved panel orientation from panel_serializable_data to the
responsibility of the mainboard, but in parallel to that patch we landed
support for some new panels on the Trogdor mainboard that should be
pointing LEFT_UP. This patch fixes up the panel orientation for those.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I416b6c8804a88b36f723c4690ed78aff928a0f8d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
Update audio FW config based on the schematic carbine_adl-p_evt_20210901.pdf
BUG=b:199180746
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I4f8ee1a97dd92c7aa0131cd0a77b05f851a26b05
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57529
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on latest schematic (0903) update the GPIO table.
BUG=b:197308586
BRANCH=None
TEST=emerge-brya coreboot
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ie79ba14859f7fa4ea66a0f0d58287f4515d01baf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Some variants may require more complex power sequencing than can be
accomodated with just 2 GPIO tables, therefore introduce one in romstage
as well.
BUG=b:187691798
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I7a63a2ee2cd036b9ae5822be9c87d8a026a54922
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
gimble only uses one WiFi SAR table, contained in a file named wifi_sar_0.hex
BUG=b:189068477
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Ied030b79183cc6f962674260e7a82a7261b317ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57616
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds a new variant called kingoftown.
it's clamshell only, no FPR, eDP panel.
BUG=b:198365759
BRANCH=master
TEST=make
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I648664c50dfad11530a854f574f39264158b44e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
In order to distinguish which mipi panel to use,
it need to read the PANEL_ID, and combine
the PANEL_ID and SKU_ID into a new SKU_ID.
BUG=b:197708579,b:191574572,b:198548221
TEST=PANEL_ID should be set correctly.
BRANCH=none
Change-Id: I018b3f460f9d084d1a3f0dac026f1cd9dde284e2
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This change uses the newly added `SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES`
Kconfig to enable USB4 resources and drops the configuration in
mainboard.
Change-Id: Id0951937cab8bf5432fc902ba7af21f56fe98087
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:
1. K4U6E3S4AA-MGCR (Samsung)
BUG=b:192521391
BRANCH=dedede
TEST=Build and boot bugzzy board
Change-Id: Ic0b02559c671845a73a71bd57cd7237850c76645
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
The ANX7625 display bridge requires customized
hs_da_trail time.
This patch is based on CB:51433 (commit 6482b16,
"mb/google/kukui: fine tune the data lane trail")
BUG=b:198558237
TEST=emerge-asurada coreboot
BRANCH=asurada
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Change-Id: I0eedb8fa6a1b3dfd9619c7cbf755c9c4071a8484
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Add mipi panel support for mrbland
- Setup gpio and modify LCD sequence.
- Use the following panel for mrbland:
AUO B101UAN08.3
BOE TV101WUM-N53
- Use panel_id to distinguish which mipi panel to use.
BUG=b:195516474,b:197300875,b:197300876
BRANCH=none
TEST=emerge-strongbad coreboot
Change-Id: Ib7cd2da429b114bf6bad5af312044a0f01319b46
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57336
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The USB descriptions are flipped. Fix by inverting the USB descriptions
in devicetree.
BUG=None
TEST=Build
BRANCH=None
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I4b33f4de137536c5f3592380da15f6b3a3633bf5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57538
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a short documenting comment to each usb entry in devicetree so it is
clear which function each usb port maps to.
BUG=None
TEST=Build
BRANCH=None
Change-Id: I14cbb6af021bb27c89aa82456722f21aa09617be
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56725
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
FSP-S hides the PMC from the PCI bus when it runs, but there are still
initialization steps coreboot programs for the PMC. Therefore, change
all of the cannonlake mainboards to set the PMC as hidden in the
devicetree, which means the device will be skipped during enumeration,
but device callbacks are still issued as if the device were enabled.
TEST=Ran full patch train on google/dratini, disassembled SSDT and the
PEPD device matches what is in pep.asl. Also verified via dmesg that the
INT33A1 device is still initialized by the kernel.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ib4a20ce9075ce7653388a5d3e281fe774bf89355
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Some bridge chips or panels require DSI signal output
before the DSI receiver is ready to work.
This patch is based on CB:47380 (commit b32e4d6,
"mb/google/kukui: Add panel api after dsi start")
BUG=b:198558237
TEST=emerge-asurada coreboot
BRANCH=asurada
Change-Id: Id72560caee9352f88db2de7269b1472f56ac1bdf
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57485
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ALC5682-VD/ALC5682-VS load different kernel driver by different hid
name. Update hid name depending on the AUDIO_CODEC_SOURCE field of
fw_config. Define SSFC bit 9-11 in coreboot for codec within ec.
ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"
BUG=b:193694180
TEST=ALC5682-VD/ALC5682-VS audio codec can work
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: Ib458cf47909a2d7a65f086c5f30f85a16f78d589
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
According to the schematic diagram of version C14_MB_20210902A_SB,
modify the settings of GPIO and fw_config.
BUG=b:197700276
BRANCH=none
TEST=emerge-brya coreboot
Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I14907faeb631193715b1e0e451e427fb79a68279
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add supported memory parts in mem_parts_used.txt, and generate
SPD id for this part.
MT53E512M32D1NP-046 WT:B
BUG=b:199032134
TEST=emerge-dedede coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: Ic9ccee7c0957119a69ee179854cf13d30db40621
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Setting the usb_phy version and length in the soc code instead of devicetree.
That way the devicetree code does not have to reapeat it for different
AMD Cezanne based systems.
Tested on guybrush by changing phy settings in devicetree and then checking
the usb phy register.
Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Change-Id: I2db49e095672054b9b15042fb003a93b67e3a4c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The AMD Cezanne FSP expects a usb phy config structure ID of 0xd 0x6.
If the ID does not match, the FSP USB will not set up the phy.
Tested on guybrush by changing phy settings in devicetree and then checking
the usb phy register.
Cq-Depend: chrome-internal:4087511
Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Change-Id: I4fdb5af1cbc3c70cc113ef6f0fd9332e1a27f142
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57215
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
To take any effect, a `chip` entry in a devicetree or overridetree
always needs a `device` node.
Change-Id: I158459e28dc8c63df4f1d58b30017868a57e5602
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57466
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set GPIO GPP_A8 as high to enable EN_PP3300_TOUCHSCREEN.
also reduce enable delay time for meet panel power sequence.
BUG=b:197668845
BRANCH=volteer
TEST=FW_NAME=chronicler emerge-volteer coreboot chromeos-bootimage
Verify no corruption is seen on the screen
panel power sequence meet spec
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I9a0c1d0afafb2c446fcb3d18e1a67573218614e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57103
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The eventlog requires RTC to provide correct timestamps, so we have to
turn on the config and add the common drivers.
BUG=b:199003609
TEST=check timestamp in 'mosys eventlog list'
BRANCH=none
Signed-off-by: Chen-Tsung Hsieh <chentsung@chromium.org>
Change-Id: Ia382cd023fcbfdf2c1efeb7b32c0b99feb71effa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Update fw_config.c based on the schematic carbine_adl-p_evt_20210901.pdf
BUG=b:190688567
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I240c0cd777d215e46a0a661aaac63a187311019d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
NVMe needs extra time to run boot process, enable power and deassert reset for NVMe earlier in the boot flow that gimble can successfully boot into OS with non-serial coreboot.
BUG=b:198405404
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Ib76965db2a6cd0c19be4043fec73af297a619c7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57359
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch enables SaGv support for gimble.
BUG=b:198531517
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I29887418827614afb10558c6958c9c5e9667079e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Marx Wang <marx.wang@intel.com>
Roughly half the boards had a "title" comment for the board. This adds
it for the rest of the boards to make everything consistent.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ib941318842136212727f56fc6130381c5c9cd55b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
copy config from guybrush reference board.
remove wwan & speaker amp due to the different solution is
used on nipperkin.
BUG=b:194031783
BRANCH=guybrush
TEST=emerge-guybrush coreboot chromeos-bootimage
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I58a9b8393a965a9c793802d3e660829863b74375
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This change adds a new Kconfig `SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES`
that can be selected by mainboard to reserve hotplug resources for
USB4 at the SoC level. `ADL_ENABLE_USB4_PCIE_RESOURCES` is dropped
from soc/intel/alderlake and instead the newly added Kconfig is now
used. This new Kconfig is added so that the same config can be used
across different platforms. In following changes, this Kconfig is
utilized by TGL as well.
Change-Id: Id7c359a0e255c43c2732f6cbe287bc7da14a46e3
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Configure I2C high / low time in device tree to ensure I2C
CLK runs under I2C_SPEED_FAST (400 kHz).
Measured I2C frequency just as below after tuning:
Touchpad: 386.7kHz
Touchscreen: 387.4kHz
Audio: 385.7kHz
P-sensor: 378.1kHz
BaUG=b:197247706
BRANCH=dedede
TEST=Build and check I2C clock is under 400kHz
Signed-off-by: stanley.wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: Ic5d5660181f36f161ae04cbf5003f6d7ad4bc16f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Add MT53E512M32D1NP-046 WT:B supported memory part in the
mem_parts_used.txt and generate the SPD ID for the part. Manufacturer
is Micron, and the memory part is 1anm Tech, difference to 1xnm Tech
on MT53E512M32D2NP-046.
BUG=b:194223174
BRANCH=dedede
TEST=Build the gooey board.
Change-Id: I7b83126a2bf98bb9d0ca05d397c288e0d99ed781
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57310
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
