Mainboards using Sabrina SoC will be using LP5 memory technology.
Generate the initial set of SPDs for the existing LP5 memory parts.
BUG=b:211510456
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ibb43f26b36460290341c5ffcad1ef5a2ff1647c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
CBFS MCache size was assigned a value of the coreboot tables entry size
instead of the MCache size.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I8a8c3a10c6032121b4c5246d53d2643742968c09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Some PCIe devices have extended capability lists that contain
multiples instances of the same capability. This patch provides a
function similar to pciexp_find_extended_cap that can be used to
search through multiple instances of the same capability by returning
the offset of the next extended capability of the given type following
the passed-in offset. The base functionality of searching for a given
capability from an offset is extracted to a local helper function and
both pciexp_find_extended_cap and pciexp_find_next_extended_cap use
this helper.
Change-Id: Ie68dc26012ba57650484c4f2ff53cc694a5347aa
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This reverts commit ceaf959678.
The AMD Picasso SoC doesn't support x2APIC and neither advertises the
presence of its support via bit 21 in EAX of CPUID leaf 1 nor has the
bit 10 in the APIC base address MSR 0x1b set, but it does have 0xd CPUID
leaves, so just checking for the presence of that CPUID leaf isn't
sufficient to be sure that EDX of the CPUID leaf 0xb will contain a
valid APIC ID.
In the case of Picasso EDX of the CPUID leaf 0xb returns 0 for all cores
which causes coreboot to get stuck somewhere at the end of MP init.
I'm not 100% sure if we should additionally check bit 21 in EAX of CPUID
function 1 is set instead of adding back the is_x2apic_mode check.
TEST=Mandolin with a Picasso SoC boots again.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If1e3c55ce2d048b14c08e06bb79810179a87993d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The headers added are generated as per Alder Lake N FSP v2503_00.
Changes include:
- Add all header files for Alder Lake N FSP.
- List of header files: FirmwareVersionInfoHob.h, FspmUpd.h, FspsUpd.h,
FspUpd.h, MemInfoHob.h
- Select FSP_HEADER_PATH
BUG=b:213828776
BRANCH=None
Change-Id: I97afa6d47cc825703a8dc82216250bfc5e09dc9b
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Variant should honor locked gpios from baseboard, but not the last.
Variant can add more gpios to lock if needed.
BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
volmar boots successfully to kernel.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I36355af771fbf97e655f2fd6e0505c657e0420b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Variant should honor locked gpios from baseboard, but not the last.
Variant can add more gpios to lock if needed.
BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
vell boots successfully to kernel.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I0c39d06e3b2f39db88d924205786bfa1b27df3fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Variant should honor locked gpios from baseboard, but not the last.
Variant can add more gpios to lock if needed.
BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
taniks boots successfully to kernel.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Icf6cb0d057f9ad3cbcc1155423ed7efa58a46d0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Variant should honor locked gpios from baseboard, but not the last.
Variant can add more gpios to lock if needed.
BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
taeko4es boots successfully to kernel.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I82bdf8a1bfe2df0fc1d50d154def8742714321ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Variant should honor locked gpios from baseboard, but not the last.
Variant can add more gpios to lock if needed.
BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
taeko boots successfully to kernel.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ib30815dbe99342b6afd9af9f1aa9ff61c9a4fe80
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Variant should honor locked gpios from baseboard, but not the last.
Variant can add more gpios to lock if needed.
BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
redrix boots successfully to kernel.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ifd69a9c2f1a71aefc19adf6931e10de62d05fb2c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Variant should honor locked gpios from baseboard, but not the last.
Variant can add more gpios to lock if needed.
BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
redrix boots successfully to kernel.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: If08ae5c96232efd03d77090c3c6979c77f95c998
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Variant should honor locked gpios from baseboard, but not the last.
Variant can add more gpios to lock if needed.
BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
primus boots successfully to kernel.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I71f7391df6d827b75f87e54e17f6f7983a9e829b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Variant should honor locked gpios from baseboard, but not the last.
Variant can add more gpios to lock if needed.
BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
primus boots successfully to kernel.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I3133a992617c833fd13df97795c46ec04ebb8bf9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Variant should honor locked gpios from baseboard, but not the last.
Variant can add more gpios to lock if needed.
BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
kano boots successfully to kernel.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I1d8c003b19381e6a76aff8c844546694c5710e53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Variant should honor locked gpios from baseboard, but not the last.
Variant can add more gpios to lock if needed.
BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
gimble boots successfully to kernel.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: If71ceb07a9894a0571a9983d008058598693986f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Variant should honor locked gpios from baseboard, but not the last.
Variant can add more gpios to lock if needed.
BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
gimble boots successfully to kernel.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Idd398d819dcb30a3ec588ce2ef4562a728f99405
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Variant should honor locked gpios from baseboard, but not the last.
Variant can add more gpios to lock if needed.
BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
felwinter boots successfully to kernel.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ic1e0bfc53b74bd5af9ac8d598bb80833499dd997
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Variant should honor locked gpios from baseboard, but not the last.
Variant can add more gpios to lock if needed.
BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage'
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Id5a2136e57e842fbd0b2c2836833106e7344afee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Variant should honor locked gpios from baseboard, but not the last.
Variant can add more gpios to lock if needed.
Also fix the gpio order of GPP_F19.
BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
anahera4es boots successfully to kernel.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I9a73aca1c364dcbc3f3957cd4193d86f399a40bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Variant should honor locked gpios from baseboard, but not the last.
Variant can add more gpios to lock if needed.
Also fix the gpio order of GPP_F19.
BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
anahera boots successfully to kernel.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ie50ba20a10ded184fd880be9ed288b90d346c22b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Variant should honor locked gpios from baseboard, but not the last.
Variant can add more gpios to lock if needed.
BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
agah boots successfully to kernel.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ia9272f704e5656e6d0dc318dd1b51d50fc549839
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add rest of soc sensitive gpios to lock for brask.
BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
brask boots successfully to kernel.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Iad87d13d3df0ad87c075027e3fcc4c75aa711159
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add rest of soc sensitive gpios to lock for brya.
BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
brya0 boots successfully to kernel.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I41393e7a0e8bacb3cc98610f7101dabe66308f94
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add PAD_NC_LOCK and PAD_CFG_GPI_SCI_LOCK macro to support mainboard
to lock NC and GPI_SCI pins as applicable.
BUG=b:216583542
TEST=build passed
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ie44d72f4152b55183d900228df3e3670358f7518
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61655
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The ChromiumOS kernel has the ability to restrict devices to their own
IOMMU security domains when ACPI passes this property to a device
downstream of a PCIe RP.
BUG=b:215424986
TEST=verified the property is found and WWAN is restricted to its own
IOMMU domain as expected.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I1717c0976d1d961772245fd420368fe5a9c1262e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This new chip driver will be used for attaching ACPI properties to PCIe
endpoints. The first property it supports is "UntrustedDevice." This
property can be used by a payload to, e.g., restrict the device to its
own IOMMU domain for security purposes. The new property is added by
adding a _DSD and an integer property set to 1.
Example of the property from google/brya0:
Scope (\_SB.PCI0.RP01)
{
Device (DEV0)
{
Name (_ADR, 0x0000000000000000) // _ADR: Address
Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
Package (0x01)
{
Package (0x02)
{
"UntrustedDevice",
One
}
}
})
}
}
BUG=b:215424986
TEST=boot patch train on google/brya0, dump SSDT, see above for snippet
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I53986614dcbf4d10a6bb4010e131f5ff5a9d25cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Enable USB Port A on daughterboard for Taeko
BUG=b:216533764
TEST=emerge-brya coreboot
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I1a43c256757f3fc4b53ba1f794587d6a00ba0aa5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
On systems that use the first 128kByte of the SPI flash for the EC
firmware, it is not possible to place the EFS/amdfw part at the lowest
location in flash where the on-chip PSP firmware will look for the EFS,
since this is at an offset of 128kByte into the flash which is where the
cbfs master header resides when the main CBFS is placed right after the
EC firmware. This patch introduces the AMD_SOC_SEPARATE_EFS_SECTION
option that allows putting the EFS in a separate FMAP section that can
be located right after the EC firmware FMAP section. The EFS FMAP
partition is checked to ensure it begins at the expected location.
Change-Id: I5ed0f76c9c9c9c180ee5f1b96f88689d0979bb5e
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
ALC5682-VD/ALC5682I-VS load different kernel driver by different hid
name. Update hid name depending on the AUDIO_CODEC_SOURCE field of
fw_config. Define FW_CONFIG bits 41 - 43 (SSFC bits 9 - 11)
for codec selection.
ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"
BUG=b:192535692
BRANCH=volteer
TEST=ALC5682-VD/ALC5682I-VS audio codec can work
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Ia6089441dc1ba04c3f7427dda065b85bd295af0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Mac Chiang <mac.chiang@intel.com>
I think this doesn't do anything on most architectures, but it should
still be there just in case. Found by Coverity.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I845a784d90f65610fd1e0d751ea13e9af5b970fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Post codes don't signify an emergency error, so they shouldn't be
classified as BIOS_EMERG. Now that loglevels are more visible, this
misclassification looks pretty glaring. This patch changes them to
BIOS_INFO which seems more appropriate for an informational code that is
expected to occur in the normal boot flow.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I85c8768232ae0cbf65669a7ee6abd538a3b2d5e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The patch selects USB2_PORT_MAX_TYPE_C macro for usb2 port#2 in
the device tree of Gimble DVT and Gimble EVT. The macro modifies the
USB2 configuration to indicate the port is mapped to Type-C and sets
Max TX and Pre-emp settings.
The change is required to enable port reset event on the USB2 port#2.
This event is passed to USB3 upstream ports to upgrade back to super
speed (USB3) after a downgrade during low power state. The change is
done for Gimble DVT and EVT boards.
BUG=b:193287279
TEST=Built coreboot for Gimble and tested type A pen drive detect as
super speed device on both the Type-C ports.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: If54faa63a983c859bf26a6a779751a6c3c85c43d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61586
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The patch defines USB2_PORT_MAX_TYPE_C macro to allow mark the type_c
flag.The USB2_PORT_MAX_TYPE_C macro modifies the USB2 configuration to
indicate the port mapped to Type-C and sets Max TX and Pre-emp
settings. This is an extension to existing macro USB2_PORT_MAX.
The change is required to enable port reset event on a USB2 port.
This event is passed to USB3 upstream ports to upgrade back to super
speed (USB3) after a downgrade during low power state.
BUG=b:193287279
TEST=Build the code for Gimble board
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I464f139d8e367907191c04f9170ac53d327776ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61623
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
`PLATFORM_IFD2` macro is more generic tag that can be associated with
early next SoC platform development which using IFDv2.
The current assumption is that newer SoC platform still uses the same
SPI/eSPI frequency definition being used for latest platform(TGL, ADL)
and if the frequency definition is updated later, `PLATFORM_IFD2' will
use latest frequency definition for early next SoC development.
And once upstream is allowed for new platform, platform name will be
added in tool later.
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I14a71a58c7d51b9c8b92e013b5637c6b35005f22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch implements `cse_control_global_reset_lock()` as per ME BWG
(doc: 627331) recommendation.
It is recommended that BIOS should set this bit early on in the boot
sequence, and then clear it and set the CF9LOCK bit prior to loading
the OS in both an Intel CSME Enabled and a Intel CSME Disabled system.
Note: For CSE-Lite SKUs BIOS should set CF9LOCK bit unconditionally.
BUG=b:211954778
TEST=Able to build and boot Brya.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3894b2cd8b90dc033f475384486815ab2fadf381
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Nivviks P1 will also use Micron MT62F512M32D2DR-031 WT:B. Add it to the
parts list and regenerate the memory IDs using part_id_gen.
BUG=b:217095281
TEST=abuild -a -x -c max -p none -t google/brya -b nivviks
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: I2b56b0844e70a2712923b197436dd2d668e58a27
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
The implementation of clearing watchdog status is wrong in CB:58835.
The value written to the 'wdt_mode' register should be
'wdt_mode | 0x22000000' instead of 'wdt_status | 0x22000000'.
BUG=b:204229208
TEST=check watchdog status is cleared.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I8c5dbaab2ac43d3867037bc4160aa5af2d79284f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
For most MediaTek SoCs (MT8183, MT8192, MT8195) we rely on an external
program (e.g., the "DRAM blob") to do the full DRAM calibration first,
then store and and apply the generated parameters to the reference
"fast DRAM calibration" in the vendor/mediatek folder for normal system
boot.
Starting with MT8186 the implementation of fast calibration may need
to be changed, and a "DRAM blob" only path is introduced for devices
that have to do both full and fast calibration using the external blob.
TEST=fast calibration pass on kingler/krabby
BUG=b:204226005
Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com>
Change-Id: If25a7dd6aa6261ecff79a1b4df8b1f2e53d896dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Add WiFi SAR table for taeko.
BUG=b:212405459
TEST=build FW and checked SAR table can load by WiFi driver.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I061dc798ae7177d05bc50648cfda46a3eec2c912
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Trackpad GPIO configuration does not align with the IRQ configuration
in the devicetree. Configure the trackpad GPIO to generate SCI on
falling edge.
BUG=None
TEST=Build and boot to OS in Nipperkin. Ensure the trackpad is
functional. Suspend the device and wake it using trackpad. Perform
suspend/resume sequence for 100 iterations.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: If4324e09535d2676c8a8c6643604227eeaba0fe8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
For USB ports, we want to use custom PLD fields with more details to
indicate physical location. Custom PLD will also be added to other brya
variants in the future as we figure out physical port locations on those
devices. Type A port on MLB is removed since it is no longer used.
BUG=b:216490477
TEST=emerge-brya coreboot & SSDT dump in Brya test device
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: Iea975a4f436a204d4edd19fad0f5652fb44c6301
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
ADL and Sabrina have different advisory regarding encoding the bus
width. Encode the bus width as per the respective advisories.
BUG=b:211510456
TEST=Build spd_gen and ensure that the bus width is encoded as expected.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ia12a5bd8f70a70ca8a510ecf00f6268c6904ec25
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Sabrina uses the same MMIO_CONF_BASE MSR as the previous AMD CPUs to
configure the PCI MMCONF base address.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7e3064bab5ca1e277b04f9aae98f9adabce75399
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This will make debugging boot failures with a non-serial firmware
easier. If we encounter an error that requires a reboot, this will dump
the entire CBMEM contents onto the UART. This is especially helpful
during S0i3 resume because the PSP verstage console logs are not
exposed anywhere.
BUG=b:215599230
TEST=Cause verstage error in S0i3 with non-serial firmware and see that
the verstage logs were dumped to the UART before rebooting.
Entering PSP verstage S0i3 resume
tpm_setup failed rv:1
VB2:vb2api_fail() Need recovery, reason: 0x3f / 0xcc
Saving nvdata
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I908037527206cc7bed2302fab60b2912d6dabc73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Karthikeyan Ramasubramanian