This commit adds the following to MA785GM:
Refactor some alignment handling
Unify Local APIC address definitions
ACPI: More ../../.. removal
Remove old AMD fam10 fixme comment
amd/sb700: Move HAVE_HARD_RESET to southbridge
Change-Id: I85a95bb641375dd61d1f58a2f2f972771d1d9ad9
Signed-off-by: Alec Ari <neotheuser@ymail.com>
Reviewed-on: http://review.coreboot.org/922
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
Add early_smbus.c for romstage-y list and remove respective
include on mainboard romstage.c files.
Tested on AOpen board.
Change-Id: I1c7e6cb32e3a9d7cc9b6037dc27e59149d492001
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/909
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch adds coreboot support for the
GIGABYTE MA785GM-US2H board.
This port now removes all dead code in
the previous patch set, and also boots Fedora 16
on x86_64 (Phenom II X4 955 BE)
On-board audio causes spurious interrupts and
the kernel gets stuck in an infinite loop.
AtomBIOS on RadeonHD video cards does not function
and causes another infinite loop. radeon.modeset=0
must be set. acpi=off must also be set.
With those kernel command line options set,
Fedora 16 makes it to the login screen. USB
mouse and keyboard don't work though. several
USB error codes on boot-up. PS/2 should.
Change-Id: I58a7083a023ebf7373b6ded2e9f0adda7ab76dea
Signed-off-by: Alec Ari <neotheuser@ymail.com>
Reviewed-on: http://review.coreboot.org/476
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The Alix6 is very similar to the alix2, differing in having 1 mini-PCIe
slot (USB 2.0 only), an RFKILL GPIO line going to that slot, and 1 or 2
SIM sockets.
Change-Id: I19e4e756966e60bb0310c19286654d3d579b8850
Signed-off-by: Philip Prindeville <philipp@redfish-solutions.com>
Reviewed-on: http://review.coreboot.org/521
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
No longer include northbridge files directly in the source for
mainboard romstage.c and fix includes.
Also make required adjustments to function declarations.
Change-Id: Iafdcc0766ed44c64cc628e5935eef2c6372f5f22
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/906
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
It takes about 3 seconds to scrub 8GiB DDR266 RAM.
After ECC scrub XIP cache is disabled for system stability. There is
very little to do in romstage after ECC scrub, especially when RAM
debug messages are turned off. So the delay caused by this is hardly
noticeable.
Cache for complete ROM is re-enabled before ramstage is decompressed,
and it has no unstability issues. So the code required to re-enable
cache for ROM currently already exists in cache-as-ram_ht.inc.
A Kconfig option HW_SCRUBBER enables the scrub to be run on hard
reboots and power-ons.
Change-Id: Icf27acf73240c06b58091f1229efc0f01cca3f85
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/905
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Hope no more blank issue is got from future copy-paste.
Change-Id: I5eb50e8232e339e7039a15054606aaff6b7ebc52
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/907
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The name of processor created by AGESA is P00n, whose P is
BLDCFG_PROCESSOR_SCOPE_NAME(is 'C' if it is undefined.) and n starts
from 0. The dsdt should be aligned with that.
This feature has only been tested on persimmon. The changes on all the
other boards were propagated.
Change-Id: I8c3fa4b94406d530d2bed8e9a1f42b433bbec3ec
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/884
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
During normal boot, the cbmem is uninitialized. So it is illegal to find
the heap in cbmem.
Change-Id: I8b5e1dbf1124819ed91693a86a6dbe41aea109e5
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/904
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Persimmon is the demo board. Tested by Linux and Windows 7.
Change-Id: I5ded942b51e63ebeb08ace0b202b4ed239b0c14c
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/624
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
HEST feature starts from ACPI 4.0.
HEST is one of four kinds of tables of ACPI Platform Error
Interfaces (APEI). In Windows world, APEI is called Windows Hardware
Error Architecture (WHEA).
APEI consists of four separate tables:
1. Error Record Serialization Table (ERST)
2. BOOT Error Record Table (BERT)
3. Hardware Error Source Table (HEST)
4. Error Injection Table (EINJ)
All these 4 tables have the same header as FADT, MADT, etc. They are
pointed by RSDP.
For the HEST, it contains the error source. The types of them are
defined as
type description
1. Machine Check Exception (MCE)
2. Corrected Machine Check (CMC)
3. NMI Error
6. PCI Express Root Port AER
7. PCI Express Device AER
8. PCI Express Bridge AER
9. Generic Hardware Error Source
Error source types 3, 4, and 5 are reserved for legacy reasons and
must not be used.
Currently AMD board only provide part of "Machine Check
Exception (MCE)" & Corrected Machine Check (CMC)". we need to provide
the header of each error source. Other types of Error Sources is in
TODO list.
Only persimmon is tested. Linux can add HEST feature. The dmesg says,
ACPI: HEST 0000000066fe5010 00198 (v03 CORE COREBOOT 00000000 CORE 00000000)
......
HEST: Table parsing has been initialized.
No more message is got.
Windows can boot with this patch. Havent found a way to test it.
Change-Id: I447e7f57b8e8f0433a145a43d0710910afabf00f
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/888
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
"This file must be in UNIX format" is not valid anymore.
Change-Id: I86169b12e7db159c1d3f380b0434874e9b6f5274
Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Reviewed-on: http://review.coreboot.org/899
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested on real hardware, mainboard with dual Xeon P4 HT CPUs
requires cache-as-ram init code with AP SIPI protocol.
Also enable 2nd CPU and PATA and clean-up Kconfig and ACPI.
Change-Id: I415482f3af22df79d82492c49aed83549f29aa56
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/886
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Some places still hardcoded the address instead of using IO_APIC_ADDR.
Change-Id: I3941c1ff62972ce56a5bc466eab7134f901773d3
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/677
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Fix delay loop comments. Time waited and the comments did not match
in the origin (e7501), so delays currently "just work".
Move reset detection to main raminit and don't use generic
sdram_initialize for now, as there are local debug
functions I need to use. Fix AOpen respectively.
Disable ecc scrub, until I have it fixed for cache-as-ram use.
Change-Id: I0529297f43c565d30b5fb7d1836700278ac029c4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/883
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
It's almost 10 years old. It never worked. It's a soldered in FLASH,
so mistakes are fatal. It's got no redeeming features.
Remove the dell directory. In 12 years of trying to work with Dell
we have not had much interest. It's misleading to have it there.
Change-Id: I83ff009bd7a6d5289229ca39608789ae5c33710b
Reviewed-on: http://review.coreboot.org/876
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
some blank changing is integrated into the previous patches, which hold
the unsplitted diff hunk.
Change-Id: If9e5066927c5e27fee7ac8422dbfbf2cbeac7df5
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/625
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
... and drop duplicate definition in via/epia-n code.
Change-Id: Id79daaaa35c4d412c8c1f621a3638d129681d331
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/820
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Cache was enabled for the last 4 MB below 4 GB when ramstage is
loaded. This does not cover the case of a 8 MB Flash and could
overlap with some system device placed at high memory.
Use the actual device size for the cache region. Mainboard
may override this with Kconfig CACHE_ROM_SIZE if necessary.
Change-Id: I622223b1e2af0b3c1831f3570b74eacfde7189dc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/641
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit adds support for Bifferboard, a 32MB 486 PC
Change-Id: Iad790ebf242ef07bf6298f8e3577783e5e743113
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/810
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This is handy for bifferboard to provide same size as original bootloader.
Change-Id: I179917d8c6354fa55cebdd70918a96cd299c4f3c
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/809
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Also any CPU_AMD_AGESA_FAMILYxx selects CPU_AMD_AGESA, so remove
the explicit selects from the mainboards.
Change-Id: I4d71726bccd446b0f4db4e26448b5c91e406a641
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/792
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Use NORTHBRIDGE_INTEL_I945 to select the driver directory for build.
Use _SUBTYPE_945GC and _SUBTYPE_945GM to define at compile-time
which model of I945 the driver is built for.
Change-Id: I11b1e0998d0fc28f8946bad4f0989036a9b18af4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/684
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Use separate Kconfig option to select a driver directory for
build and the specific type of southbridge to support.
Change-Id: I9482d4ea0f0234b9b7ff38144e45022ab95cf3f3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/685
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit includes the changes to enable the HDMI on Union
Station. The changes switch the output from the display port
to the HDMI.
Change-Id: I4e15ff6db7d056f156791ff1406d4bae35ff2767
Signed-off-by: Frank Vibrans <frank.vibrans@se-eng.com>
Reviewed-on: http://review.coreboot.org/788
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
Because the Union Station platform doesn't have an SIO chip,
this commit removes the Fintek SIO support.
Change-Id: Idba4222ce136821dee2530a72d1630eb5ad613a2
Signed-off-by: Frank Vibrans <frank.vibrans@se-eng.com>
Reviewed-on: http://review.coreboot.org/787
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
Change-Id: I69ee67c35113d98e034bdccf5d00e8452d3d9bd2
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/778
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
We used several names for that same value, and hardcoded the value
at some more places.
They're all LOCAL_APIC_ADDR now (except for lapic specific code
that still uses LAPIC_DEFAULT_BASE).
Change-Id: I1d4be73b1984f22b7e84681edfadf0588a7589b6
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/676
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This is an old (pre-2005) entry-level server mainboard. The code
is adapted from mainboard/intel/xe7501devkit.
Featured chips:
- Dual socket604
- E7505 northbridge
- 82801DB southbridge (with EHCI debug port)
- 82870p2 PCI-X bridge
- LPC47M102S-MC super-io
- 512kB FWH flash (flashrom does the job well)
What works:
- Dual-Xeon P4/HT boot with microcode update
- RAM: registered ECC DDR266 in dual-channel
- PCI-X slot interrupts with ACPI and I/O apic
- On-board PCI-X GbE and SCSI
- ACPI power-off and wakeup with PME#
Notes :
- Current ACPI is more or less a mess
- Interrupts do not route correctly with PIRQ
- MP-table is not implemented
- Issues with reboots remain (cold and warm)
- Many superio devices are disabled by default
- Audio codec is not investigated
Change-Id: I02d18c83f485a09ada65dde03bcc86e9163f2011
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/303
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Board identifiers use them without underscore, too. Unify that.
Change-Id: I146384ef6dbe601ad131dada8224f43e6c18433d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/674
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Southbridge SP5100 support was compiled with SB700 code, but static
device info structure would use sp5100/chip.h. To solve this drop
support for separate chip sp5100 and adjust the relevant Kconfig
options.
Removes chip directory:
src/southbridge/amd/sp5100/
Rename Kconfig option
from: SOUTHBRIDGE_AMD_SP5100
to: SOUTHBRIDGE_AMD_SUBTYPE_SP5100
Change-Id: I873c6ad3624ee69165da6ab7287dfb7e006ee8e8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/679
Tested-by: build bot (Jenkins)
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Thanks to ruik on #coreboot Freenode IRC channel for
explaining to me how to get the cpu revision:
Feb 21 22:07:32 <ruik> ruik@ruik:~/coreboot$ cpuid | grep ^00000001
Feb 21 22:07:32 <ruik> 00000001 00020f32 00020800 00000001 178bfbff
[..]
Feb 21 22:07:44 <ruik> the 20f32 is mine CPUID
The rest was just looking at the correspondance in
src/cpu/amd/model_10xxx/update_microcode.c
like Marc Jones explained(thanks Marc Jones) in the mailing list here:
http://www.coreboot.org/pipermail/coreboot/2012-February/068332.html
Change-Id: Ie0f004990e6b65456de009a4dcc306498bdb47e9
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/669
Reviewed-by: Marc Jones <marcj303@gmail.com>
Tested-by: build bot (Jenkins)
CPP is ran with src/ as part of its search path, so
using <northbridge/...> and the like is safe.
Change-Id: I644d60190ac92ef284d5f0b4acf44f7db3c788ee
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/649
Tested-by: build bot (Jenkins)
No in-tree board using that chipset has it not selected, so move
selection from boards to southbridge.
Change-Id: I16b27e40ca1a201b2f968f8ce303eaafe43804c0
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/660
Tested-by: build bot (Jenkins)
The family10 code had a very slow decompress before the cache settings were
fixed. This has been fixed for some time. Remove all the old messages from the
serial stream.
Change-Id: I476efe1a430f702af394734f354ff69bd053f1d2
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/672
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Fixes the warnings generated in the torpedo mainboard build. Most of these
changes are similar to fixes already implemented in the persimmon mainboard.
Change-Id: Ib931be51c0e6448c00c8cfeb13073e1f392582a5
Signed-off-by: Martin L Roth <martin@se-eng.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/634
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Make changes to MPtable to match the ACPI tables.
Change-Id: Icc18c9a25695d01d88d6ee5367064d527cc42bc1
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/629
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Fix the ACPI IRQ routing. Also, fix the SSDT generations and TOM2 fixup.
Change-Id: Ica4a992d11bab63a510238dcd468b9fe80136def
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/628
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
No in-tree board using that chipset has it not selected, so move
selection from boards to southbridge.
Change-Id: Ibfb7b294aa5007ac2f767d85e090572f85148bad
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/659
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
No in-tree board using that chipset has it not selected, so move
selection from boards to southbridge.
Change-Id: I7a7a1919b7a555156b8da21e8db7dd8f682d68e1
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/661
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
No in-tree board using that chipset has it not selected, so move
selection from boards to southbridge.
Change-Id: Ifba0b65d81af60774f368d151e935ae1cc768336
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/662
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
No in-tree board using that chipset has it not selected, so move
selection from boards to southbridge.
Change-Id: I9762ef01fc10c453ef643599c1c5dc8ee78081c3
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/663
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
No in-tree board using that chipset has it not selected, so move
selection from boards to southbridge.
Change-Id: I83105e92d1cc5d2d12aede564a1ab9c5d912ac56
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/664
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
No in-tree board using that chipset has it not selected, so move
selection from boards to southbridge.
Change-Id: I521deecf58e5d5de303f1ef2f5ff7e965294de18
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/665
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
