Commit Graph

34037 Commits

Author SHA1 Message Date
Julius Werner 50c1f27069 libpayload: xhci: Fix CAPREG address calculation
I rushed CB:40895 in to fix a bug only to introduce another. xhci_init()
no longer crashes, but it doesn't correctly initialize the XHCI
controller either, and unfortunately the error messages are all hidden
behind USB_DEBUG. This patch fixes the incorrect address calculation to
what it was  before CB:39838.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I14293e2135108db30ba6fd2efea0573fe266fa37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-05-02 01:51:22 +00:00
Aaron Durbin 806ea463db soc/amd/picasso: add sd/emmc0 configuration to chip.h
In order to isolate mainboard code from direct FSPS manipulation
allow sd/emmc0 configuration to be supplied by devicetree.cb.

BUG=b:153502861

Change-Id: I2569ccccd638faaf2c9ac68fe582ecb9fa967d9f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2146439
Commit-Queue: Aaron Durbin <adurbin@google.com>
Tested-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-01 23:28:37 +00:00
Marshall Dawson 00a220877c soc/amd/picasso: Add FSP support for including AGESA
AMD has rewritten AGESA (now at v9) for direct inclusion into UEFI
build environments.  Therefore, unlike the previous Arch2008
(a.k.a. v5), it can't be built without additional source, e.g. by
combining with EDK II, and it has no entry points for easily
building it into a legacy BIOS.

AGESA in coreboot now relies on the FSP 2.0 framework published
by Intel and uses the existing fsp2_0 driver.

* Add fsp_memory_init() to romstage.c.  Although Picasso comes out
  of reset with DRAM alive, this call is added to maximize
  compatibility and facilitate internal development.  Future work
  may look at removing it.  AGESA reports the memory map to coreboot
  via HOBs returned from fsp_memory_init().
* AGESA currently sets up MTRRs, as in most older generations.
  Take ownership back immediately before running ramstage.
* Remove cbmem initialization, as the FSP driver handles this.
* Add chipset_handle_reset() for compatibility.
* Top of memory is determined by the FSP driver checking the HOBs
  passed from AGESA.  Note that relying on the TOM register happens
  to be misleading when UMA is below 4GB.

BUG=b:147042464
TEST=Boot trembyle to payload

Change-Id: Iecb3a3f2599a8ccbc168b1d26a0271f51b71dcf0
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34423
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01 23:27:26 +00:00
Raul E Rangel e04c2c4527 src/soc/amd/picasso: Add methods to save and restore MTRRs
FSP AGESA overrides the MTRRs that coreboot set up. Until this is fixed
we need to save and restore the MTRRs to undo what AGESA did.

Once AGESA is fixed, we can delete these files.

BUG=b:155426691, b:147042464
TEST=Boot trembyle and see MTRRs being modified
Saving Variable MTRR 0: Base: 0x00000000 0xff000005, Mask: 0x0000ffff 0xff000800
Saving Variable MTRR 1: Base: 0x00000000 0x08070006, Mask: 0x0000ffff 0xffff0800
Saving Variable MTRR 2: Base: 0x00000000 0x00000000, Mask: 0x00000000 0x00000000
Saving Variable MTRR 3: Base: 0x00000000 0x00000000, Mask: 0x00000000 0x00000000
Saving Variable MTRR 4: Base: 0x00000000 0x00000000, Mask: 0x00000000 0x00000000
Saving Variable MTRR 5: Base: 0x00000000 0x00000000, Mask: 0x00000000 0x00000000
Saving Variable MTRR 6: Base: 0x00000000 0x00000000, Mask: 0x00000000 0x00000000
Saving Variable MTRR 7: Base: 0x00000000 0x00000000, Mask: 0x00000000 0x00000000
Saving Fixed MTRR 0: 0x00000000 0x00000000
Saving Fixed MTRR 1: 0x00000000 0x00000000
Saving Fixed MTRR 2: 0x00000000 0x00000000
Saving Fixed MTRR 3: 0x00000000 0x00000000
Saving Fixed MTRR 4: 0x00000000 0x00000000
Saving Fixed MTRR 5: 0x00000000 0x00000000
Saving Fixed MTRR 6: 0x00000000 0x00000000
Saving Fixed MTRR 7: 0x00000000 0x00000000
Saving Fixed MTRR 8: 0x00000000 0x00000000
Saving Fixed MTRR 9: 0x00000000 0x00000000
Saving Fixed MTRR 10: 0x00000000 0x00000000
Saving Default Type MTRR: 0x00000000 0x00000800
Saving SYS_CFG: 0x00000000 0x00000800
...
MSR 0x200 was modified: 0x00000000 0x00000006
MSR 0x201 was modified: 0x0000ffff 0x80000800
MSR 0x202 was modified: 0x00000000 0x80000006
MSR 0x203 was modified: 0x0000ffff 0xc0000800
MSR 0x204 was modified: 0x00000000 0xc0000006
MSR 0x205 was modified: 0x0000ffff 0xf0000800
MSR 0x250 was modified: 0x06060606 0x06060606
MSR 0x258 was modified: 0x06060606 0x06060606
SYS_CFG was modified: 0x00000000 0x00740000


Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6048b25bd8a32904031ca23953f9726754b5a294
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40922
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01 23:26:24 +00:00
Andrey Petrov 4e48ac04da soc/intel/xeon_sp/cpx: Implement hide/unhide P2SB traditional dance
Perform the P2SB hide/unhide trick. This is needed so that BAR0
(0xfd000000) is not reclaimed by resource allocator, since it can
not deal with a device that does not exist (hidden).

Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: I5db0ae4e31d72ba86efba5728b2afc68d3180d5d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-05-01 23:12:12 +00:00
Andrey Petrov cf270f0d62 soc/intel/xeon_sp/cpx: Enable common P2SB
Use common P2SB driver. This is needed to address a problem when
enumerator does not see p2sb device (since it is hidden) but it
is active and BAR is decoded.

Change-Id: I9cb821a5684f15f1e1486872bf806a6ee3d0676f
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40920
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01 23:12:02 +00:00
Andrey Petrov 15070e7ea8 soc/intel/xeon_sp: Add C620 p2sb.h
Add p2sb.h that is shared by all currently supported Xeon SP CPUs.

Change-Id: Idcbff7ad587cb116897a953c079fb0a8b86cc2ed
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40919
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01 23:11:55 +00:00
Andrey Petrov 26679699cd mb/intel/cedarisland_crb: Enable P2SB device
Enable P2SB in static device tree so that hide/unhide trick
works.

Change-Id: I7dc20b001605b715155d333a07580e21a5f24136
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-01 23:11:44 +00:00
Andrey Petrov f8f9b282b4 mb/intel/cedarisland_crb: Populate 2-socket parameters for FSP-M
These parameters were found to work fine for 2-socket configuration,
for FSP based on tag 16.D.21.

Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: I466a7f2951ef307036ddaed0be0aacf98dd2710f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-01 23:11:38 +00:00
Maxim Polyakov 8fb221dbd5 md/tiogapass: move all *.h to dir and make them global
It is necessary to rename the file gpio.h so that there are no conflict
with another file (src/include/gpio.h)

Change-Id: I4e3ef5882d6cb0ddbcb8357b54106ff2f47e4c51
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40733
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01 22:13:08 +00:00
Maxim Polyakov d2b3e81095 xeon_sp, ocp/tiogapass: remove unused FSP-style GPIO defs
Change-Id: I8599dca99c1f34e3937c5b77b3505815ce625b46
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-01 22:12:41 +00:00
Maxim Polyakov d2b418bd33 mb/ocp/tiogapass: fix advanced _PAD_CFG_STRUCT macros in config
If the current pad configuration can not be defined using standard
macros from the gpio_defs.h [1], then the intelp2m utility generates
"advanced" _PAD_CFG_STRUCT() macros. However, often this configuration
in the vendor’s firmware is erroneous. Change the extended macros to
standard ones taking into account the information based on the schematic
diagram and the previous GPIO configuration for FSP-M [2].

[1] src/soc/intel/common/block/include/intelblocks/gpio_defs.h
[2] src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h

Change-Id: I56e45b1df77acbdd67e6325c3745a7ad137f8805
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
2020-05-01 22:12:18 +00:00
Maxim Polyakov 2bb3e78066 mb/ocp/tiogapass: rework GPIOs configuration using macros
This format of PCH GPIOs configuration, unlike the raw DW0 and DW1
registers values from the inteltool dump, is more understandable and
makes the code much cleaner. The gpio.h file with PAD_CFG macros was
automatically generated using the util/intelp2m [1] utility:

./intelp2m -p lbg -file tiogapass/vendorbios/inteltool_gpio.log

According to the documentation [2], the Host Software Pad Ownership
register only affects the pads that are configured as input (GPI).
The intelp2m utility takes this into account when converting macros
and ignores bits from this register for the corresponding pads.

[1] https://review.coreboot.org/c/coreboot/+/35643
[2] Intel Document Number: 549921

Change-Id: I21e98721e58b00be9196927837daa2b5d2560822
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40731
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01 21:58:15 +00:00
Maxim Polyakov 89d2aa0cdc mb/tiogapass: use common driver to configure GPIO
According to changes in the soc/xeon_sp code [1,2], server motherboards
with Lewisburg PCH can use the soc/intel/common/gpio driver to configure
GPIO controller. This patch adds pads configuration map, which has the
format required by the GPIO driver. The data for this was taken from the
inteltool register dump with AMI firmware. The gpio.h file with pad
configuration was generated automatically using the util/intelp2m [3]:

./intelp2m -raw -p lbg -file tiogapass/vendorbios/inteltool_gpio.log

[1] https: //review.coreboot.org/c/coreboot/+/39425
[2] https: //review.coreboot.org/c/coreboot/+/39428
[3] https: //review.coreboot.org/c/coreboot/+/35643

Change-Id: I818d040fa33f3e7b94b73c9bbbafca5df424616d
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39427
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01 21:39:21 +00:00
Andrey Petrov ed7d91d257 mb/ocp/sonorapass: Populate FSP-M parameters
Since CPX FSP headers are not released yet, populate certain
settings with hard-coded offsets. Provided values are probably
not correct and I do not understand what they mean and there is
no documentation available yet. However they were found to work
to a certain degree.

TEST=tested on OCP Sonora Pass EVT

Change-Id: I0f78cde69cb8a49a388a412b97bf8713e5b380ea
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40554
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01 16:40:42 +00:00
Elyes HAOUAS 6468d87dde soc/intel/baytrail: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I9b15b5458bb8140fa9bb6b0ffb6b9c78e8d8a93b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-05-01 16:40:20 +00:00
Ryback Hung f87ad9225c mb/ocp/sonorapass: Add Sonora Pass
Just a minimal set of board files needed to get it to boot
in 1 CPU mode.

Signed-off-by: Ryback Hung <ryback.hung%quantatw.com@gtempaccount.com>
Change-Id: Ia7b45c78b38d091bd9535899b681746e13efb4fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
2020-05-01 16:40:11 +00:00
Elyes HAOUAS d2bbc68fa3 soc/intel/baytrail: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I353daf35c843521b089ff8411a9ba8c801605ff9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-05-01 16:37:47 +00:00
Elyes HAOUAS 066e61f3ea soc/intel/braswell: Fix 16-bit read/write PCI_COMMAND register
Change-Id: Ie213b8c08e2d2b33a1dc1fda632163160d1cd70e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-05-01 16:37:13 +00:00
Elyes HAOUAS ad87d1c8b9 soc/intel/cannonlake: Fix 16-bit read/write PCI_COMMAND register
Change-Id: If7e2c84c39039e0dc6811f247390f856fc634b33
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-05-01 16:36:28 +00:00
Elyes HAOUAS 2ec1c13ac4 soc/intel/common: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I09cc69a20dc67c0f48b35bfd2afeaba9e2ee5064
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-05-01 16:36:26 +00:00
Elyes HAOUAS b887adf7a5 soc/intel/broadwell: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I0fd1a758d8838b3eea5640b41eee6a6893360aa3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-05-01 16:35:06 +00:00
Raul E Rangel 3e42ee05d8 cpu/x86/mtrr/earlymtrr: Validate MTRR arguments
The AMD64 Architecture Programmer's Manual, Volume 2: Systems
Programming says the following about variable MTRRs:

Variable Range Size and Alignment.
The size and alignment of variable memory-ranges (MTRRs) and I/O ranges
(IORRs) are restricted as follows:
* The boundary on which a variable range is aligned must be equal to the
range size. For example, a memory range of 16 Mbytes must be aligned on a
16-Mbyte boundary (i.e., naturally aligned).
* The range size must be a power of 2 (2^n , 52 > n > 11), with a minimum
allowable size of 4 Kbytes. For example, 4 Mbytes and 8 Mbytes are
allowable memory range sizes, but 6 Mbytes is not allowable.

Print out errors if these conditions are violated. I didn't assert since
`set_var_mtrr` can be used in boot block before the serial console is
enabled.

BUG=b:147042464
TEST=Boot trembyle and see MTRR errors:
MTRR Error: base 0xcc800000 must be aligned to size 0x1000000

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8b8c734c7599bd89cf9f212ed43c2dd5b2c8ba7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40762
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01 15:42:01 +00:00
Christian Walter e4c81bcca5 documentation: Add documentation ideas for season of docs
Let's gather some documentation ideas for the season of docs. I reused
the project ideas style (thanks Patrick). Feel free to add yourself as a
mentor here. Also if you have more ideas, please add them to the
document.

Change-Id: I72221cbd53b99cdc946109753cf72af9c865a1e5
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40662
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01 13:47:06 +00:00
Elyes HAOUAS 1234925ad7 sb/intel/i82801gx: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I11b8743234cb1292db8c930edecf8fb5c47d63fd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-05-01 11:51:08 +00:00
Subrata Banik 38df060aba mb/google/dedede: Fix crossystem wpsw_cur error
Add GPIO_PCH_WP (GPP_C11) to associate GPP_PCH_WP with community
zero.

TEST=Build coreboot, flash, boot to
and log into kernel, execute "wp enable" in console,
execute "crossystem" at kernel prompt and verify that "wpsw_cur"
shows as being "1", Execute "wp disable" in console, execute
"crossystem" at kernel prompt and verify "wpsw_cur" is 0.

Change-Id: Ie4ae1365a7611b8be3e795798c171e3f7ea9e417
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40744
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01 07:01:01 +00:00
Aaron Durbin 09f60ff0e2 soc/amd/picasso: initialize i2c controllers in SoC flow
BUG=b:153642124
TEST=Saw I2C communication

Change-Id: I31f8b97d1ff7b687d7e078d5b594d1ad73c815e7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2145457
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-01 06:59:22 +00:00
Raul E Rangel 4cf3af49ca soc/amd/picasso/bootblock: Remove duplicate sb_reset_i2c_slaves
sb_reset_i2c_slaves is called in fch_pre_init.

BUG=b:153675916
TEST=Builds on trembyle

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I157e473984257d633ceb3ef9df45c71a31c5c00b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-01 06:59:12 +00:00
Raul E Rangel f771b1669b soc/amd/picasso/bootblock/bootblock: Remove duplicate i2c init
fch_early_init already calls i2c_soc_early_init().

BUG=b:153675916
TEST=Boot trembyle and only see 1 i2c initialization message

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I689616fb617904df1781be3abe9d1dc580608173
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-01 06:59:03 +00:00
Aaron Durbin 89e51e6178 soc/amd/picasso: Allow mainboard to provide pci ddi descriptors
Mainboards must provide their DDI descriptors.

BUG=b:153502861

Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2146443
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2146439
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2146438
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2145453
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2145454
Change-Id: Ib3f115711e74d0e6eb5b063b3dccb36b265779af
Signed-off-by: Raul E Rangel <rrangel@chromium.org>

Reviewed-on: https://review.coreboot.org/c/coreboot/+/40875
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01 06:58:03 +00:00
Victor Ding b468f9b9ea ec/google/chromeec: Fix incorrect diag message
The expected error code observed in clear_pending_events() should
be EC_RES_UNAVAILABLE(9), not EC_RES_INVALID_COMMAND(1).

BUG=b:153896701

Change-Id: I609490ceef675267760d34b5e9775211da93347c
Signed-off-by: Victor Ding <victording@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40900
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01 06:57:11 +00:00
Eric Lai 5874c7831c mb/google/deltaur: Add BT reset gpio
Harrison Peak (HrP) 9560 module needs a reset pin for BT power sequence.

BUG=b:155248677
TEST=Boot into OS and check BT is functional.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I55ed1b095ba53c414c44088f4a6e7720b970e2f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-05-01 06:56:58 +00:00
Subrata Banik 7be0df8dd3 soc/intel/{jsl,tgl}: Rename PcdDebugInterfaceFlags macros for better understanding
BIT 1 -> DEBUG_INTERFACE_UART_8250IO
BIT 4 -> DEBUG_INTERFACE_LPSS_SERIAL_IO

Change-Id: I566b9dc82b2289af42e58705ebeee51179886f1f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-05-01 06:56:45 +00:00
Ivy Jian 1d17529954 mb/google/deltaur: Update USB/WWAN config
Update USB3 ports configuration as schematics design.

BUG=b:155026295
TEST=Boot into OS and check WWAN device detected by lsusb.

Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: Icb938e5a9c05fcc9772219b081a6f05334261baf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40818
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01 06:55:55 +00:00
Duncan Laurie ed6eb2713a acpi_device: Make integer array input variable const
An array of 64bit integers is passed to acpi_dp_add_integer_array() but
it is not const so can't take a const array without a compiler error.

The function does not modify the array so it can be made const without
breaking anything and allowing a const array to be passed in the future.

BUG=b:146482091

Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I98ecdaef5ddfa2026390e2812f5ea841ee51f073
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40882
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01 06:54:51 +00:00
Duncan Laurie de13519ca5 arch/x86/acpi: Add define for generic container HID
The generic container HID is defined in ACPI specification as PNP0A05.

BUG=b:146482091

Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I3632e77533a47f22b92259b469b03e63f51687e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-01 06:54:21 +00:00
Duncan Laurie c1adeb68a0 arch/x86/acpi_device: Allow empty child references
Currently if a child table is created and added to a property list
without adding any properties to that child it will generate an
empty package.  For example:

struct acpi_dp *dsd = acpi_dp_new_table("_DSD");
struct acpi_dp *prop = acpi_dp_new_table("PROP");
acpi_dp_add_child(dsd, "dsd-prop", prop);
acpi_dp_write(dsd);

Results in an empty PROP package:

Name (_DSD, Package (2)
{
  ToUUID("dbb8e3e6-5886-4ba6-8795-1319f52a966b")
  Package (1) {
    Package (2) {
      "dsd-prop",
      "PROP"
    }
  }
}
Name (PROP, Package (0)
{
}

Empty packages don't seem to be explicitly forbidden, but they don't
serve a purpose with device properties.  Instead, if packages without
any properties or children are skipped then this empty package is not
written and the added child property can refer to another property that
is already defined.

This allows creating property references to existing tables, which can
save duplication and namespace collision issues with nested properties.

BUG=b:146482091

Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I9fee2ceb8a4496b90c7210533eee8c2b186cdfff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-01 06:53:57 +00:00
Marco Chen 7d18f88c6d soc/intel/jasperlake: fix args of dimm_info_fill() for dram_part_num
BUG=b:152019429
BRANCH=None
TEST=1. provision dram_part_num field of CBI
     2. modify mainboard - dedede to report DRAM part number from CBI
     3. check DRAM part number is correct in SMBIOS for memory device

Change-Id: I509d06a81bd005c5afe6e74a2da2ca408dee7b29
Signed-off-by: Marco Chen <marcochen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-05-01 06:52:48 +00:00
Kevin Chiu 0025f777ed mainboard/google/kahlee: move specific setting to variant
Separate specific setting to variant from baseboard.
baseboard/romstage.c in current release is only utilized by
careena, we could remove it from the rest of variant build.

BUG=b:154357210,b:154848243
BRANCH=master
TEST=emerge-grunt coreboot

Change-Id: I658526e44aadc47bdc5538f506a1bfe2e5f20f63
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2020-05-01 06:50:54 +00:00
Patrick Rudolph 09a106907e soc/intel/cannonlake/bootblock: Fix FSP CAR
Fix FSP CAR on platforms that have ROM_SIZE of 32MiB.
CodeRegionSize must be smaller than or equal to 16MiB
to not overlap with LAPIC or the CAR area at 0xfef00000.

Tested on Intel CFL, the new code allows to boot using FSP-T.

Change-Id: I4dfee230c3cc883fad0cb92977c8f5570e1a927c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-01 06:48:44 +00:00
Evgeny Zinoviev d991bf1fb4 Doc/mb/51nb/x210: Do minor fixes
Fix code blocks, add a newline, use inline code blocks for commands.

Change-Id: Iecf04b00ed12323c124517f2557cc8b60640b618
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-05-01 06:44:07 +00:00
Sheng-Liang Pan f86c3265e8 mb/google/octopus/variants/bobba: Disable XHCI LFPS power management
LTE module is lost after idle overnight, with this workaround,
host will not initiate U3 wakeup at the same time with device,
which will avoid the race condition.

Disable XHCI LFPS power management.
If the option is set in the devicetree, the bits[7:4] in
XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated
from default 9 to 0.

BUG=b:146768983
BRANCH=octopus
TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash
     the image to the device. Run following command to check if
     bits[7:4] is set 0:
     >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"

Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Ib8e5ae79e097debf0c75ead232ddbb2baced2a2a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-05-01 06:43:06 +00:00
William Wei e11072e6c7 mb/google/volteer/malefor: Enable touch screen
Enable Goodix touch screen and ensure it works properly.

BUG=b:154191288
TEST=FW_NAME=malefor emerge-volteer coreboot chromeos-bootimage
Boot to kernel and check the Goodix touch screen function.

Signed-off-by: William Wei <wenxu.wei@bitland.corp-partner.google.com>
Change-Id: I236ac56dd0a1817092151bae93e699115ba88e4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40598
Reviewed-by: Alex Levin <levinale@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01 06:40:37 +00:00
Frans Hendriks 7023174b88 vc/eltan/security/verified_boot/vboot_check.c: Increase wb_buffer size
Running commit aee0baf069 on
Facebook fbg1701 results in an error:
VB2:vb2_rsa_verify_digest() ERROR - vboot2 work buffer too small!
ERROR: HASH table verification failed!

The actual vboot structures require more space.
Workbuffer size needs to be increased.

We didn't determine the commit causing the issue because this change
fixes the issue.

BUG=N/A
TEST=Build and boot Facebook fbg1701

Change-Id: I5caebc643eb493f4285c2f2fc164ff3a5d35e24e
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-05-01 06:38:37 +00:00
Jan Dabros a67cc5f5e8 tests: Add device/i2c-test test case
Add unit test for src/device/i2c.c module.

This patch is also used as an example for incorporating Cmocka mocking
feature (-wrap linker flag).

Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I2eeb565aacc724ae3b9f5c76ef4b98ef695416d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-05-01 06:33:49 +00:00
Jan Dabros 2d0ee36913 tests: Add lib/string-test test case
Show a basic example of how unit testing can be applied for the coreboot
project. Add a test harness for lib/string.c module.

TEST=Install cmocka via appropriate command:
sudo apt-get install -y libcmocka-dev
sudo emerge dev-util/cmocka
yum install libcmocka-devel
* Build and run unit tests via `make unit-tests`
* Check the output to see that tests passed.

Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: Ibf5554d1e99a393721a66bdd35af0122c2e412c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-05-01 06:33:38 +00:00
Jan Dabros ef1c968374 tests: Add build subsystem for unit testing coreboot
Add a subsystem which will be used for writing, building and running
unit tests for different coreboot's modules. This work is built using
Cmocka unit testing framework. Description of what unit testing means
(for the author) and how unit testing framework evaluation was performed
may be found in Documentation/technotes/2020-03-unit-testing-coreboot.md

Makefiles structure is very similar to this used for building coreboot
images. Every directory has its own Makefile.inc were tests' names,
sources, subdirs and multiple other test-related attributes are defined
in form of variables.

Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I9b0220b84b9a6e448476ca3eb3ccccc5fb829ad1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-05-01 06:32:47 +00:00
Jan Dabros 6449b67427 Documentation: Add proposal for firmware unit testing
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I552d6c3373219978b8e5fd4304f993d920425431
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-05-01 06:31:25 +00:00
Raul E Rangel da5e07e6c7 soc/amd/common/block/graphics/graphics: Add missing const to fill_ssdt
BUG=none
TEST=Made sure trembyle builds

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9df70fd5c41a9a68edc7be3c2e920c4dc94d5af9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40871
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01 06:30:03 +00:00
Benjamin Doron ac08c81836 mb/purism/librem_skl: Use ACPI backlight controls
Enables ACPI backlight controls.

Change-Id: Iccf50f427b7555ee1a3ef9cc11a89d532789ac54
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-05-01 06:29:22 +00:00