Commit Graph

24013 Commits

Author SHA1 Message Date
Nico Huber 8e50b6d63d sb/intel/bd82x6x: Let mainboard override SPI opmenu
For some SPI chips (e.g. those with AAI writes), the default OPMENU
definitions don't work well. Thus, provide an option to override the
defaults in the devicetree.

Writing the OPMENU now happens in ramstage instead of the SMM finalize
handler. If you let coreboot call the finalize handler, nothing should
change. If you call the handler from your payload, OTOH, the OPMENU
might have been changed in between, so be careful what you lock.

Change-Id: I9ceaf5b2d11365e21a2bebc9c5def1fcf0be8aad
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/23587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicola Corna <nicola@corna.info>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-04-05 15:58:37 +00:00
chriszhou 385e8fc5a9 mb/google/poppy/variants/nami: Add SPD file for Vayne
Add SPD file for sdp hynix_dimm_H5AN8G6NAFR-UHC (ram id: 6).

BUG=b:77290144
TEST=Verified that the device with this memory part boots to OS fine.

Change-Id: I33503de21c9fc14537c00c092986fd4d2998dace
Signed-off-by: chriszhou <chris_zhou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Shelley Chen <shchen@google.com>
2018-04-05 15:57:39 +00:00
Richard Spiegel 8e1f563cd6 mb/amd/gardenia/gpio.c: Convert GPIO to new format
New macros were developed that replace previous way of defining GPIO, with
pin and intention very clear while keeping the table mostly identical to
previous method (there's no pull up or pull down when a GPIO is set as an
output). Change current gardenia table to use the new macros.

BUG=b:72875858
TEST=Build Gardenia.

Change-Id: I402b95374cc5ba01bb961ebcb34d8e465b443c08
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25512
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-05 15:57:03 +00:00
T Michael Turney a12c6019b5 soc/qualcomm/sdm845: Add MMU support
Initialize 1st 4GB as Device Memory, except:
 * 1st page: NULL address
 * System_IMEM: Cached SRAM
 * Boot_IMEM: Cached SRAM

TEST=build

Change-Id: Ic6cf022b08bb2568fdf956cea8bad46da89236c5
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/25201
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-05 15:56:13 +00:00
T Michael Turney ace0c06de1 soc/qualcomm/sdm845: remove hole in memlayout.ld
Removed 33KB hole in SSRAM

TEST=build & run

Change-Id: I6851860f878d9a0688975fa855980870d657ee1a
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/25391
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-05 15:55:12 +00:00
Nico Huber c37b0e3d07 soc/intel/skylake: Generate ACPI DMAR table
If the SoC is VT-d capable, write an ACPI DMAR table. The entry for the
GFXVTBAR is only generated if the IGD is enabled.

Change-Id: I8176401dd19aee7ad09a8a145b7a3801fe5b2ae1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
2018-04-05 15:53:20 +00:00
Nico Huber 2afe4dc075 soc/intel/skylake: Enable VT-d and X2APIC
We use the usual static addresses 0xfed90000/0xfed91000 for the GFX
IOMMU and the general IOMMU respectively. These addresses have to be
configured in MCHBAR registers (maybe, who knows, the blob is undocu-
mented), advertised to FSP and reserved from the OS.

The new devicetree option `ignore_vtd` allows to retain the old beha-
viour (do whatever pre-set UPD values suggest).

We also let FSP set up distinct BDFs for messages originating from the
I/O-APIC and the HPET.

Change-Id: I77f87c385736615c127143760bbd144f97986b37
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
2018-04-05 15:52:45 +00:00
Patrick Rudolph db06cf0576 src/drivers/pl011: Add verstage support
Build pl011 to support building vboot on arm platforms.

Change-Id: I1ddc372d558b380065ff944fccb0d84eb37d4213
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-04-05 15:50:52 +00:00
Martin Roth 99519bc0aa mainboard/google/kahlee: Update WP to active low
The WP signal to the AP isn't inverted as it is on other platforms, so
it was reporting incorrectly.  Change the ACPI table to be active low,
and invert the signal when reporting it to everything else.

BUG=b:74946358
TEST=Boot grunt with battery inserted, WP signals both report 1.  Remove
battery, WP_CUR reports 0, WP_BOOT still reports 1.

Change-Id: Ic1369dbda609e34b308af308880449643be6af39
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/25469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-05 15:50:07 +00:00
Ivan J 85c76c9bc0 intelmetool: Include <sys/io.h> for musl-libc
This allows compiling the program using musl-libc, since otherwise
iopl(2) is undeclared.

Change-Id: Ia27203cf47b9be3f7bf1ad422c8f490caeae8f56
Signed-off-by: Ivan J. <parazyd@dyne.org>
Reviewed-on: https://review.coreboot.org/23834
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-05 14:01:39 +00:00
Naresh G Solanki f92fcabba8 x86: Add function to modify CR3 register
Register CR3 holds the physical address of paging-structure hierarchy.
Add functions to enable read/write of this register.

Change-Id: Icfd8f8e32833d2c80cefc8f930d6eedbfeb5e3ee
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/25478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-05 10:17:29 +00:00
Sumeet Pawnikar 65d2d21a04 mb/google/octopus/variants/baseboard: Set PL1 and PL2 value
This patch sets PL1 value to ~6W. Here, 8W setting gives
a run-time 6W actual measured power.
Also, this patch sets PL2 value to 15W.

BUG=None
BRANCH=None
TEST=Build and read the MSR 0x610.

Change-Id: I2439a49b9917db0d9b05f333ce1c35003da493f6
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/25341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-04 16:19:56 +00:00
Jonathan Neuschäfer 2f828ebb59 nb/intel/gm45/raminit: Use CxDRT*_MCHBAR instead of magic numbers
This is hopefully more readable.

TEST=Build lenovo/x200 with and without this patch (using make
BUILD_TIMELESS=1), compare build/coreboot.rom, notice no differences.

Change-Id: I079d5353633a3d58ce0e5e616f3fad687a064d65
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23709
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-04 13:44:47 +00:00
Vaibhav Shankar 0b861daecc mainboard/google/zoombini: Enable HAVE_ACPI_RESUME
This patch selects `HAVE_APCI_RESUME` to enable S3 resume. This
has a dependency on EC to store the hash.

BUG=b:72472969
TEST=suspend and resume from S3 should work.

Change-Id: I9de84dfd450936b3bc08e016bec6cf5ae88eab3d
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/25390
Reviewed-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-03 23:07:01 +00:00
Patrick Rudolph 03c7b05a5a include/string: Add strrchr
Copy strrchr from libpayload.
To be used by Cavium's BDK or FDT parsers.

Change-Id: Iab7981c25113ed16f1b8130de4935d30c29d2fa5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-04-03 14:16:16 +00:00
Julius Werner 4783db2cf1 spi: Add helper functions for bit-banging
Sometimes when bringing up a new board it can take a while until you
have all the peripheral drivers ready. For those cases it is nice to be
able to bitbang certain protocols so that you can already get further in
the boot flow while those drivers are still being worked on. We already
have this support for I2C, but it would be nice to have something for
SPI as well, since without SPI you're not going to boot very far.

This patch adds a couple of helper functions that platforms can use to
implement bit-banging SPI with minimal effort. It also adds a proof of
concept implementation using the RK3399.

Change-Id: Ie3551f51cc9a9f8bf3a47fd5cea6d9c064da8a62
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/25394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-03 00:34:52 +00:00
Julius Werner ffeee42091 rockchip: Add gpio_set() function
The <gpio.h> API is supposed to include a gpio_set() function that just
toggles the state of a GPIO already configured as an output, even though
we rarely need it since gpio_output() can already be used to initialze a
GPIO to a default value while configuring it as an output. This function
was forgotten on Rockchip, so this patch adds it now.

Change-Id: I201288139a2870e71f55a7af0d79d4a460b30a0c
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/25393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-03 00:34:46 +00:00
Hannah Williams e7e35674d6 mb/google/octopus: Fix Trackpad interrupt GPIO config
BUG=b:73137125
TEST= tested trackpad on Octopus
Change-Id: Icc416e7be4e42bda188f74c69db150ba42562128
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/25415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-02 21:40:24 +00:00
Martin Roth d738749d47 src/soc/stoneyridge: Add a check for CMOS failure
BUG=b:77345148
TEST=Pull power from grunt, verify CMOS power failure is detected.
Reboot and verify that CMOS power failure is not detected.

Change-Id: Idbf0254e197a6d282e618a98bced52ea5a44917f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/25468
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-02 21:03:34 +00:00
Hannah Williams 8dce5bcca5 mb/google/octopus: Make PMC I2C pads IOSTANDBY_IGNORE
This fixes wake from S0ix

Change-Id: I3b340deafccbf909ec1f4b11ba9a77c6b13a89fd
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/25467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-02 17:36:56 +00:00
Furquan Shaikh d6630d1165 x86: Increase time out for parking APs to 250ms
Change f43adf0 (intel/common/block/cpu: Change post_cpus_init after
BS_DEV RESOURCES) moved post_cpus_init to BS_OS_RESUME for S3
path. This results in BSP timing out waiting for APs to be
parked. This change increases the time out value for APs to be parked
to 250ms. This value was chosen after running suspend-resume stress
test and capturing the maximum time taken for APs to be parked for
100 iterations. Typical values observed were ~150ms. Maximum value
observed was 152ms.

BUG=b:76442753
TEST=Verified for 100 iterations that suspend-resume does not run into
any AP park time out.

Change-Id: Id3e59db4fe7a5a2fb60357b05565bba89be1e00e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-04-01 20:01:34 +00:00
Zhuohao Lee 7824d9bf69 chromeec: fix an uninitialized local variable
google_chromeec_command() may only write the 1 or 2 bytes to
variable r (4 bytes). However, this api returns 4 bytes data.
To avaid returning the incorrect data, we need to initialize the
local variable.

BUG=b:76442548
BRANCH=none
TEST=write 2 bytes data into the flash, then, read by cbi_get_uint32

Change-Id: I3395c97ab6bfd7882d7728310de8a29041190e76
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/25460
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-01 19:50:30 +00:00
Lijian Zhao b1fc13ac9a arch/x86/smbios: Consider corner case of Part Number
In case of all DMI Type 17 to be empty, the strip trailing whitespace
code will have a zero length Part Number entry, which will cause
exception when using (len - 1) where len is zero. Add extra code to
cover this corner case.

BUG=b:76452395
TEST=Boot up fine with meowth platform, without this patch system will
get stuck at "Create SMBIOS type 17".

Change-Id: Id870c983584771dc1b60b1c99e95bbe7c0d25c4c
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25377
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-01 19:43:01 +00:00
Arthur Heymans c2a9f0cf76 drivers/spi/flashconsole.c: Fix broken header
Change-Id: I61d28791fa75a32591448fc2c40186acfddca86d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/25413
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-01 18:10:45 +00:00
M Naveen f0082ac71a mb/google/octopus: update SSP port and DMIC 4CH nhlt support
Patch corrects SSP configuration to enable audio on GLK boards.
Octopus variant board uses max98357a speaker codec and 4CH DMIC,
Select the appropriate NHLT blob to be packaged in CBFS.

Change-Id: I101ed80f4421925120116b018424ef19d95a2a3a
Signed-off-by: Naveen Manohar <naveen.m@intel.com>
Reviewed-on: https://review.coreboot.org/25387
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.corp-partner.google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-01 17:41:56 +00:00
Matt DeVillier 76d17719fe soc/intel/skylake: Save/restore GMA OpRegion address
Add global/ACPI nvs variables required for IGD OpRegion.
Add functions necessary to save the ACPI OpRegion table
address in ASLB, and restore table address upon S3 resume.

Implementation modeled on existing Baytrail code.

Test: boot Windows 10 on google/chell with Tianocore payload and
GOP display init, observe display driver loaded and functional,
display not black screen when resuming from S3 suspend.

Change-Id: Icd6b514e531eec6e49dbb03eb765144f41c1e31b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/25198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-03-30 07:21:03 +00:00
Matt DeVillier 132bbe6be5 soc/intel/braswell: Save/restore GMA OpRegion address
Add global/ACPI nvs variables required for IGD OpRegion.
Add functions necessary to save the ACPI OpRegion table
address in ASLB, and restore table address upon S3 resume.

Implementation modeled on existing Baytrail code.

Test: boot Windows 10 on google/edgar with Tianocore payload and
GOP display init, observe display driver loaded and functional,
display not black screen when resuming from S3 suspend.

Change-Id: I7c1fbf818510949420f70e93ed4780e94e598508
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/25197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-03-30 07:20:38 +00:00
Patrick Rudolph c7edf18f7c soc/intel/common/opregion: Get rid of opregion.c
Get rid of custom opregion implementation and use drivers/intel/gma/opregion
implementation instead.

Test: boot Windows 10 on google/chell and google/edgar using Tianocore
payload with GOP init, observe Intel graphics driver loaded and functional.

Change-Id: I5f78e9030df12da5369d142dda5c59e576ebcef7
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21703
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-30 07:19:52 +00:00
Shamile Khan 0bcd86a14a mb/google/octopus: Enable i2c4 which is the root port for audio codec
BUG=None
BRANCH=None
TEST=On octopus, "aplay -l" shows the Audio codec.

Change-Id: I5d837d62f00d34edf28fd472ae0dbe7c0d94447a
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/25376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-30 07:18:57 +00:00
Kane Chen 5b84fad5a9 soc/intel/skylake: Protect me_progress_rom_values array boundary
me_progress_rom_values array provides detailed information maps to ME
HFSTS2 register value.

There is a chance that ME status value might be over the size of
me_progress_rom_values.

This commit adds a check before access the array.

BUG=b:77247550

Change-Id: I5de569c62b94b0595d3d3ea254f50e312e8c11a4
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/25425
Reviewed-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-30 06:43:12 +00:00
Duncan Laurie ba49c09b2f mb/google/poppy: Add variant for Atlas
Add a new variant of Poppy for the Atlas board.

BUG=b:75454415
TEST=tested on a P0 board.  System boots and is mostly
functional, though some peripherals are not ready so there
are no touchpad/touchscreen devices configured yet.

Change-Id: I5a0bccd1bda0134aa51885ac2c6e7bb5b45de924
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/25389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-30 02:57:06 +00:00
Furquan Shaikh ade3bc5c40 mb/google/octopus: Fix wifi configuration
This change updates devicetree and GPIO configurations to match the
schematics:
1. pcie_rp...[2] is the one being used for wifi, thus, clk_req and
deemphasis_enable for [2] need to be set instead of [0].
2. WLAN power enable, wifi disable and PERST# GPIOs need to be
configured correctly.

BUG=b:76180142
TEST=Verified that wlan0 scan works.

Change-Id: Ic51a94902e2cac3491081ade32079e5b88719f45
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-03-29 21:53:42 +00:00
Duncan Laurie f5116952bb soc/intel/skylake: Limit xDCI feature when VBOOT is enabled
Use the common xDCI function to check if the controller is allowed
in the current mode before enabling it.  Otherwise, disable the
PCI device if it has been enabled in devicetree.

To make the SOC behavior consistent the XdciEnable config option
is removed in favor of direct control by devicetree.cb and the
mainboards that had defined it were adjusted accordingly.

This was tested on an Eve board with xDCI enabled in devicetree.cb
to ensure the xDCI device is enabled in developer mode and disabled
in normal mode.

Change-Id: Ic3c84beac87452f17490de32082030880834501d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/25365
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-28 22:52:38 +00:00
Arthur Heymans 8b76605a4a nb/intel/gm45: Allocate a 8M TSEG region
Tested on Thinkpad X200.

Change-Id: I9db7a71608aaec956a7b22649498b97d58f35265
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23418
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-28 06:49:19 +00:00
Arthur Heymans a050817ce5 sb/intel/common: Add common code for SMM setup and smihandler
This moves the sandybridge both smm setup and smihandler code to a
common place.

Tested on Thinkpad X220, still boots, resume to and from S3 is fine
so smihandler is still working fine.

Change-Id: I28e2e6ad1e95a9e14462a456726a144ccdc63ec9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-03-28 06:49:08 +00:00
Roy Mingi Park a6ab9afc49 mb/intel/glkrvp: Enable ThunderPeak wifi card
This enables ThunderPeak WiFi card on M.2.

TEST=Verify wlan card shows up in lspci

Change-Id: I5b3f871bdc67bfc4ed283b997b2a5698451b2bd2
Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-on: https://review.coreboot.org/24931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-28 06:47:47 +00:00
Matt DeVillier 9aae51ad11 soc/intel/common/block: add VMX support
Enable VMX if supported by CPU and enabled in board devicetree.
Check lock bit unset before enabling VMX.

Change-Id: Ic57eac45e9c65baa4479735c6d70a7eb685f080e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/25331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-28 06:46:28 +00:00
Duncan Laurie 2410cd9379 soc/intel/cannonlake: Limit xDCI feature when VBOOT is enabled
Use the common xDCI function to check if the controller is allowed
in the current mode before enabling it.  Otherwise, disable the
PCI device if it has been enabled in devicetree.

To make the SOC behavior consistent the XdciEnable config option
is removed in favor of direct control by devicetree.cb.

Change-Id: I34e7d750d3f75757a68977ae8d92bfbee1a10af1
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/25366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-28 06:44:02 +00:00
Duncan Laurie 4c8fbc0658 soc/intel/apollolake: Limit xDCI feature when VBOOT is enabled
Use the common xDCI function to check if the controller is allowed
in the current mode before enabling it.  Otherwise, disable the
PCI device if it has been enabled in devicetree.

Change-Id: I5aea15511c52d1191babf551feb237f4144683e4
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/25364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-28 06:43:40 +00:00
Duncan Laurie 4df7d2c495 soc/intel/common: Add function to check if xDCI is allowed
When CONFIG_VBOOT is enabled then the xDCI controller should only be
enabled if the system is in developer mode.  This prevents a system
in normal/verified mode from being used as a USB peripheral device
which could potentially be used to access user data.

This change adds a function to return whether xDCI can be enabled
or not, which will be used by the SOCs.

Change-Id: Ie3ee9dd7077c094a01fd857a2e4033a12ce8979b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/25347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-28 06:43:03 +00:00
Matt DeVillier 969ef10f54 soc/intel/skylake: enable VMX support
Use soc/common VMX block to enable VMX on supported devices.

Change-Id: Iaa1a6201b431783d709c0509715fa8e8b1ce349a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/25332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
2018-03-28 06:42:34 +00:00
Vaibhav Shankar 83abfdfb21 mainboard/google/meowth: Disable debug consent and enable S0ix
This patch disables debug consent in the devicetree. When debug
consent is set to DBC by default, it prevents some clocks from turning
off during S0ix. This blocks S0ix entry.

This patch also enables S0ix from the devicetree.

BUG=b:76163091
TEST=enter S0ix and check if slp_s0 is asserted

Change-Id: I05001a41b13e7784c34fa8f1f773fb94bbdcd01f
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/25312
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-28 06:42:00 +00:00
Van Chen f47c2c5ce6 mb/google/poppy/variants/nami: Add SPD file for sona.
Add SPD file for sdp samsung_dimm_K4A8G165WC-BCTD (ram id: 8).

BUG=b:76086834
TEST=Verified that the device with this memory part boots to OS fine.

Change-Id: I49fa114f07ad2eef10f18de9f6c3380173681bdd
Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25379
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-28 00:28:19 +00:00
Duncan Laurie e6c8a38986 soc/intel/skylake: Add NHLT config for max98373 codec
Add the NHLT configuration for the max98373 codec to skylake,
taken directly from cannonlake.

This will allow skylake/kabylake boards to use this codec.

Change-Id: Ifb6bf2d31fda25b18d9b1ce2bb721255335d55e4
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/25367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: HARSHAPRIYA N <harshapriya.n@intel.com>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
2018-03-27 19:55:48 +00:00
Duncan Laurie 314db17c69 mainboard/google/poppy: Add SPD for Hynix H9CCNNNCLGALAR-NUD
Add an SPD for this particular Hynix memory type to the poppy board
so it can be used by poppy variants.

BUG=b:75454415

Change-Id: I2249c7a4f2c83ec2b3266047a74b9bc22dad43be
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/25368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-27 19:55:44 +00:00
Nico Huber 54fe32f677 inteltool: Add some Skylake desktop ids
Change-Id: I1738a2544eb2435cb4b8718bcce5170d1ef04f72
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/25144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-03-27 15:42:14 +00:00
Furquan Shaikh be04583331 soc/intel/skylake: Do a heci_reset before reading ME firmware version
This change adds a call to heci_reset before attempting to read
ME firmware version. This is important to ensure that both ME and BIOS
are in sync.

BUG=b:76167737
BRANCH=poppy
TEST=Verfied that ME firmware version read does not fail on first boot
after power failure (i.e. removing battery and AC power).

Change-Id: Ib6b39c398d2e1177b087352a4acb8bcf5a9897d6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-27 06:10:14 +00:00
Furquan Shaikh b7b49b00de mb/google/octopus: Remove emmc tuning parameters from devicetree
Current emmc tuning parameters for octopus were copied over from other
boards and result in failure to boot from emmc. This change gets rid
of the emmc tuning parameters in devicetree. Once emmc tuning tests
are run for octopus, these parameters can be added back.

BUG=b:75986903
BRANCH=None
TEST=Verified that octopus boots from eMMC without any errors in
depthcharge.

Change-Id: I7ac44a54afd1ecfe355a9654ac8e92133b67637f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-27 03:26:39 +00:00
Julius Werner ae423852c2 vboot: Update to most recent GBB flag usage
This patch changes the GBB flag configuration to the latest usage in
upstream vboot (as of https://chromium-review.googlesource.com/976660).

Change-Id: I585d662d7de34b4964d028e3d06b4df5665fbe9e
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/25346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-26 22:46:44 +00:00
Youness Alaoui be78775a93 ec/purism: Fix CPU Turbo value (PPCM) set by the EC
The EC needs to set the PPCM value depending on whether
Turbo is enabled or not, and the values differ between
Broadwell (0, 1) and Skylake (1, 2) platforms.

Change-Id: I662dce54415e685c054ffc00b6afde0f1f7765e2
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/25329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-03-26 10:25:58 +00:00