Commit Graph

19144 Commits

Author SHA1 Message Date
Martin Roth 9369e10f1f payloads/external/Makefile.inc: Clean up makefile
- Add comments dividing the payload sections.
- Move separate TINT and Memtest sections that were intermingled.

Change-Id: If0bbd6e182359c5186a8b958dd2c9ab9f0e0a3f3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17046
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-10-25 21:14:36 +02:00
Aaron Durbin 06590a2014 Revert "soc/apollolake: Add soc core init"
This reverts commit a52f883b10
(https://review.coreboot.org/16587).

The above commit caused another sever kernel boot regression upwards
of 2 minutes to get through kernel init on quad core systems.

BUG=chrome-os-partner:58994

Change-Id: Id4abc332bf2266e3b3b7be714371ce9cf329bcd9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17121
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-10-25 19:27:50 +02:00
Yidi Lin 79daac9890 google/oak: Add derivative board Hana
CQ-DEPEND=CL:379684
BUG=chrome-os-partner:58064
TEST=verified on hana rev0

Change-Id: Icd076dcaf07a97f3b83b428b9619e8a4dafe744d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7c483951a0dcd419735fffb79e6187f9ca3b08a8
Original-Change-Id: I9d886abf15931496ac61e8fd38d7fd306f2a1bf7
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/379504
Original-Commit-Ready: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Philip Chen <philipchen@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17107
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-25 17:10:49 +02:00
Patrick Georgi 4003283c51 util/scripts: add copyright notices
Change-Id: Ia40543e5585845e5e6c178a620052c6a25927a5c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/17102
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-25 17:10:14 +02:00
Lin Huang 4ef9899bfe rockchip/rk3399: gru/kevin: drop unused sdram configs
There are some sdram configurations that are no longer used. Drop them.

BUG=None
BRANCH=None
TEST=None

Change-Id: Ib6d2d58c3071147a3095bc1ed7fa7b02c748e1a5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 111d375005ec6a3b91e47acdd676e8f1644c931c
Original-Change-Id: I5f9278093f02e785b2894faa8e8cf09ecec20325
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/399122
Original-Commit-Ready: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17103
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-25 17:09:55 +02:00
Patrick Georgi cd48d19836 Rename and move util/gitconfig/rebase.sh
It has nothing to do with git configuration, but is one of our
convenience scripts. It also has nothing to do with rebases (except that
it can be comfortably used through git rebase --exec)

Change-Id: Icc60c4de486a0027fe2230e93b441e62ba022193
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/17101
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-25 17:09:19 +02:00
Patrick Georgi 45037c8732 Drop convert-all-depthcharge-fmap.dts.sh script
The relevant data is gone in Chrome OS depthcharge's master branch, and
so the script outlived its usefulness.

Change-Id: I04f3f168e23d4bc7c31692263a8eec3f97ee50de
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/17100
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-25 17:09:12 +02:00
Lin Huang df3321aa34 rockchip/rk3399: reset system if DDR init fails
We found sdram may fail in pctl_cfg(), so we check the status in this
function. If it exceeds 100ms still in this function, we will restart
the system. We also found there are rare chances DDR training fails,
so also restart system in that case.

BUG=chrome-os-partner:57988
BRANCH=None
TEST=coreboot resets on failure and eventually the system comes up

Change-Id: Icc0688da028a8f4f81eafe36bbaa79fdf2bcea74
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 89e45f8352f62e19a203316330aba14ccc5c8b11
Original-Change-Id: If4e78983abcfdfe1e0e26847448d86169e598700
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/397439
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17045
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-25 17:08:58 +02:00
Jonathan Neuschäfer 65a9462a73 mb/emulation: Select QEMU-i440fx by default
It's a better default than QEMU-armv7, which is currently the default
board when coreboot is configured for the first time, because most
coreboot development targets x86.

With this patch, the minimal steps to coreboot+SeaBIOS booting in QEMU
become:

    git clone https://review.coreboot.org/coreboot.git && cd coreboot
    make crossgcc-x86
    make olddefconfig && make
    qemu-system-x86_64 -bios build/coreboot.rom

Change-Id: Ie44a5d95547a55df93f29082c3b5a86fb83aa1e7
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16987
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-10-25 01:31:43 +02:00
Furquan Shaikh 4a2cfad13b arch/x86/acpigen_dsm: Add support for DSM types
Currently, the only supported DSM type is I2C
HID(3CDFF6F7-4267-4555-AD05-B30A3D8938DE). This provides the required
callbacks for generating ACPI AML codes for different function
identifiers for I2C HID.

BUG=chrome-os-partner:57846

Change-Id: Ia403e11f7ce4824956e3c879547ec927478db7b1
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17091
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-25 00:13:32 +02:00
Furquan Shaikh c00bd18b13 arch/x86/acpigen: Add support for _DSM method generation
Add acpigen_write_dsm that generates ACPI AML code for _DSM
method. Caller should provide set of callbacks with callback[i]
corresponding to function index i of DSM method. Local0 and Local1
should not be used in any of the callbacks.

BUG=chrome-os-partner:57846

Change-Id: Ie18cba080424488fe00cc626ea50aa92c1dbb199
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17090
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-25 00:13:16 +02:00
Furquan Shaikh 1d33488968 drivers/i2c/generic: Re-factor SSDT generation code
1. Export i2c_generic_fill_ssdt to allow other device-specific i2c
drivers to share and re-use the same code for generating AML code for
SSDT. In order to achieve this, following changes are required:
 a. Add macro I2C_GENERIC_CONFIG that defines a structure with all
 generic i2c device-tree properties. This macro should be placed by the
 using driver at the start of its config structure.
 b. Accept a callback function to add any device specific information to
 SSDT. If generic driver is used directly by a device, callback would be
 NULL. Other devices using a separate i2c driver can provide a callback
 to add any properties to SSDT.
2. Allow device to provide _CID.

BUG=chrome-os-partner:57846

Change-Id: I3a0054e22b81f9d6d407bef417eae5e9edc04ee4
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17089
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-10-25 00:13:05 +02:00
Furquan Shaikh 9b39adb454 arch/x86/acpigen: Add more functions to ACPIGEN library
1. If (LEqual (Op1, Op2))
2. ToBuffer (src, dst)
3. ToInteger (src, dst)
4. Buffer (n) { op1, op2 .... }
5. Return ( )

BUG=chrome-os-partner:57846

Change-Id: I24fe647c690b2dd4849f0c53b2672ac7a2caa2de
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17088
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-25 00:10:05 +02:00
Furquan Shaikh 3ce104e5d8 mainboard/google/reef: Add PowerResource for ELAN touchscreen
Define reset_gpio and enable_gpio for touchscreen device so that when
kernel puts this device into D3, we put the device into
reset. PowerResource _ON and _OFF routines are used to put the device
into D0 and D3 states.

BUG=chrome-os-partner:55988

Change-Id: Ia905f9eb630cd96767b639aec74131dbd7952d0e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17083
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-10-25 00:09:41 +02:00
Furquan Shaikh 00a9e38f74 soc/intel/apollolake: Implement GPIO ACPI AML generating functions
Implement GPIO ACPI AML generating functions that can be called by
coreboot drivers to generate GPIO manipulation code in AML. Following
functions are implemented:
1. acpigen_soc_read_rx_gpio
2. acpigen_soc_get_tx_gpio
3. acpigen_soc_set_tx_gpio
4. acpigen_soc_clear_tx_gpio

BUG=chrome-os-partner:55988

Change-Id: I3d8695d73a1c43555032de90f14ee47ccee45559
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17082
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-10-25 00:09:29 +02:00
Furquan Shaikh 626ad205a7 drivers/i2c/generic: Enable support for adding PowerResource for device
Add support to allow a device to define PowerResource in its SSDT AML
code. PowerResouce ACPI generation expects SoC to define the
callbacks for generating AML code for GPIO manipulation.

Device requiring PowerResource needs to define following parameters:
1. Reset GPIO - Optional, GPIO to put device into reset or take it out
of reset.
2. Reset delay - Delay after reset GPIO is de-asserted (default 0).
3. Enable GPIO - Optional, GPIO to enabled device.
4. Enable delay - Delay after enable GPIO is asserted (default 0).

BUG=chrome-os-partner:55988

Change-Id: Ieb2dd95fc1f555f5de66f3dda425172ac5b75dad
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17081
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
2016-10-25 00:09:19 +02:00
Elyes HAOUAS f5f0b7b71a mainboard/emulation: Use C89 comments style & remove commented code
Change-Id: I627338505fe1273366bc8f6f528d829b3162b371
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16916
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-24 20:32:47 +02:00
Elyes HAOUAS dedccb8556 mainboard/amd/tilapia_fam10: Use C89 comments style & remove commented code
Change-Id: I7515288190ca57a321fb8ffe57a1181b638c336a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16978
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-24 20:32:21 +02:00
Elyes HAOUAS caccd97d4e mainboard/amd/serengeti_cheetah*: Use C89 comments style & remove commented code
Change-Id: I2fae9e02e2fccaff97f2441fd17f8960e8ab9786
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16975
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-24 20:31:50 +02:00
Elyes HAOUAS 15622ee5f0 mainboard/amd/mahogany: Use C89 comments style & remove commented code
Change-Id: Ife9c0b8a1ab55fe683c88e34239d7f5806e1ff9b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16971
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-24 20:31:30 +02:00
Elyes HAOUAS 767f6e80b7 mainboard/amd/lamar: Use C89 comments style & remove commented code
Change-Id: I765814450b82755f84c010f63bc8f919bb0cd4c1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16970
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-24 20:31:11 +02:00
Arthur Heymans a6b0fc9d7c nb/i945/Kconfig: select the correct VGA_BIOS_ID for 945GC
Change-Id: I48ae27c5460020b9118e6ade1a3e610b542999c7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17040
Tested-by: build bot (Jenkins)
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-24 20:30:56 +02:00
Ronald G. Minnich 5965cba3dc RISCV: Clean up the common architectural code
This version of coreboot successfully starts a Harvey (Plan 9) kernel as a payload,
entering main() with no supporting assembly code for startup. The Harvey port
is not complete so it just panics but ... it gets started.

We provide a standard payload function that takes a pointer argument
and makes the jump from machine to supervisor mode;
the days of kernels running in machine mode are over.

We do some small tweaks to the virtual memory code. We temporarily
disable two functions that won't work on some targets as register
numbers changed between 1.7 and 1.9. Once lowrisc catches up
we'll reenable them.

We add the PAGETABLES to the memlayout.ld and use _pagetables in the virtual
memory setup code.

We now use the _stack and _estack from memlayout so we know where things are.
As time goes on maybe we can kill all the magic numbers.

Change-Id: I6caadfa9627fa35e31580492be01d4af908d31d9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/17058
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-10-24 20:25:04 +02:00
Furquan Shaikh 0a48aee795 arch/x86/acpigen: Add support for interacting with GPIOs
Since reading/toggling of GPIOs is platform-dependent task, provide an
interface with common functions to generate ACPI AML code for
manipulating GPIOs:
1. acpigen_soc_read_rx_gpio
2. acpigen_soc_get_tx_gpio
3. acpigen_soc_set_tx_gpio
4. acpigen_soc_clear_tx_gpio

Provide weak implementations of above functions. These functions are
expected to be implemented by every SoC that uses ACPI. This allows
drivers to easily generate ACPI AML code to interact GPIOs.

BUG=chrome-os-partner:55988

Change-Id: I3564f15a1cb50e6ca6132638447529648589aa0e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17080
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-24 17:44:15 +02:00
Furquan Shaikh fcc7a04cc8 arch/x86/acpigen: Add new functions to acpigen library
Add functions to support generation of following AML operations:
1. PowerResource
2. Store
3. Or
4. And
5. Not
6. Debug
7. If
8. Else
9. Serialized method

BUG=chrome-os-partner:55988

Change-Id: I606736b38e6a55ffdc3e814b6ae0fa367ef7595b
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17079
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-10-24 17:44:00 +02:00
Furquan Shaikh e4e9b94db1 arch/x86/acpigen: Clean up acpigen library
Instead of using hard-coded values for emitting op codes and prefix
codes, define and use enum constants. With this change, it becomes
easier to read the code as well.

BUG=chrome-os-partner:55988

Change-Id: I6671b84c2769a8d9b1f210642f3f8fd3d902cca2
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17078
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-10-24 17:43:47 +02:00
Furquan Shaikh 3f4e627200 drivers/i2c/generic: Return correct name for acpi_name
Return config->name if it is not NULL.

BUG=chrome-os-partner:55988

Change-Id: I9ae229949b73de6f991383daae8d962d6cf457a7
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17077
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-24 17:43:35 +02:00
Elyes HAOUAS 8e64174137 mainboard/amd/db-ft3b-lc: Use C89 comments style & remove commented code
Change-Id: I2a3bf53e6bc4084305238fa176ae46161da4be8f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16967
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-21 19:43:33 +02:00
Elyes HAOUAS a8802577ea mainboard/amd/bimini_fam10: Use C89 comments style & remove commented code
Change-Id: I4e628cbe11da32d291c4b8e4c7be91e9b0a86ad9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16966
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-21 19:43:17 +02:00
Elyes HAOUAS 874fe1d328 mainboard/amd/bettong: Use C89 comments style & remove commented code
Change-Id: I137b27ffb0e54a9ca6b0bd3a454b1d99b3e1c22b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16907
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-21 19:42:55 +02:00
Daisuke Nojiri a51d2db4f0 marvell/mvmap2315: Compose BOOTBLOCK region
This patch adds a Makefile rule for mvmap2315 to install a BDB and
bootblock code in the BOOTBLOCK region. The resulting BDB has a
header and data both signed by a RSA-4096 key.

BUG=chrome-os-partner:57889
BRANCH=none
TEST=emerge-rotor coreboot and examined the output binary. Booted
coreboot.rom.

Change-Id: I1e20a09b12f8f8ed4d095aa588e3eb930f359fc5
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/16747
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-21 19:42:23 +02:00
Martin Roth 8337a3867b 3rdparty/vboot: update to latest master for rotor support
This pulls in the bdb support for futility so that rotor can build.

Change-Id: Icfa432fb840bea3e1616933ed02cf34a681fa3ce
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17061
Tested-by: build bot (Jenkins)
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
2016-10-21 19:39:00 +02:00
Martin Roth 0529236ed2 Makefile.inc: Don't share amdfwtool between platforms
amdfwtool currently gets built for a specific size of ROM chip.  This
should be updated to be passed in on the amdfwtool command line, but
until that's done, stop sharing the tool between builds.

This caused a problem for abuild when we tried changing the default
rom to one that used a 256KB rom chip.  That wasn't large enough for
all of the files included by amdfwtool on several platforms, causing
build failures.

Change-Id: Ib08f3283e5be956f995a4a416a70b12a32462882
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/17070
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-10-21 19:38:39 +02:00
Elyes HAOUAS de2918bd1a util/inteltool: Remove unnecessary whitespace
Change-Id: Id42a2901cf76e6b867f62a752a38bbd6f6e5f54e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/17059
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-20 20:22:05 +02:00
Elyes HAOUAS 9450150892 util/inteltool: Use tabs for indents
Change-Id: I9d27c276053c51021166f4b22d150060e415d08f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/17025
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2016-10-20 20:21:51 +02:00
Naresh G Solanki 124a368702 kunimitsu: Add choice to select FSP driver
Add choice to select between FSP 1.1 & FSP2.0 driver to be used.

Change-Id: Ied7eab6f4a2191e0bcf220cde5ca519a3c3e2d76
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17051
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-20 20:20:16 +02:00
Wisley Chen 084a343b58 mainboard/google/reef: add snappy variant
Create the initial Snappy variant which refers to the Reef device.

Snappy, an Apollolake-platform, is deviated from reference board Reef.

BRANCH=master
BUG=None
TEST=Built & booted

Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Change-Id: I6f32c0b1a154edbd8c4822acdbdbdbeb4a0098e6
Reviewed-on: https://review.coreboot.org/17043
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-20 20:18:52 +02:00
Patrick Georgi b753eeb7af intel/broadwell: "free" memory after use
While we stub out free(), tools like coverity scan have no idea, and it
might change in the future. So free it.

Change-Id: I1d93a6f45b64445662daa95b51128140ad0a87e2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1260716
Reviewed-on: https://review.coreboot.org/17055
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2016-10-19 21:26:49 +02:00
Arthur Heymans 9c5fc62f96 nb/i945/gma.c: use IS_ENABLED instead of #if, #endif
Change-Id: Ib58126e1c9001ed679e161d6d06241fac762bdb3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17049
Tested-by: build bot (Jenkins)
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-19 17:34:49 +02:00
Naresh G Solanki fe517f635b soc/intel/skylake: Allow selecting FSP driver in Kconfig
Enable mainboard Kconfig to select between FSP 2.0 & 1.1 driver to be
used.

If mainboard Kconfig selects MAINBOARD_USES_FSP2_0 the FSP2_0 driver is
used else FSP1_1.

Change-Id: I724aaa87c2b0b8f6ddb18f61af9c37176ef632f2
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/17044
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-19 17:32:56 +02:00
Elyes HAOUAS 09ec9e74a9 winbond/w83627ehg: Remove unnecessary value
Change-Id: I5f88f34d1c040ac6ed413cfaf8ceb45a358c117c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/17048
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-19 17:31:39 +02:00
Arthur Heymans 8b6df62fc2 nb/i945/raminit: Add fix for clock crossing for 800MHz FSB CPU
The cross clocking of 800MHz FSB CPU with 667MHz RAM was incorrect.
The result is that 800MHz FSB CPUs now properly work with 667MHz RAM.

Value taken from vendor bios on ga-945gcm-s2l and suggested by Haouas
Elyes.

Change-Id: I56c12af50c75a735af0150a4e7bce4faacc93648
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17038
Tested-by: build bot (Jenkins)
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-10-19 17:04:37 +02:00
Arthur Heymans e189761603 nb/i945/raminit: Add fix for 1067MHz FSB CPUs
Previously the 945gc raminit only worked for 533MHz FSB CPUs.

This extends the tRD_Mclks in drt0_table for other FSB speeds. The values are
taken from the vendor bios of Gigabyte ga-945gcm-s2l.

The result is that 1067MHz FSB CPUs now boot without problems.
800MHz FSB cpus still don't get past romstage.

Change-Id: I13a6b97d2e580512155edf66c48405a153121957
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17034
Tested-by: build bot (Jenkins)
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-10-19 17:04:10 +02:00
Elyes HAOUAS 3baa7e7073 util/msrtool: Use tabs for indents
Change-Id: Ib1aa4ad04dc8a584a751677aac5652cfa2e457df
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/17031
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-19 17:02:07 +02:00
Arthur Heymans ff1286d500 nb/gm45,x4x/gma.c remove writes to nonexisting FDI registers
This removes writes to FDI related registers since there is no FDI
link on these targets. This is likely a remainder from copying code from
later targets.

TESTED on Thinkpad x200 (gm45)

Change-Id: Id67fdc999185fa184a9ff0e5c3fc9bced04131ad
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16993
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2016-10-19 17:00:50 +02:00
Arthur Heymans 75f9131453 nb/i945,gm45,x4x/gma.c: fix unsigned arithmetics
This issue was found by Coverity Scan, CID 1364118.

Change-Id: Iba3c0f4f952729d9e0987d928b63ef8b8fe8841e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16992
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2016-10-19 17:00:00 +02:00
Arthur Heymans 063cd5f6ee nb/gm45,x4x/gma.c: Compute p2 in VGA init instead of hardcoding it
According to: "Intel ® 965 Express Chipset Family and Intel ® G35 Express
Chipset Graphics Controller PR" the p2 divisor needs to be 10 when the
dotclock is below 225MHz and 5 when its above 225MHz.

Change-Id: I363039b6fd92051c4be4fdc88788f27527645944
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16991
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-10-19 16:59:34 +02:00
Arthur Heymans f2b8d7cbd6 mb/asus/kcma-d8,kgpe-d16: use MAINBOARD_DO_NATIVE_VGA_INIT
MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG should only occur together with
MAINBOARD_HAS_NATIVE_VGA_INIT. It seems to be used to just have to have
the option to be able to select SEABIOS_VGA_COREBOOT.

This patch makes these boards use MAINBOARD_DO_NATIVE_VGA_INIT and
MAINBOARD_HAS_NATIVE_VGA_INIT to have it select SEABIOS_VGA_COREBOOT
by default when SeaBIOS is chosen.

Change-Id: If0a36af1883a3d62b16a61483733be981a85e5e2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16981
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-10-19 16:55:53 +02:00
Arthur Heymans 31bc716d6b Select SEABIOS_VGA_COREBOOT when native graphic init is selected
Change-Id: I19db898a5e76bf9c151934c7979316fb3737e881
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16965
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-10-19 16:55:27 +02:00
Julius Werner e74f5eaa43 rk3399: display: Use edid_set_framebuffer_bits_per_pixel() helper
This refactoring was already carried into RK3288 with commit 6911219
(edid: Add helper function to calculate bits-per-pixel dependent values)
but it seems that the code for RK3399 was copy&pasted from it too early
to pick this up. Fix that so that future Rockchip SoCs can copy&paste
the right thing.

Change-Id: I5050c58d18db38fffabc7666e67a622d4a828590
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17050
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-10-18 19:52:44 +02:00