Commit Graph

41163 Commits

Author SHA1 Message Date
Raul E Rangel 95b3dc3da9 soc/amd/cezanne: Implement PROVIDES_ROM_SHARING
BUG=none
TEST=Build guybrush and verified with the PPR that the register and bits
are still the same

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0619f84cf82cbb90ded9dfd58afa6acc9520fb8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-29 18:57:28 +00:00
Felix Held f4e90e8a61 soc/amd/common/block/acpimmio/mmio_util: add fch_disable_kb_rst
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Kangheui Won <khwon@chromium.org>
Change-Id: Ie65e39ffb8c353415f5b68e1e0f378d18eeb7498
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51784
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-29 18:57:03 +00:00
Felix Held c1042ba2c5 soc/amd: move PM_RST_CTRL1 register definition to common acpimmio header
TEST=Verified that this register and the defined bits exist in Cezanne,
Picasso, Stoneyridge, Bolton and SB800.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I32d1d577b05edab006981516a5aefd822e7b984a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-29 18:56:36 +00:00
Felix Held 51d6f5cc0a soc/amd/*/gpio: include types.h instead of stdint.h to have size_t
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7a747d4c28e6d449c054ce83966767e13b51a939
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-29 18:47:59 +00:00
Angel Pons e7a68ec05a nb/intel/pineview/raminit.c: Correct clkset1 programming
Reference code does a 32-bit write, and the values don't fit in 16 bits.

Change-Id: I1195c0637b5c215a45328ebae312cf620cd4c950
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51860
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28 18:02:31 +00:00
Angel Pons 7ee1c47cba nb/intel/pineview: Correct HICLKGTCTL write
Reference code uses the `0x06` as an or-mask, which makes more sense.

Change-Id: I04e5262d9ab36ae866fccd90255e4a0f85328e85
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51859
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28 18:02:02 +00:00
Angel Pons 7383318856 nb/intel/pineview: Drop MCHBAR macro from DMIBAR access
While the macro value is the same, the DMIBAR register is not HTBONUS1.

Tested with BUILD_TIMELESS=1, Foxconn D41S remains identical.

Change-Id: I5025f115f5a55dc782092989f3d158802d1d9353
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51858
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28 18:01:26 +00:00
Angel Pons 0cc811789c nb/intel/ironlake/quickpath.c: Correct one value
Commit 56823f53dc (nb/intel/ironlake:
Rewrite early QPI init) rewrote this part, but the or-value is missing
one zero. Correct this magic value to align with MRC binaries.

Change-Id: Id7a6766b3f0fe415dea70cbc54afc30f808c8b16
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51857
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28 18:01:15 +00:00
Angel Pons ca8968dbc1 nb/intel/ironlake: Drop copy-pasted finalisation steps
This was copied from Sandy Bridge and does not apply to Ironlake. These
offsets go past the MCHBAR window (MCHBAR size is 16 KiB on Ironlake).
Some of these writes would have collided with `DEFAULT_HECIBAR` if the
PCI resource had been reported as fixed. Remove the copy-pasted code.

Change-Id: I7688921ad7517cbd68a0c48262b29ecf7b4c396c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51856
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28 18:01:01 +00:00
Angel Pons 7adfe80469 nb/intel/haswell: Replace `DMIBAR64` and `EPBAR64`
While 64-bit writes seem to work properly, there could be unknown
side-effects in some cases, e.g. when running in long mode. Since
reference code uses two 32-bit writes, follow suit.

Change-Id: I48ed3d94c7865b3a3cce52108e99cf1656b57fc2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51855
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28 18:00:49 +00:00
Stanley Wu 498f1285d2 mb/google/dedede/var/boten: Fix DPTF passive and critical policies
Thermal sensor2 defined in baseboard do not exist in boten.
With the format the DPTF policies are defined in boten, all the entries
from the baseboard are included and then the overrides applied.
This causes the non-existent DPTF devices to be exported in the ACPI table
and in turn OS reading invalid temperatures. Fix the format for
DPTF passive and critical policies.

BUG=None
BRANCH=dedede
TEST=Build and boot to OS in boten. Ensure that the DPTF entries look
correct in both static.c and SSDT tables i.e. passive and critical
policies for applicable devices only are present.

Change-Id: I63c781e0a439f1e7a3525fa7cf290fa9300cb066
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Ben Kao <ben.kao@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-03-28 16:08:17 +00:00
Kevin Chiu 800fab86dc mb/google/zork: update stamp_boost parameter for gumboz
Original Stamp_boost parameter will cause boost time over 2500sec(3960sec)
To pass balance performance and skin temperature test, decrease stamp_boost:
2500 -> 1640

BUG=b:182753072
TEST=1. emerge-zork coreboot
     2. run balance performance and skin temperature test

Change-Id: I43c104ef912aafecadf9497f9ea20c8478c0e920
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-03-28 16:08:08 +00:00
Sumeet R Pawnikar 77298c6820 soc/intel/alderlake: add processor power limits control support
Add processor power limits control support to configure values for
alderlake soc based platforms.

BRANCH=None
BUG=None
TEST=Build and test on alderlake rvp board

Change-Id: I9dc37c7a43e6bd6f1ff5e8a97e22a0c7ac421802
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-28 16:08:02 +00:00
Martin Roth 8bd525001f Update amd_blobs submodule to upstream master
Updating from commit id 3a9d7cd:
2021-03-03 15:37:08 -0700 - (picasso: Update Dali SMU firmware)

to commit id dded82f:
2021-03-23 15:36:36 -0600 - (picasso: Update Dali SMU firmware)

This brings in 2 new commits.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: If71e52a2a3e50aeb8599798de7b49bc71ed26a04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-28 16:06:19 +00:00
Matt DeVillier fcb68f31b6 mb/purism/librem_14: Move/fix touchpad interrupt GPIO
On production boards, the touchpad interrupt line was moved
from GPP_B20 to GPP_B3. Fix the GPIO pad config and devicetree entry,
and update documentation to remove touchpad config issue.

Change-Id: Iaefeba8f78c567b67e7a416c27299bff574c23ab
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51797
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28 16:05:57 +00:00
Matt DeVillier 385667f679 documentation: Add documentation for Purism Librem 14
Change-Id: Ic68a3d17534f78dae8c432253982e8d10a6427f0
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-28 16:05:51 +00:00
Tim Wawrzynczak a603e443eb soc/intel/common/gpio: Add function to get GPIO index in group
The gpio_get_index_in_group function returns the index of the GPIO
within its own group

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I7f6b312bd1d0388ef799cd127c88b17bad6a3886
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-28 16:05:02 +00:00
Tim Wawrzynczak 5b90c0f158 soc/intel/common/systemagent: Add macros to access REGBAR space
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I97203aca377d4dd77e03b2c83fdd20a2874cc1c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51755
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28 16:04:54 +00:00
Tim Wawrzynczak e2852579b8 soc/intel/tigerlake: Fix REG_BASE_SIZE
REG_BASE_SIZE is supposed to represent the size of the REGBAR MMIO space
in KiB. It is currently sized at 4MiB, but this is incorrect, EDS Vol. 2
indicates REGBAR is 16MiB in size, therefore update the constant to
reflect this.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I0cfbe5b8bb07faa854efd4bf70640daa117f2bb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-28 16:04:44 +00:00
Tim Wawrzynczak 5de0897671 soc/intel/common/tcss: Rename TCSS_DISPLAY
This name isn't very meaningful, rename the config option to
ENABLE_TCSS_DISPLAY_DETECTION to make its meaning more obvious.

Change-Id: Ib21a3b5a37d25f93bd515f8c6e5ad39c9d2ea1c4
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51771
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28 16:04:33 +00:00
Tim Wawrzynczak eb6ebc025e soc/intel/tigerlake: Move TCSS code to intel/common/block
The Type-C subsystem ("TCSS") IP block is similar between TGL and
ADL. For pre-boot purposes, the limited amount of functionality required
appears to be common between the two, therefore move the functionality
to intel/common/block and rename from `early_tcss to `tcss` along the way.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I1c6bb9c7098691f0c828f9d5ab4bd522515ae966
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51753
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28 16:04:23 +00:00
John Zhao 6edbb18901 ACPI: Add SATC structure for DMAR table
The SoC integrated address translation cache(SATC) reporting structure
is added to Virtualization Technology for Directed I/O specification
Rev3.2. This change adds an ACPI Name-Space Device Declaration structure
SATC which has type 5 reporting structure.

BUG=None
TEST=Built image successfully.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I91d1384083c98b75bcbdddd9cc7b7a26fab25d9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51776
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28 16:03:21 +00:00
lizhi7 56eb876c40 mb/google/dedede/var/blipper: Enable ALC1015 AMP (Auto Mode) driver
Enable gpio mode driver for ALC1015 AMP Auto Mode.

BUG=b:181732574
BRANCH=dedede
TEST=ALC1015Q-VB drive speaker OK

Signed-off-by: lizhi7 <lizhi7@huaqin.corp-partner.google.com>
Change-Id: Idc5b190fc2c30689feaf08229b2a75c69894ac5e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51763
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28 16:03:07 +00:00
lizhi7 40a1d0d0fc mb/google/dedede/var/storo: Enable ALC1015 AMP (Auto Mode) driver
Enable gpio mode driver for ALC1015 AMP Auto Mode.

BUG=b:177868812
BRANCH=dedede
TEST=ALC1015Q-VB drive speaker OK

Signed-off-by: lizhi7 <lizhi7@huaqin.corp-partner.google.com>
Change-Id: Ic7deb9be6444d85d32ff94ce8e4a140dbdea349e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-28 16:03:03 +00:00
Tao Xia fd952aaa50 mb/google/dedede/var/storo: Configure I2C times for I2C devices
Configure I2C high / low time in device tree to ensure I2C
CLK runs accurately at I2C_SPEED_FAST (400 kHz).

Measured I2C frequency just as below after tuning:
touchpad:371.63 kHz
touchpanel:368.24 kHz
audio codec RT5682:369.13 kHz
speaker AMP L:366.21 kHz
speaker AMP R:365.8 kHz
P-sensor:368.34 kHz
MIPI Camera:363.35 kHz

BUG=b:181589325
BRANCH=dedede
TEST=Build and check after tuning I2C clock is under 400kHz

Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: I1a755a54540e106b41ac427f84989ed7e8037558
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51624
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28 16:02:54 +00:00
Felix Held 2fa96eb33e soc/amd/common/gpio: add PAD_NF_SCI pad type
This patch adds a pin configuration macro that supports both switching a
pin to its native function and configuring it as a SCI source. This is a
preparation to remove the GPIO2 soc_gpio_hook.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If0da5c010f35fd902f6b8857368daec93c12394a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50373
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28 16:02:20 +00:00
Kevin Chiu 89d3a2f01e mb/google/zork: update telemetry settings for gumboz
update telemetry to improve the performance.

BUG=b:182753072
BRANCH=zork
TEST=1. emerge-zork coreboot
     2. run AMD SDLE stardust test => pass

Change-Id: I6e4d0c6fcd740d82edf073fb307aa6a6b09ec78a
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51790
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28 16:01:32 +00:00
Matt DeVillier 98ec53bdf1 mb/google/caroline: Re-enable I2C2 / fix digitizer
Caroline has a Wacom W9013 digitizer on I2C2, which was
incorrectly disabled in commit d957d12e6
[mb/google/glados: clean up variant devicetrees]
as part of preparation for converting to overridetree format.

Test: build/boot, verify digitizer now available under Linux

Change-Id: I234bc0126b5d13c22a663d6544382890b312ce63
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-28 16:01:25 +00:00
Maulik V Vaghela 2d22f82a0c mb/intel/adlrvp_m: Enable ADL-M RVP LP5 memory configuration
List of changes:
1. Add correct board Id for ADL-M LP5 configuration
2. Add spd hex files for LP5 Micron part
3. Update memory.c file with correct Dq-dqs and byte mapping for LP5

BUG=None
BRANCH=None
TEST=Build is successful for ADL-M RVP

Change-Id: I0bbd3f5b56bf7fbe918cc599d32a01dcae896ddd
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2021-03-28 16:01:15 +00:00
Maulik V Vaghela fb670fee3c mb/intel/adlrvp_m: Enable ADL_M RVP LP4 memory configuration
List of changes:
1. Add board Ids for ADL-M LP4 configuration
2. Add spd hex files for LP4 configuration
3. Update memory.c file with correct Dq-dqs and byte mapping for LP4

BUG=None
BRANCH=None
TEST=Build and boot is successful for ADL M LP4 RVP

Change-Id: Id817faee3fff2a8a911ebda35774dfb6ddc5524b
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50257
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28 16:01:04 +00:00
Varshit Pandya af53ab38ad mb/intel/adlrvp: Configure GPIOs for ADLRVP-M
List of changes:
1. Add separate file for ADL-M GPIOs
2. Configure GPIOs as per the schematics of ADL-M RVP

TEST=Able to build ADL-M

Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com>
Change-Id: I03a532f69f42db723b976a0f7b0acf6f4b98e354
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2021-03-28 16:00:53 +00:00
Sridhar Siricilla 1ea938ca5e mb/intel/shadowwmountain: Enable CSE Lite SKU for shadowmountain
During the initial phases, the development and validation teams have to
deal with both Consumer SKU and Lite SKU firmware. Having the support for
CSE Lite enabled by default in coreboot helps in integrating both the SKUs.
With this we only have to interchange the CSE region in the full BIOS image
without having to worry about Kconfigs. Eases the build and integration
flow.

TEST=Verified build for Shadowmountain

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I2ebf4da1b8c1df2e9c43b6e3bb688a9f8db652d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51496
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28 16:00:38 +00:00
Sridhar Siricilla d1150fd6d7 mb/intel/adlrvp: Enable CSE Lite SKU
During the initial phases, the development and validation teams have to
deal with both Consumer SKU and Lite SKU firmware. Having the support for
CSE Lite enabled by default in coreboot helps in integrating both the SKUs.
With this we only have to interchange the CSE region in the full BIOS image
without having to worry about Kconfigs. Eases the build and integration
flow.

TEST= Built and booted on ADL-P LP4 RVP

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ia92c7b71c69a23104ace9fc53fd39f01120fa751
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51567
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28 16:00:32 +00:00
Felix Held 5052e1f45c soc/amd/picasso/mca: add missing comma in mca_bank_name array of strings
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Found-by: Coverity CID 1451389
Change-Id: I0af379360fc95e4c6b72d677738c6e7497ed9206
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-28 16:00:13 +00:00
Jakub Czapiga caebcb7014 tests/include/tests/test.h: Add TEST_REGION_UNALLOCATED
Some tested modules require regions to be defined but do not necessarily
access them. TEST_REGION_UNALLOCATED() combined with DECLARE_REGION()
are sufficient for most cases that require symbols only.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I51c5f6ce56575021c6e4277a9ed17263cd2e3bb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51769
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28 16:00:01 +00:00
Seunghwan Kim 265fad562f mb/google/dedede/var/sasuke: Add support zinitix touchpad
This change adds support zinitix touchpad for sasuke.

BRANCH=dedede
BUG=None
TEST=built and checked touchpad worked on sasuke

Change-Id: I85794311c49e33c4683482e125bea5ca2dbacfa8
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-28 15:59:50 +00:00
Kevin Chiu fb796034da grunt/barla: add Realtek ALC5682 codec support
ALC5682 i2c address: 0x1A

BUG=b:171755306
BRANCH=master
TEST=emerge-grunt coreboot

Change-Id: I8bc571104bebe02acf86507774580effc808beb6
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-28 15:59:37 +00:00
Arthur Heymans 0514324724 security/intel/cbnt: Generate KM from Kconfig symbols
Add an option to generate the Key Manifest from Kconfig options.

Change-Id: I3a448f37c81148625c7879dcb64da4d517567067
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50410
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28 15:56:49 +00:00
Arthur Heymans 2ef2e4793a security/intel/cbnt: Add option to generate KM
This add an option to generate KM using the 9elements bg-prov tool
using a json config file.

The option to just include a provided KM binary is kept.

A template for the json config file can be obtained via
"bg-prov template".
Another option is to extract it from a working configuration:
"bg-prov read-config".

Change-Id: I18bbdd13047be634b8ee280a6b902096a65836e4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50409
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28 15:56:24 +00:00
Arthur Heymans 21176ddd57 security/intel/cbnt: Prepare for KM/BPM generation
Private and/or public keys will be provided as user input via Kconfig.
As a private key also contains the public key, only ask what is required.

Change-Id: I86d129bb1d13d833a26281defad2a1cb5bf86595
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2021-03-28 15:56:11 +00:00
Jitao Shi 6482b16c7f mb/google/kukui: fine tune the data lane trail
ANX7625 requires customized hs_da_trail time.
So override the data trail for ANX7625.

BUG=b:173603645
BRANCH=kukui
TEST=Display is normal on Jacuzzi

Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Change-Id: I620035363507daaa19e3c272a44059c17be29af1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@chromium.org>
2021-03-28 15:55:48 +00:00
Angel Pons c57cae8c8b soc/amd/common/block/i2c: Use `size_t` for `num_pins`
There's no need to use a fixed-width type here.

Change-Id: I727c64661990040db356c5508fecc0a65960c095
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51794
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28 14:11:38 +00:00
Angel Pons cf72a51abf soc/amd/common/block/i2c: Fix printf format specifiers
The correct printf format specifier for an `unsigned int` is `%u`.

Change-Id: Iaf780eb366f8c3493b89beb9a5643fa285e7825d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51793
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28 14:11:28 +00:00
Nico Huber 10a879e65b Makefile.inc: Use `additional-dirs` for $(objcbfs), $(objgenerated)
We use `additional-dirs` for a single `mkdir -p` invocation for all
directiories. I don't see why these two, $(objcbfs) and $(objgenerated),
should be an exception.

Fixes clean builds for targets that don't include the phony `coreboot`
target, e.g. `make qemu`.

Change-Id: I85abaa74cddefd2bd669e2b5c8934352775070fe
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-27 19:34:58 +00:00
Angel Pons 84ec70312e mb/intel/dcp847ske: Drop useless MCHBAR writes
There's no need to write the GDCRTRAININGRESULT registers after raminit.

Change-Id: If604920fe7a3bee96f72f8aff5e96f0e25548f18
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50534
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-27 18:36:05 +00:00
Jitao Shi 927fa6d04c soc/mediatek: Adjust hsa, hbp, hfp packets for MIPI_DSI_MODE_LINE_END
ANX7625 requires the line packets to end at the same time.
Otherwise, the display will be shifted.

BUG=b:173603645
BRANCH=kukui
TEST=Display is normal on Jacuzzi

Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Change-Id: I5949de1a9a1947fa188233787166a478b1de68b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-03-27 10:03:41 +00:00
Jitao Shi 7de5677643 drivers/analogix: Increase the clock tolerance from 0.1% to 2%
Increase the input tolerance to avoid panel scroll.

BUG=b:173603645
BRANCH=kukui
TEST=None

Change-Id: I4af96f58876932175b28fc0a8543720ebd7b5deb
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39025
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-27 10:02:18 +00:00
Subrata Banik f9650771d3 mb/intel/adlrvp: Allow GPIO PM override to disable dynamic GPIO PM
This patch allows overriding GPIO PM miscconfig register for each
GPIO community to avoid dynamic clock gating.

TEST=Dump GPIO Community MISCCFG register to ensure all Bit [7:0]
are set to '0'.

Change-Id: I9aca9cb0641e2731c028ea5ed76c563da3400b74
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-27 04:23:31 +00:00
Subrata Banik 2ccc0a4d9f soc/intel: Rename and move MISCCFG_GPIO_PM_CONFIG_BITS definition to soc/gpio.h
Lists of changes:
1. Rename MISCCFG_ENABLE_GPIO_PM_CONFIG -> MISCCFG_GPIO_PM_CONFIG_BITS
2. Move MISCCFG_GPIO_PM_CONFIG_BITS definition from intelblock/gpio.h to
soc/gpio.h. Refer to detailed description below to understand the
motivation behind this change.

An advanced GPIO PM capabilities has been introduced since CNP PCH,
refer to 'include/intelblock/gpio.h' for detailed GPIO PM bit definitions.

Now with TGP PCH, additional bits are defined in the MISCCFG register
for GPIO PM control. This results in different SoCs supporting
different number of bits. The bits defined in earlier platforms
(CNL, CML, ICL) are present on TGL, JSL and ADL too. Hence, refactor the
common GPIO code to keep the bit definitions in intelblock/gpio.h, but
the definition of MISCCFG_GPIO_PM_CONFIG_BITS is moved to soc/gpio.h so
that each SoC can provide this as per hardware support.

TEST=On ADL, TGL and JSL platform.
Without this CL :
GPIO COMM 0 MISCCFG:0xC0 (Bit 6 and 7 enable)

With this CL :
GPIO COMM 0 MISCCFG: 0x00 (Bit 6 and 7 disable)

Change-Id: Ie027cbd7b99b39752941384339a34f8995c10c94
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-27 04:23:12 +00:00
Subrata Banik 299ee183c4 soc/intel/common/block/gpio: Fix typecasting issue
This patch fixes unsigned conversion from 'int' to 'uint8_t'
{aka 'const unsigned char'} changes value from '-256' to '0'
[-Werror=overflow].

Change-Id: Ifcc42e5a2ff06f0af0eb96bef4c6044cbcdbd94b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-27 04:22:31 +00:00