The Deep S3 state will lose a lot of register contents that we
used to rely on for determining wake source.
In order to make use of this override the enable bit for wake
sources that are enabled for Deep S3 in devicetree.cb.
BUG=chrome-os-partner:58666
TEST=check for _SWS reporting wake source on S3 resume on skylake
Change-Id: If5113d6890f6cbecc32f92af67a29952266fe0ac
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17137
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Remove the FADT from the individual mainboards and select and
use COMMON_FADT in the SOC instead. Set the ACPI revision to 5.
Change-Id: Ieb87c467c71bc125f80c7d941486c2fbc9cd4020
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17138
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Those registers are only used on more recent Intel platforms featuring a
PCH. The DP registers on G4X hardware are at a different offset.
Change-Id: I4660e547426ccec0b2095d897e4a8c86e0acf41e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17111
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Those registers are only used on more recent Intel platforms featuring a
PCH. The DP registers on G4X hardware are at a different offset.
Change-Id: Ib49e54d4e7d6595dc09fb1be35ac8178b80c7f71
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17110
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Also drop an odd comment about the resource allocator which seems to
work fine, with the right id.
Change-Id: I9099211fe946c28f90dd7730345b81a3f7f6f545
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/17095
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Three things are required to enable wake-on-usb:
1. 5V to USB ports should be enabled in S3.
2. ASL file needs to have appropriate wake bit set.
3. XHCI controller should have the wake on attach/detach bit set for the
corresponding port in PORTSCN register.
Only part missing was #3.
This CL adds support to allow mainboard to define a bitmap in
devicetree corresponding to the ports that it wants to enable
wake-on-usb feature. Based on the bitmap, wake on attach/detach bits in
PORTSCN would be set by xhci.asl for the appropriate ports.
BUG=chrome-os-partner:58734
BRANCH=None
TEST=Verified that with port 5 enabled, chell wakes up from S3 on usb
attach/detach.
Change-Id: I40a22a450e52f74a0ab93ebb8170555d834ebdaf
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17056
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use intel common infrastructure to enable support for write-protecting
SPI flash range. Also, enable this protection for RW_MRC_CACHE.
BUG=chrome-os-partner:58896
TEST=Verified that write to RW_MRC_CACHE fails in OS using
"flashrom -p host -i RW_MRC_CACHE -w /tmp/test.bin"
Change-Id: I35df12bc295d141e314ec2cb092d904842432394
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17117
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Write-protect SPI flash range provided by caller by using a free Flash
Protected Range (FPR) register. This expects SoC to define a callback
for providing information about the first FPR register address and
maximum number of FPRs supported.
BUG=chrome-os-partner:58896
Change-Id: I4e34ede8784e5587a5e08ffa10e20d2d14e20add
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17115
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
According to: "Intel ® 4 Series Chipset Family datasheet"
the IGD only has 1 IRQ pin.
Change-Id: I974f002f5a213056f4593a1eab10772527bb241d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17098
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This fixes an instability on 945gc where the IGD completely locks
up the system, when for instance tasked to do something with
compositing (like GNOME or GDM).
TESTED on ga-945gcm-s2l and d945gclf
TEST: launch GDM (gnome display manager)
Change-Id: Iec49bccf3e3164df9dc1e0b54460a616fe92e04d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17094
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
Add support for Kaby Lake RVP3.
Use kunimitsu at commit 028200f as base.
Kabylake RVP3 is based on Kabylake-Y with onboard Dual Channel
LPDDR3 DIMM.
* Update board name to kblrvp
* Remove fsp 1.1 specific code( As Kabylake uses fsp2.0)
* Remove board id function.
* Remove unused spd & add rvp3 spd file.
This is an initial commit does not have full support to boot.
Will add more CLs to boot Chrome OS with depthcharge.
Change-Id: Id8e32c5b93fc32ba84278c5c5da8f8e30c201bea
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17032
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
CQ-DEPEND=CL:379684
BUG=chrome-os-partner:58064
TEST=verified on hana rev0
Change-Id: Icd076dcaf07a97f3b83b428b9619e8a4dafe744d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7c483951a0dcd419735fffb79e6187f9ca3b08a8
Original-Change-Id: I9d886abf15931496ac61e8fd38d7fd306f2a1bf7
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/379504
Original-Commit-Ready: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Philip Chen <philipchen@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17107
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
There are some sdram configurations that are no longer used. Drop them.
BUG=None
BRANCH=None
TEST=None
Change-Id: Ib6d2d58c3071147a3095bc1ed7fa7b02c748e1a5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 111d375005ec6a3b91e47acdd676e8f1644c931c
Original-Change-Id: I5f9278093f02e785b2894faa8e8cf09ecec20325
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/399122
Original-Commit-Ready: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17103
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
We found sdram may fail in pctl_cfg(), so we check the status in this
function. If it exceeds 100ms still in this function, we will restart
the system. We also found there are rare chances DDR training fails,
so also restart system in that case.
BUG=chrome-os-partner:57988
BRANCH=None
TEST=coreboot resets on failure and eventually the system comes up
Change-Id: Icc0688da028a8f4f81eafe36bbaa79fdf2bcea74
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 89e45f8352f62e19a203316330aba14ccc5c8b11
Original-Change-Id: If4e78983abcfdfe1e0e26847448d86169e598700
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/397439
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17045
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
It's a better default than QEMU-armv7, which is currently the default
board when coreboot is configured for the first time, because most
coreboot development targets x86.
With this patch, the minimal steps to coreboot+SeaBIOS booting in QEMU
become:
git clone https://review.coreboot.org/coreboot.git && cd coreboot
make crossgcc-x86
make olddefconfig && make
qemu-system-x86_64 -bios build/coreboot.rom
Change-Id: Ie44a5d95547a55df93f29082c3b5a86fb83aa1e7
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16987
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Currently, the only supported DSM type is I2C
HID(3CDFF6F7-4267-4555-AD05-B30A3D8938DE). This provides the required
callbacks for generating ACPI AML codes for different function
identifiers for I2C HID.
BUG=chrome-os-partner:57846
Change-Id: Ia403e11f7ce4824956e3c879547ec927478db7b1
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17091
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add acpigen_write_dsm that generates ACPI AML code for _DSM
method. Caller should provide set of callbacks with callback[i]
corresponding to function index i of DSM method. Local0 and Local1
should not be used in any of the callbacks.
BUG=chrome-os-partner:57846
Change-Id: Ie18cba080424488fe00cc626ea50aa92c1dbb199
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17090
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
1. Export i2c_generic_fill_ssdt to allow other device-specific i2c
drivers to share and re-use the same code for generating AML code for
SSDT. In order to achieve this, following changes are required:
a. Add macro I2C_GENERIC_CONFIG that defines a structure with all
generic i2c device-tree properties. This macro should be placed by the
using driver at the start of its config structure.
b. Accept a callback function to add any device specific information to
SSDT. If generic driver is used directly by a device, callback would be
NULL. Other devices using a separate i2c driver can provide a callback
to add any properties to SSDT.
2. Allow device to provide _CID.
BUG=chrome-os-partner:57846
Change-Id: I3a0054e22b81f9d6d407bef417eae5e9edc04ee4
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17089
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Define reset_gpio and enable_gpio for touchscreen device so that when
kernel puts this device into D3, we put the device into
reset. PowerResource _ON and _OFF routines are used to put the device
into D0 and D3 states.
BUG=chrome-os-partner:55988
Change-Id: Ia905f9eb630cd96767b639aec74131dbd7952d0e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17083
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Implement GPIO ACPI AML generating functions that can be called by
coreboot drivers to generate GPIO manipulation code in AML. Following
functions are implemented:
1. acpigen_soc_read_rx_gpio
2. acpigen_soc_get_tx_gpio
3. acpigen_soc_set_tx_gpio
4. acpigen_soc_clear_tx_gpio
BUG=chrome-os-partner:55988
Change-Id: I3d8695d73a1c43555032de90f14ee47ccee45559
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17082
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Add support to allow a device to define PowerResource in its SSDT AML
code. PowerResouce ACPI generation expects SoC to define the
callbacks for generating AML code for GPIO manipulation.
Device requiring PowerResource needs to define following parameters:
1. Reset GPIO - Optional, GPIO to put device into reset or take it out
of reset.
2. Reset delay - Delay after reset GPIO is de-asserted (default 0).
3. Enable GPIO - Optional, GPIO to enabled device.
4. Enable delay - Delay after enable GPIO is asserted (default 0).
BUG=chrome-os-partner:55988
Change-Id: Ieb2dd95fc1f555f5de66f3dda425172ac5b75dad
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17081
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
This version of coreboot successfully starts a Harvey (Plan 9) kernel as a payload,
entering main() with no supporting assembly code for startup. The Harvey port
is not complete so it just panics but ... it gets started.
We provide a standard payload function that takes a pointer argument
and makes the jump from machine to supervisor mode;
the days of kernels running in machine mode are over.
We do some small tweaks to the virtual memory code. We temporarily
disable two functions that won't work on some targets as register
numbers changed between 1.7 and 1.9. Once lowrisc catches up
we'll reenable them.
We add the PAGETABLES to the memlayout.ld and use _pagetables in the virtual
memory setup code.
We now use the _stack and _estack from memlayout so we know where things are.
As time goes on maybe we can kill all the magic numbers.
Change-Id: I6caadfa9627fa35e31580492be01d4af908d31d9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/17058
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Since reading/toggling of GPIOs is platform-dependent task, provide an
interface with common functions to generate ACPI AML code for
manipulating GPIOs:
1. acpigen_soc_read_rx_gpio
2. acpigen_soc_get_tx_gpio
3. acpigen_soc_set_tx_gpio
4. acpigen_soc_clear_tx_gpio
Provide weak implementations of above functions. These functions are
expected to be implemented by every SoC that uses ACPI. This allows
drivers to easily generate ACPI AML code to interact GPIOs.
BUG=chrome-os-partner:55988
Change-Id: I3564f15a1cb50e6ca6132638447529648589aa0e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17080
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add functions to support generation of following AML operations:
1. PowerResource
2. Store
3. Or
4. And
5. Not
6. Debug
7. If
8. Else
9. Serialized method
BUG=chrome-os-partner:55988
Change-Id: I606736b38e6a55ffdc3e814b6ae0fa367ef7595b
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17079
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Instead of using hard-coded values for emitting op codes and prefix
codes, define and use enum constants. With this change, it becomes
easier to read the code as well.
BUG=chrome-os-partner:55988
Change-Id: I6671b84c2769a8d9b1f210642f3f8fd3d902cca2
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17078
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This patch adds a Makefile rule for mvmap2315 to install a BDB and
bootblock code in the BOOTBLOCK region. The resulting BDB has a
header and data both signed by a RSA-4096 key.
BUG=chrome-os-partner:57889
BRANCH=none
TEST=emerge-rotor coreboot and examined the output binary. Booted
coreboot.rom.
Change-Id: I1e20a09b12f8f8ed4d095aa588e3eb930f359fc5
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/16747
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
While we stub out free(), tools like coverity scan have no idea, and it
might change in the future. So free it.
Change-Id: I1d93a6f45b64445662daa95b51128140ad0a87e2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1260716
Reviewed-on: https://review.coreboot.org/17055
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
The cross clocking of 800MHz FSB CPU with 667MHz RAM was incorrect.
The result is that 800MHz FSB CPUs now properly work with 667MHz RAM.
Value taken from vendor bios on ga-945gcm-s2l and suggested by Haouas
Elyes.
Change-Id: I56c12af50c75a735af0150a4e7bce4faacc93648
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17038
Tested-by: build bot (Jenkins)
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Previously the 945gc raminit only worked for 533MHz FSB CPUs.
This extends the tRD_Mclks in drt0_table for other FSB speeds. The values are
taken from the vendor bios of Gigabyte ga-945gcm-s2l.
The result is that 1067MHz FSB CPUs now boot without problems.
800MHz FSB cpus still don't get past romstage.
Change-Id: I13a6b97d2e580512155edf66c48405a153121957
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17034
Tested-by: build bot (Jenkins)
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Duncan Laurie