Commit Graph

37831 Commits

Author SHA1 Message Date
Felix Held 407b866a3e mb/amd: Add Pollock CRB Cereme as Mandolin variant
Even though the devicetrees of Mandolin and Cereme are relatively
similar, they are kept as separate files instead of using devicetree
overrides to facilitate creating mainboard ports based on those CRBs.
The two boards are reference boards for different zen/zen+ APU platforms
that share the silicon, but use different packages. This is also
consistent with the google/zork boards that have two different full base
devicetrees for the two different platforms and then use devicetree
overrides for the different variants of the two reference designs.

BUG=b:159617786,b:169644059
BRANCH=zork

Change-Id: Ief8a05b0a360563d26a81941720b78014feb0d25
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42786
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-30 22:24:31 +00:00
Felix Held 4ae3e41deb 3rdparty/blobs: advance submodule pointer
This pulls in the following changes:
* soc/intel/baytrail/microcode.bin: Remove outdated microcode
* mainboard/amd/mandolin: add Cereme APCB

Change-Id: If6dd7881b346782635dec07710fe5c4449254e3c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45851
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-30 21:45:06 +00:00
Felix Held 6646cb0972 mb/amd/mandolin: change EFS SPI mode from 1-4-4 to 1-1-4
With this change the flash addresses will only get transferred over one
data pin like in the non-quad SPI mode and only the data will get sent
over all four data pins. Since this gives the flash chip a bit more time
to fetch the data the host requested, this allows higher SPI frequencies
resulting in a higher throughput when bigger chunks of memory get read.

BRANCH=zork

Change-Id: Iad4c922ffcdba4b17e6e81244ff37302eb171d97
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45831
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-30 21:38:53 +00:00
Felix Held e310c7747a mb/amd/mandolin: add missing SPI configuration to devicetree
This fixes the board not booting reliably when running from flash
without the EM100 option selected during build time. Selecting EM100
mode overrides the settings, so when testing with an EM100 I didn't run
into this issue.

BUG=b:169644059
BRANCH=zork

Change-Id: I2c7043c174dcf4501776a03b7689d8a20c214afb
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45830
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-30 21:38:09 +00:00
Martin Roth 60d89e287d soc/amd/picasso: Add fields for the PSP to the transfer struct
The PSP will be adding information into these fields after verstage
runs.  This allows data to be passed directly to coreboot very early
in the boot process.

BUG=b:168895748
TEST=None
Branch=Zork

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Idbd1dfece59e99f6f15dfd8d002529ea6417cdbe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-30 19:23:14 +00:00
Jamie Ryu 8053595370 mb/google/volteer: Update SLP_Sx assertion widths and PwrCycDur
This patch updates the SLP_Sx assertion widths and power cycle duration
for volteer.

Power cycle duration:
With default value,
     S0->S5 -> [ ~4.2 seconds delay ] -> S5->S0

With value set to 1,
     S0->S5 -> [ ~1.2 seconds delay ] -> S5->S0

BUG=b:159108661
TEST=Verified that the power cycle duration is 1~2s with a global reset
on volteer.

Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: Idf4e0c3a60b4ac59e31df1357f2ff28f195ff17f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
2020-09-30 15:27:18 +00:00
Eugene D Myers 075df92298 security/intel/stm: Fix size_t printf format error
Size_t seems to have a compiler dependency.  When building on the
Purism librem 15v4, size_t is 'unsigned long'.  In this instance,
the compiler is the coreboot configured cross-compiler.  In another
instance, size_t is defined as 'unsigned short'.  To get around
the formatting conflict caused by this, The variable of type
size_t was cast as 'unsigned int' in the format.

Change-Id: Id51730c883d8fb9e87183121deb49f5fdda0114e
Signed-off-by: Eugene D Myers <cedarhouse@comcast.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
2020-09-30 10:17:19 +00:00
Eugene D Myers 61a77d6fcc 3rdparty: Add STM as a submodule
The patch incorporates the STM build as a part of the coreboot
build.  A separate patch lists and documents the options that
the developer can use.  In most cases the default options will
suffice.

Change-Id: I8c6e0c85edd4e2b0658791553bd9947656e8c796
Signed-off-by: Eugene D Myers <cedarhouse@comcast.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
2020-09-30 10:17:03 +00:00
Jeremy Compostella 612ae2ec7c libpayload: use PRIu64 type to print u64
The appropriate way to print a u64 variable regardless of the current
architecture is to use the PRI*64 macros.  libpayload is mostly used
in 32 bits but when ported to other projects and compiled in 64 bits
it breaks the compilation.

Change-Id: I479fd701f992701584d77d43c5cd5910f5ab7633
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-09-30 10:16:44 +00:00
Pratik Prajapati 05ea79cf53 soc/intel/tigerlake: Set TME upd param based on config
Set TmeEnable FSP-M upd based on config.

TEST: TME ENABLE and LOCK bits get set when Tme is enabled.

Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Change-Id: Ia804c88057e17844f055fd852fc0b36cfe316432
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-09-30 10:16:05 +00:00
Maxim Polyakov 3554888f25 mb/51nb/x210/gpio: Remove comments that contain pad functions
Remove these comments, because they do not contain useful information
that helps to understand the circuit, which we do not have.

Change-Id: I8a994a6f27d830bd05819043336d12c2ecef2f48
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45371
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-30 10:15:14 +00:00
Maxim Polyakov e5b9dda758 mb/51nb/x210/gpio: 4/4 Convert field macros to PAD_CFG
Converts bit fields macros to target PAD_CFG_*() macros. To do this,
the following command was used:

./intelp2m -n -t 1 -file ../../src/mainboard/51nb/x210/gpio.h

This is part of the patch set
"mb/51nb/x210/gpio: Rewrite pad config using intelp2m":

CB:43566 - 1/4 Decode raw register values
CB:43567 - 2/4 Exclude fields for PAD_CFG
CB:43568 - 3/4 Fixes PAD_RESET to convert to PAD_NC()
CB:43410 - 4/4 Convert field macros to PAD_CFG

Tested with BUILD_TIMELESS=1, 51NB-X210, remains identical.

Change-Id: I18c0c321561eee04ff927681b0a231f6d79c63e2
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-30 10:15:03 +00:00
Nico Huber d09064e432 drivers/pc80/rtc: Fix linking verstage (and use `all` target)
`option.c` was already linked into verstage but needs `mc146818rtc.c`
to work. While we are at it, also make use of the `all` target.

Change-Id: I8f545e036962ed0716bcd3b9a5b5d06e18a367f6
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45802
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-30 10:14:23 +00:00
Angel Pons 1a43de16bb soc/intel/icelake/acpi/gpio.asl: Correct GADD method
Some cases are inconsistent. Refer to the 495 series on-package PCH to
confirm which GPIO pads are the first for each community and fix it.

Change-Id: Ie4c4c12c6629478d754f55fa3fb75fa16eb01335
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-09-30 10:14:07 +00:00
Iru Cai 871f62c376 lenovo/t440p: Add HDA verbs from the OEM firmware
To get the HDA verbs from the OEM firmware, open the firmware with
UEFITool, search for the existing HDA verbs, extract the UEFI module
and look for the verbs. Copy the consecutive 4 dword sets that look
like HDA verbs.

It is tested to make audio output from both the speaker and headphone
work.

Change-Id: Ie359fdf6785b1c0be8dc201cd76176c0a7fe7942
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-30 10:13:48 +00:00
Elyes HAOUAS fbdab90b57 mb/packardbell/ms2290/acpi: Convert 'battery.asl' to ASL 2.0 syntax
Change-Id: Id8b7d3776ab2cc8c487095273582cd013241bd3a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-30 10:13:17 +00:00
Elyes HAOUAS e6174d3e28 mb/packardbell/ms2290/acpi/battery.asl: Remove unused remainder
We store the remainder in Local0, but we never use it.

Change-Id: I4d209d7434508cb626aca8e7df50cc1c424e294a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-30 10:13:08 +00:00
Subrata Banik 7335225600 soc/intel/skylake: Move PMC MMIO offset macro into pmc.h
This patch ensures PMC offset 0xfc resides into pmc.h rather defining
into p2sb.h.

Change-Id: Iae1c38beae15355a077be80112b723b8ad3d0a44
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45800
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-30 03:54:29 +00:00
Subrata Banik 063e933194 soc/intel/skylake: Align PMC offset 0x31C name with CNL
As per EDS PMC BASE Offset 0x31C is known as CPPMVRIC hence rename
CIR31C with CPPMVRIC.

Change-Id: Idaff62fb742e6c58b1d8e662b5e4087fa2da79a3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45795
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-30 03:53:42 +00:00
Subrata Banik e37e668e5a soc/intel/skylake: Align soc_pch_pirq_init() with CNL
This patch replaces pch_interrupt_routing[] with PCH_IRQx macro.

Change-Id: I9645b0e185bcde7b27da35863564dbcf73850e8c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45788
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-30 03:52:23 +00:00
Subrata Banik 02d5faa992 soc/intel/apollolake: Add PCH_IRQx into irq.h
This patch is needed to make use of LPC common code.

Change-Id: I5d0e8dbf8f8e52caf4ba78c0e3969efaac387204
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-30 03:52:08 +00:00
David Wu 006acd3c28 mb/google/puff: Update DPTF parameters for faffy
1. TSRO trip point from 75C change to 73C
2. Sample period time from 5s change to 60s

BUG=b:160385395
BRANCH=puff
TEST=build and verify by thermal team

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I0b000841845ce793be0e52fc28a07ac6a931ef7a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-09-30 02:22:12 +00:00
Daniel Kang 029069960e mb/google/volteer: Change default camera power GPIO to 0
The default GPIO values for camera power were set as 1 so the LED was
turned on by default when the board is powered on.
This status is kept until the camera is probed then being turned off.
So the LED is turned on for a few seconds during the boot up.

By setting the default power to 0, the LED is lit only when camera
is turned on for probing and this should be just a blink.

BUG=b:167635396
BRANCH=none
TEST=Build and boot volteer board. Monitor camera privacy LED
and check it is not lit more than 0.5 seconds.

Signed-off-by: Daniel Kang <daniel.h.kang@intel.com>
Change-Id: Ic7df391aa512daafe6e1ce49e9222b90e17ad806
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45058
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-29 23:09:49 +00:00
Frank Wu 9f963d3325 mb/google/volteer/halvor: Update settings for audio function
Configure overridetree settings for audio function.

BUG=b:153680359, b:163382106
TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I107f6fc21b99d80d69931139dc50e7d5873a8e52
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-09-29 18:31:33 +00:00
Daniel Kang b4b8c1d174 mb/google/volteer: Add "i2c-allow-low-power-probe" property for
cameras

There is a patch https://lkml.org/lkml/2020/9/3/235 which allows i2c
device can support driver probe without power up the device.
In order to support this, need add coreboot add
"i2c-allow-low-power-probe" property.

BUG=b:169058784
BRANCH=none
TEST=Build and boot volteer board. Monitor camera privacy LED
and check it blinks. It should not blink.

Signed-off-by: Daniel Kang <daniel.h.kang@intel.com>
Change-Id: I46f90ff8d412b18c7ee4bd7f22f9a7db771eb84f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-09-29 17:18:27 +00:00
Patrick Rudolph dc2f0e39ae cpu/qemu-x86/car: Move long mode entry right before c entry
This fixes non-emulation platforms as those are using 32bit code
after the bootblock_crt0 entry, like setting up CAR and updating
microcode, which isn't yet converted to support long mode.

This is a noop for the only supported x86_64 platform and all
x86_32 platforms.

Change-Id: I45e56ed8db9a44c00cd61e962bb82f27926eb23f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-29 12:27:04 +00:00
Krishna Prasad Bhat 20f580b6f9 soc/intel/jasperlake: Add IGD, MCH Device ID
Add IGD Device ID and MCH Device ID for Jasperlake.
Reference is taken from Jasperlake EDS volume 1(Document Number:
613601).

TEST=Build and boot Jasperlake platform.

Change-Id: I00ee7950ffa378b428a76bf367a9a05ab287e7ed
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-09-29 06:52:40 +00:00
Michael Niewöhner 8e60571f6e mb/clevo/cml-u: drop PcieRpSlotImplemented for card reader
PcieRpSlotImplemented should only be set to 1 for PCIe ports
implementing a PCIe slot. Drop it for the on-board card reader.

Change-Id: I22628b4d4a7e317a01e46a61b5cd7bb9ebf548a0
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-29 06:01:34 +00:00
Angel Pons c88a4794c8 nb/intel/gm45: Answer question about conversion stepping A1
The datasheet briefly mentions what this mysterious stepping is about.

Change-Id: I5bc1040b74fcdf3822b15e7564f8e4ccebd7d45f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45449
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-29 06:00:49 +00:00
Arthur Heymans 2f7d4c362c cpu/x86/smm/smihandler.c: Implement smm_get_save_state()
This will be used in common save_state handling code.

Change-Id: I4cb3180ec565cee931606e8a8f55b78fdb8932ae
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44320
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-29 05:59:59 +00:00
Arthur Heymans ac0d2ee2de cpu/x86/smm/smmhandler.c: Get revision using C code
This allows to remove some assembly code.

Tested with QEMU Q35 to still print the revision correctly.

Change-Id: I36fb0e8bb1f46806b11ef8102ce74c0d10fd3927
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-29 05:59:37 +00:00
Maulik V Vaghela 258ceb7507 mb/intel/jslrvp: Update PMC as hidden device
This change allows treating the PMC as a 'hidden' PCI device on
JasperLake, so that the MMIO & I/O resources can be exposed as
belonging to this device, instead of the system agent and LPC/eSPI.

Original patch for jasperlake SoC here:
CB:42018

This change was missing for JasperLake rvp board.

TEST=Checked PMC init function is called and also checked PCI resource
for PMC device 1f.2.

Change-Id: I7531d32c62d3f9735938f744f2892ab9c9bebddf
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-09-29 03:48:27 +00:00
Pratik Prajapati 823e73e143 soc/intel/common: Add config option to enable TME/MKTME
Add config option to enable TME/MKTME.
The spec is available at: "https://software.intel.com/sites/
default/files/managed/a5/16/Multi-Key-Total-Memory-Encryption-
Spec.pdf"

Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Change-Id: I181aed2bf4a79005fe42e3e133b5faee91201dad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-09-29 03:47:38 +00:00
Maxim Polyakov c65f1f95dc util/intelp2m/apl: Remove unused plat-spec function
Change-Id: I42074387a08b66b038ad2939f31be263eaa3af0e
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44473
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-28 15:44:23 +00:00
Maxim Polyakov be96c62b1e mb/google/fizz/endeavour/gpio: Reflow long lines
Use the 96 character limit.

Change-Id: I865288051869e50602a579a6999b1b23ef68ec2f
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-28 15:44:04 +00:00
Subrata Banik ac17fad84e Revert "soc/intel/xeon_sp: Improve performance efficiencies"
This reverts commit d51449d017.

Reason for revert: Causing compilation issue as below

src/soc/intel/xeon_sp/cpx/acpi.c: In function 'acpi_create_rhsa':
src/soc/intel/xeon_sp/cpx/acpi.c:825:4: error: initialization
discards 'const' qualifier from pointer target type
[-Werror=discarded-qualifiers]
    &hob->PlatformData.IIO_resource[socket];
    ^
Change-Id: I7050060f1db7b9a9b5a77b5a6245c8fda05623a4
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44998
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-28 14:28:22 +00:00
Tom Hiller 9e7c99dcae Intel GBE 82579LM bincfg set and spec
Using bincfg, generate Intel 82579LM GBE region firmware.

* Intel 82579LM is used in Lenovo models including x220 and x230.
* PXE is disabled.
* Intel 82579V variant could be generated with a few modifications to
set.  Noted in set file comments.

Change-Id: I377cbe2f77f2aef39f452dc6511a0ea6b2015963
Signed-off-by: Tom Hiller <thrilleratplay@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-09-28 09:44:45 +00:00
Maxim Polyakov fd76c5e540 util/intelp2m: Remove unnecessary tabs
Change-Id: I5aa4b9ac4fa1ceb6f3c2ade214d47b29246ece55
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-28 09:42:24 +00:00
Eric Lai 5f43369bec mb/google/octopus/variants/fleex: Only do LTE power off for LTE sku
Only do LTE power off for LTE sku in order to save extra 130ms delay
for non-LTE sku.

BUG=b:168075958
BRANCH=octopus
TEST=build image and verify on the DUT with LTE DB.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: If983185ff2f09fb1b2553c6ff1a1473d3254de4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
2020-09-28 09:41:55 +00:00
Elyes HAOUAS 40ed6f2f78 mb/clevo/cml-u/Kconfig: Remove MAINBOARD_SMBIOS_PRODUCT_NAME
MAINBOARD_SMBIOS_PRODUCT_NAME is duplicated.

Change-Id: I011f83c4d4e0657256839db207bfd1517922744c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-28 09:41:04 +00:00
Raul E Rangel 96c704a167 soc/amd/picasso: Set eMMC preset UPDs
Now that all boards have bootable driver strengths and init frequency,
we can pass them to FSP.

BUG=b:159823235
TEST=Boot ezkinil to kernel and print presets.

SDHC0x8F0 Initialization 3.3V or 1.8V => 0x03ff
 14 => 0 [B]: DvrStrength
 10 => 0: ClkGen
 00 => 0x3ff: SdClkFreq
SDHC0x8F2 Default Speed 3.3V => 0x0004
 14 => 0 [B]: DvrStrength
 10 => 0: ClkGen
 00 => 0x4: SdClkFreq
SDHC0x8F4 High Speed 3.3V => 0x0002
 14 => 0 [B]: DvrStrength
 10 => 0: ClkGen
 00 => 0x2: SdClkFreq
SDHC0x8F6 SDR12 1.8V => 0x0008
 14 => 0 [B]: DvrStrength
 10 => 0: ClkGen
 00 => 0x8: SdClkFreq
SDHC0x8F8 SDR25 1.8V => 0x0004
 14 => 0 [B]: DvrStrength
 10 => 0: ClkGen
 00 => 0x4: SdClkFreq
SDHC0x8FA SDR50 1.8V => 0x0002
 14 => 0 [B]: DvrStrength
 10 => 0: ClkGen
 00 => 0x2: SdClkFreq
SDHC0x8FC SDR104 1.8V => 0x4000
 14 => 0x1 [A]: DvrStrength
 10 => 0: ClkGen
 00 => 0: SdClkFreq
SDHC0x8FE DDR50 1.8V => 0x0002
 14 => 0 [B]: DvrStrength
 10 => 0: ClkGen
 00 => 0x2: SdClkFreq
SDHC0x900 HS400 => 0x4000
 14 => 0x1 [A]: DvrStrength
 10 => 0: ClkGen
 00 => 0: SdClkFreq


Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5fe5c0a5a5ecf292ce8703e9c9ea80b6f1b6440e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-09-28 09:39:49 +00:00
Raul E Rangel 94be1f7399 mb/google/zork: Set eMMC presets
They should be tuned per board to get the best signal and boot time.

This fixes the HS400 preset, so it's correctly set to A. It also changes
the SDR50 and DDR50 presets to B. We can't boot correctly when DDR50 is
set to A.

I chose 1 as the init kHz value since that's what depthcharge uses to
calculate the init clock.

BUG=b:159823235
TEST=Boot Ezkinil and dump SDHCI preset registers.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ie2f3497b65d771820ab1a803fec73265547f8906
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-09-28 09:39:39 +00:00
Raul E Rangel 5590d9aa75 soc/amd/picasso: Add eMMC driver strength and init kHz settings
This allows passing in the presets to FSP.

I will set the UPD values after all the zork boards have had their
presets correctly set. This way we don't override the UPD defaults with
0s.

BUG=b:159823235
TEST=Build test

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I44951cacb1e9d788016a70283cf9688bf88a09f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-09-28 09:39:25 +00:00
Jonathan Zhang 60d800537b mb/ocp/deltalake: add LPC device entry in ACPI
PCH LPC device is on CSTACK. Add LPC ACPI device entry.

Without this change, following error message shows up in target OS
boot log:
ACPI BIOS Error (bug): Failure looking up [\_SB.PCI0.LPCB], AE_NOT_FOUND (20180105/dswload-211)
ACPI Error: AE_NOT_FOUND, During name lookup/catalog (20180105/psobject-252)
ACPI Error: AE_NOT_FOUND, (SSDT:COREBOOT) while loading table (20180105/tbxfload-228)
ACPI Error: 1 table load failures, 1 successful (20180105/tbxfload-246)

Also TPM device is not created.

TESTED=Booted DeltaLake DVT, run following command in target OS:
[root@dhcp-100-96-192-153 ~]# dmesg | grep tpm
[    7.331890] tpm_tis MSFT0101:00: 2.0 TPM (device-id 0x1B, rev-id 16)

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I8614f6951389bd5c8f8f33522d0a9a9160ac3f66
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-09-28 09:39:11 +00:00
Jonathan Zhang 1ba42a9ca2 soc/intel/xeon_sp/cpx: add ACPI name for CSTACK
Add ACPI name for CSTACK. The name is PC00 to match with ACPI table
generated.

The PCIe domain has multiple PCIe stacks. devicetree.cb at the moment
does not support multiple PCIe stacks, eg. IIO stacks. For now, assign
the name to PCIe domain. In future, the name needs to be assigned to
CSTACK.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I24a6f29734452426218419cdcf66702edde96f46
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-09-28 09:39:02 +00:00
Jonathan Zhang db202bad09 soc/intel/common/block/lpc: add acpi name
Add ACPI name for LPC device. The name matches with what is in
soc/intel/common/block/acpi/acpi/lpc.asl.

Since several Intel SOCs select CONFIG_SOC_INTEL_COMMON_BLOCK_LPC,
remove duplicated acpi name assignments.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: If418c83caafe5d9e2af135a8946cbe5eb687b9ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-28 09:38:39 +00:00
Jonathan Zhang 339fa7389b doc/mb/ocp: update deltalake server documentation
Upon completion of 2nd build/test/release cycle of Deltalake server
alternative firmware engineering, update the document.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I1806526bd477ed407bb7fd36c7fe4ce0e57b72f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-09-28 09:37:57 +00:00
Jonathan Zhang 7614099b8e vc/intel/fsp/fsp2_0/CPX-SP: upgrade to ww38 FSP release
Intel CPX-SP FSP ww38 release made some changes to FSP-M header
file. Those changes do not need corresponding soc code change.

TESTED=built image with ww38 FSP RELEASE binary, booted DeltaLake
DVT to target OS.

Change-Id: I320c4a674f9f4d37c30ce6df510f18ad1ae057eb
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-28 09:37:01 +00:00
Eric Lai 58a706af96 mb/google/octopus/var/fleex: Use Wifi SAR table for non-LTE sku only
Use Wifi SAR table for non-LTE sku only.

BUG=b:169115341
BRANCH=octopus
TEST=Check no SAR table can be loaded with sku id 4.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I086fa14a9f23e4a0fc0ef8085040219c932dbf17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45640
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-28 09:36:11 +00:00
Patrick Rudolph 0348bbe971 include/cpu/x86/tsc: Fix rdtsc on x86_64
The used assembler code only works on x86_32, but not on x86_64.
Use the inline functions to provide valid rdtsc readings on both
x86_32 and x86_64.

Tested on Lenovo T410 with additional x86_64 patches.

Change-Id: Icf706d6fb751372651e5e56d1856ddad688d9fa3
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-09-28 09:36:00 +00:00