Commit Graph

35667 Commits

Author SHA1 Message Date
Jonathan Zhang 29f61a2110 soc/intel/xeon_sp/cpx: update HOB display code
Fix a typo to use CONFIG_DISPLAY_HOBS instead of CONFIG_DISPLAY_HOB.

Build hob display into romstage, in addition to ramstage.

Memory map HOB data is a big structure. Update the soc_display_memmap_hob()
to assist trouble shooting of FSP interface.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Iece745fe21d11b4a470ba8318201bb6e68c5da26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42841
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-04 11:25:50 +00:00
Johnny Lin 37f38505f2 mb/ocp/deltalake: Add VPD flash regions and select VPD and VPD_SMBIOS_VERSION
Tested on OCP Delta Lake.

Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Change-Id: I1e6e2bd25cbe3b0c0547dda9e457c4d55df28388
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42428
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-04 11:24:05 +00:00
Johnny Lin 5e8709f89e mb/ocp/deltalake: Update SMBIOS type 2 Location In Chassis from BMC
There are 4 slots in YV3, Location In Chassis should be 1~4.

Tested=on OCP Delta Lake, dmidecode -t 2 verified the string is correct.

Change-Id: I3b65ecc6f6421d85d1cb890c522be4787362a01b
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-07-04 11:23:56 +00:00
BryantOu 4a8e58fd93 arch/x86/smbios: Add SMBIOS type8 data
Refer to section 7.9 Port Connector Information of DSP0134_3.3.0
to add type 8 data, the table of data should be ported according
to platform design and MB silkscreen.

Change-Id: I81e25d27c9c6717750edf1d547e5f4cfb8f1da14
Signed-off-by: BryantOu <Bryant.Ou.Q@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-07-04 11:21:18 +00:00
Johnny Lin b8899ef7e7 lib/coreboot_table: Add Intel FSP version to coreboot table
Add a new LB_TAG_PLATFORM_BLOB_VERSION for FSP version, it would
add Intel FSP version to coreboot table LB_TAG_PLATFORM_BLOB_VERSION
when PLATFORM_USES_FSP2_0 is selected.

Tested=On OCP Delta Lake, with an updated LinuxBoot payload cbmem utility
can see "LB_TAG_PLATFORM_BLOB_VERSION": "2.1-0.0.1.120"

Change-Id: I92a13ca91b9f66a7517cfd6784f3f692ff34e765
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-07-04 11:20:08 +00:00
Kyösti Mälkki 542cffacbb drivers/pc80/tpm: Remove LPC_TPM
Replace uses with MAINBOARD_HAS_LPC_TPM, if drivers/pc80/tpm
is present in devicetree.cb it is necessary to always include
the driver in the build.

Change-Id: I9ab921ab70f7b527a52fbf5f775aa063d9a706ce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner
2020-07-04 11:17:44 +00:00
Jonathan Zhang 34cfeee406 doc/mb/ocp: Add documentation for Delta Lake
Add OCP platform Delta Lake documentation.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I9216c80023db071591c8d3add7c0f041e9e6b97e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-04 11:16:44 +00:00
Christian Walter 02b3937083 MAINTAINERS: Add Maintainers for Prodrive Hermes Mainboard
Change-Id: Ifaed81016be9cd2845b3a2c55ee1a5ac4d317081
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-04 11:16:19 +00:00
Johnny Lin 407b35aa9f mb/ocp/deltalake: Populate SMBIOS data and set the read PPIN to BMC
1. Populate SMBIOS data from OCP_DMI driver read from FRU and PPIN MSR
   for OEM string 1 to 6, add string 8 for PCIE configuration.
2. Set the read PPIN MSR to BMC.

Tested on OCP Delta Lake.

Change-Id: I9127cf5da1c56d8012694d070615aec24cc22fdf
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41279
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-04 11:15:23 +00:00
Johnny Lin 54a7f41de1 soc/intel/xeon_sp: Add read CPU PPIN MSR function
These changes are in accordance with the documentation:
[*] page 208-209
    Intel(R) 64 and IA-32 Architectures, Software Developer’s Manual,
    Volume 4: Model-Specific Registers. May 2019.
    Order Number: 335592-070US

Tested on OCP Tioga Pass and Delta Lake.

Change-Id: I8c2eac055a065c06859a3cb7b48ed59f15ae2fc4
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42901
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-04 11:15:11 +00:00
Johnny Lin 99198b2f76 drivers/ipmi: Add IPMI KCS support in romstage
It's necessary to run IPMI commands in romstage for writing error SEL
such as memory initialization error SEL, and also for other usages
such as starting FRB2 timer, OEM commands, etc.

Add CONFIG_BMC_KCS_BASE for BMC KCS port address that can be used
across romstage and ramstage.

Change-Id: Ie3198965670454b123e570f9056673fdf515f52b
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40234
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-04 11:14:44 +00:00
Subrata Banik f861f99967 soc/intel/tigerlake: Remove unused EHL DID from TGL SoC
TEST=Able to build and boot TGLRVP.

Change-Id: I7be3cb0bd63778e34c810d69e68b584691225f7a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-04 09:52:10 +00:00
Jamie Ryu eb1f5bc079 mb/google/volteer: Enable CSE Lite SKU for ES2 platforms
BUG=b:158140797
TEST=build and boot volteer with CSE Lite SKU
Cq-Depend: chrome-internal:3100721

Change-Id: I4f939883617a1271b30c76d41e61113bbdd6ab5b
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42070
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03 23:56:55 +00:00
Jamie Ryu 02a1b338f8 soc/intel/tigerlake: Disable hybrid storage mode in CSE Lite RO boot
A UPD HybridStorageMode allows a platform to dynamically configure the
PCIe strap configuration required if an Optane device is connected.
The strap configuration is done by HECI commands between FSP and CSE to
override the default PCIe strap value, and the updated strap value is
stored in SPI RW data to be used on the next boot.

CSE Lite supports the strap override when running on CSE RW partition,
while CSE RO partition does not support it because CSE RO is not allowed
to access SPI RW data. The strap override failure on CSE RO causes FSP
not initializing PCH Clkreq and PCIe port mapping and this results NVMe
and Optane initialization failure.

By disabling HybridStorageMode in case of CSE RO boot, NVMe detection is
done by the default PCIe configuration and Optane is detected as a
single NVMe storage device on CSE RO boot in recovery mode. Both NVMe
and Optane devices detection as well as OS installation to these storage
devices are verified on CSE RO boot in recovery mode.

BUG=b:158643194
TEST=boot and verified with tglrvp and volteer in recovery mode
Cq-Depend: chrome-internal:3100721

Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: I5397cfc007069debe3701bf1e38e81bd17a29f0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42282
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03 23:56:34 +00:00
Patrick Georgi 401671c7ab Update vboot submodule to upstream master
Updating from commit id c531000f:
2020-05-18 20:55:55 +0000 - (vboot: Add recovery reason code for CSE Lite SKU errors)

to commit id 68de90c7:
2020-07-02 11:31:05 +0000 - (Allow building for non-CrOS environments)

This brings in 59 new commits.

Change-Id: I7f3c30511ff4acc60e3581bdab89d685dc7beaa5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43008
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03 21:03:19 +00:00
Aaron Durbin 76fcf82901 mb/google/zork: adjust eSPI virtual irq settings
The eSPI polarity macros were reversed. Those are fixed so adjust
the corresponding values related to the correct expectations of
the IRQ path: eSPI virtual wire IRQs are active level high. The EC
sends active level high virtual wire IRQs. The default interrupt
encodings in ACPI for P2/S devices are active edge high. Therefore,
there is no need to override anything.

BUG=b:157984427

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ia28d82cd9e432df98839f68bac4eae4447455e53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-03 15:36:30 +00:00
Aaron Durbin d3758540a9 soc/amd/common: fix eSPI virtual wire polarity encoding
eSPI interrupts are active level high. The eSPI polarity register
in the chipset inverts incoming signals if the corresonding bit
is 0 in the register. Therefore, all active high (edge or level)
virtual wire interrupts need to ensure they are not inverted.

And really the sender of the interrupts should be conforming to the
the eSPI spec. As such inverting any signals should not be necessary,
but this register in the chipset allows for fixing up those misbehaviors.

BUG=b:157984427

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I7346bb0484506d96d7ab2e6d046ffa0571683a48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-03 15:35:44 +00:00
Kyösti Mälkki b798deb1d5 mb/intel/cannonlake_rvp: Unconditionally select audio drivers
Change-Id: Ic9f2e44692b20c2efabc468b10ec531e8b5a3e59
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41706
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03 08:29:34 +00:00
Kyösti Mälkki 3456a68649 mb/intel/coffeelake_rvp: Unconditionally select audio drivers
Change-Id: I3fad7cb2ac0b88adbe75acfa7a17f5a9b0bde6c2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41705
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03 08:29:16 +00:00
Kyösti Mälkki e8f091580a mb/intel/icelake_rvp,jasperlake_rvp: Select DRIVERS_SPI_ACPI
Change-Id: If25ed7b5cc545abcbf16af66173058dde75260f7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41703
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03 08:28:56 +00:00
Kyösti Mälkki 53c22873b0 drivers/intel/pmx_mux: Remove redundant declaration
Change-Id: Ie64b267ac01afa9774105e1ab8a7c18021726ff3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41871
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03 08:28:20 +00:00
Tim Wawrzynczak a1061639d2 soc/intel/common: Only touch Time Window Tau bits in supported SoCs
The Time Window Tau bits are only supported by Comet Lake/Cannon Lake
onwards, so skip setting those bits for earlier SoCs.

Change-Id: Iff899ee8280a9b9bbcea57d4e98b92d5410be21d
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2020-07-03 02:33:33 +00:00
Edward O'Callaghan 7b2f503038 mb/google/hatch: Allow USB2/3 wakeups to (un)plug events in Wyvern
V.2: Spare USB routed internally to another peripheral and so
no plug event hook needed.

BUG=b:1603699358,b:157479891
BRANCH=none
TEST=none

Change-Id: Ideacac417a46b96f3e82b53bbb341ecce79ee420
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42994
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03 00:04:16 +00:00
Edward O'Callaghan 8056c910bc mb/google/hatch: Allow USB2/3 wakeups to (un)plug events in Noibat
BUG=b:160296662
BRANCH=none
TEST=none

Change-Id: I5298e1779461995a98722099b397692351767089
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42975
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03 00:03:55 +00:00
Edward O'Callaghan dc7b94450f mb/google/hatch: Allow USB2/3 wakeups to (un)plug events in Faffy
BUG=b:160295948
BRANCH=none
TEST=none

Change-Id: I3600340d3448457942c827a463b458b280fea19a
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
2020-07-03 00:03:37 +00:00
Edward O'Callaghan 181c3f846b mb/google/hatch: Allow USB2/3 wakeups to (un)plug events in Kaisa
BUG=b:160296661
BRANCH=none
TEST=none

Change-Id: Id5a03f2cbdca2723ab1882c619d2d34387996b27
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42973
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03 00:03:23 +00:00
Edward O'Callaghan 78a8c85a47 mb/google/hatch: Allow USB2/3 wakeups to (un)plug events in Duffy
BUG=b:160296325
BRANCH=none
TEST=none

Change-Id: Iffa6997029d0babfd6dd504a6cc212bd74de3a8f
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42972
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03 00:03:09 +00:00
Edward O'Callaghan d0089c2b07 util/tmpl/puff: Allow USB2/3 wakeups to (un)plug events
BUG=b:159187889
BRANCH=none
TEST=none

Change-Id: Ib59108ec42955b5414f76b591cce5073f7dad1a9
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42990
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03 00:02:55 +00:00
Piotr Kleinschmidt 899b28acdb mb/pcengines/apu1/mainboard.c: reorder includes
Originally, there was problem with PC Engines apu1 platform
which returned serial number value as -64. It was caused by wrong
value of dev->bus->secondary.
Source of the problem is in Porting.h header file. It contains
'#pragma pack(1)' which affects struct device. As mainboard.c
uses different binary layout because of this attribute,
reference dev->bus->secondary lands at wrong memory address.
This patch reorder includes and put <AGESA.h> and <AMD.h>
at the end of list, making struct device consistent.
As a result bus number value in device's structure is correct
and hence serial number.

TEST=`dmidecode -t 2` command in Linux Debian

Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com>
Change-Id: I5e8690d100b38ac7889395d375c0ff32bdefda0b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42512
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-02 19:32:43 +00:00
Angel Pons 43bcc7b6ed nb/intel/ironlake: Clean up code style (except raminit)
Reflow lines, correct coding style and align struct members, among
other things. As raminit is very large, handle it on a follow-up.

Tested with BUILD_TIMELESS=1, packardbell/ms2290 does not change.

Change-Id: I343edf1bc2a5ac20ff0aa6de4486e685ce430737
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42701
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-02 19:29:10 +00:00
Furquan Shaikh aee3b148ba mb/google/zork: Generate I2SM ACPI device at runtime
This change moves the generation of I2SM ACPI device from static asl
file to runtime generation by ACP device driver. dmic_select_gpio is
set to match version 3+ of Trembyle and Dalboz schematics. In order to
maintain backward compatibility, dmic_select_gpio is updated at
runtime using variant_audio_update for board versions that are prior
to version 3 of reference schematics.

The only difference from static generation is that the device I2SM is
added under ACPD (i.e. ACP device) instead of CREC (Chrome EC
device). It does not make any functional difference from the kernel
perspective.

BUG=b:157603026
TEST=Verified that the following device gets generated in SSDT:
    Scope (\_SB.PCI0.PBRA.ACPD)
    {
        Device (I2SM)
        {
            Name (_HID, "AMDI5682")  // _HID: Hardware ID
            Name (_UID, One)  // _UID: Unique ID
            Name (_DDN, "I2S machine driver")  // _DDN: DOS Device Name
            Method (_STA, 0, NotSerialized)  // _STA: Status
            {
                Return (0x0F)
            }

            Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
            {
                GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly,
                    "\\_SB.GPIO", 0x00, ResourceConsumer, ,
                    )
                    {   // Pin list
                        0x000D
                    }
            })
            Name (_DSD, Package (0x02)  // _DSD: Device-Specific Data
            {
                ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
                Package (0x01)
                {
                    Package (0x02)
                    {
                        "dmic-gpios",
                        Package (0x04)
                        {
                            \_SB.PCI0.PBRA.ACPD.I2SM,
                            Zero,
                            Zero,
                            Zero
                        }
                    }
                }
            })
        }
    }
Verified audio via speakers and mic input.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I5d1602c7f719eef9487ddea68e429d27408f9a76
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2253638
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-02 19:13:10 +00:00
Furquan Shaikh 583ba8b1ef soc/amd/picasso: Add support for generating I2S machine device
This change adds support in ACP device driver to generate I2S machine
device (AMDI5682) in SSDT. It expects mainboard to provide chip config
`dmic_select_gpio` that can be passed as `dmic-gpios` in _DSD for the
device.

BUG=b:157603026
TEST=Verified that I2S machine device is correctly generated for
trembyle.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I22ab53d7d68c6e042e467e598d688e360d28586f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2252557
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-02 19:13:04 +00:00
Furquan Shaikh 0d787a1b06 soc/amd/picasso: Add .acpi_name and .acpi_fill_ssdt_generator for ACP device
This change adds support for .acpi_name and .acpi_fill_ssdt_generator
device operations for the ACP device.

BUG=b:157603026

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I84bb8150dada99def85b685535706aa609de227f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2252556
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-02 19:12:54 +00:00
Furquan Shaikh d2d5e44a67 acpi_device: Replace polarity with active_low in acpi_gpio for GpioIo
As per ACPI spec, GpioIo does not have any polarity associated with
it. Linux kernel uses `active_low` argument within GPIO _DSD property
to allow BIOS to indicate if the corresponding GPIO should be treated
as active low. Thus, if GPIO has active high polarity or if it does
not have any polarity associated with it, then the `active_low`
argument is supposed to be set to 0.

Having a `polarity` field in acpi_gpio seems confusing because GPIOs
might not always have polarity associated with them. Example, in case
of DMIC-select GPIO where 0 means select DMIC0 and 1 means select
DMIC1, there is no polarity associated with the GPIO. Thus, it would
be clearer for mainboard to use macros without having to specify a
particular polarity. In order to enable mainboards to provide GPIO
information without polarity for GpioIo usage, this change also adds
`ACPI_GPIO_OUTPUT` and `ACPI_GPIO_INPUT` macros.

BUG=b:157603026

Change-Id: I39d2a6ac8f149a74afeb915812fece86c9b9ad93
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-02 19:12:46 +00:00
Furquan Shaikh 7245100cdd acpi_device: Add helper macros for setting acpi_gpio fields
This change adds helper macros for initializing acpi_gpio fields
for GpioIo/GpioInt objects. This allows dropping some redundant code
for each macro to set the structure fields.

Change-Id: Id0a655468759ed3035c6c1e8770e37f1275e344e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-02 19:12:38 +00:00
Furquan Shaikh 8c88ceca57 drivers/generic/gpio_regulator: Drop unused driver for gpio_regulator
Proposal for gpio_regulator usage in ACPI never got accepted upstream
for Linux kernel. So, the gpio_regulator driver in coreboot remains
unused. This change drops this unused driver.

Change-Id: Ia1e0ae4f955b9ffc8346d957f755499419d8cbc7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-02 19:12:32 +00:00
Jonathan Zhang 8cdb0b3767 mb/ocp: remove sonorapass
Sonora Pass server program was terminated.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I5354ea1e912fd25f0ac9851edf0461413ad8bb21
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42948
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-02 16:34:57 +00:00
Jonathan Zhang e9b0b08079 MAINTAINERS: Add entry for src/soc/intel/xeon_sp
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Ib8d16057e3882c50bdca454632a64227166016fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Anjaneya "Reddy" Chagam <anjaneya.chagam@intel.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-02 16:34:02 +00:00
Jonathan Zhang dd4f64346e MAINTAINERS: Add entry for mb/ocp/deltalake
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Ib13ffac064c197c68de4ea7b04fc6ae024f5c099
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Anjaneya "Reddy" Chagam <anjaneya.chagam@intel.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-02 16:33:56 +00:00
Aaron Durbin c5bb02f2ec soc/amd/common: fix SPI bar resource usage
The ACPI code was not masking off the correct bits for publishing
the SPI bar to the OS.

It resulted in a dmesg messagelike:
	system 00:00: [mem 0xfec10002-0xfec11001] has been reserved
And /proc/iomem entry
	fec10002-fec11001 : pnp 00:00

These addresses are wrong because they are including bits of a
register that are not a part of the address.

Moreover, the code does not publish the eSPI register area either.
The eSPI registers live at 0x10000 added to the SPI bar. Lastly,
both regions are less than a page so only report a page of usage
for each.

Stoney Ridge's SPI bar register defines the address as 31:6 while
Picasso's SPI bar register defines the address as 31:8. Use Picasso's
valid mask for both cases because no one is assigning addresses
that are aligned to less than 256 bytes.

With the fixes, dmesg reports:
	system 00:00: [mem 0xfec10000-0xfec10fff] has been reserved
	system 00:00: [mem 0xfec20000-0xfec20fff] has been reserved
And /proc/iomem indicates:
	fec10000-fec10fff : pnp 00:00
	fec20000-fec20fff : pnp 00:00

BUG=b:160290629

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I130b5ad26d9e13b44c25fbb35a05389f9e8841ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42959
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-02 15:55:46 +00:00
Tim Chen 57285820a3 mb/google/faffy: update DPTF parameters
Modify DPTF parameters for faffy from thermal team.

BUG=b:160292247
BRANCH=None
TEST=emerge-puff coreboot chromeos-bootimage
     verify the parameters are correct

Change-Id: Ie8290f5460838f785a587c85b2ab7dd171dd0a54
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
2020-07-02 00:33:08 +00:00
Patrick Rudolph f664321508 Documentation: Add several fixes
* Add support for Sphinx 3.0+
* Add backward support for Sphinx 1.8 and older
* Make sphinxcontrib ditaa an optional extension
* Allow SPHINXOPTS to be set from command line
* Add sphinx and sphinx-lint to top level Makefile

Change-Id: If10aef51dc426445cb742aad13b19ee7fe169c51
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41492
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-01 21:51:26 +00:00
Angel Pons ecdbc842e2 nb/intel/ironlake/northbridge.c: Drop thunk functions
Just call the called function directly.

Change-Id: I0c997a63cbbd2b1029f94c23685847df910f8a0e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-07-01 21:39:54 +00:00
Furquan Shaikh 489ffefef6 mb/google/zork: Move EC wake to happen in ramstage
Currently, EC wake signal (GPIO_24) is configured early on in
romstage. However, there is no need for that since EC wake is not
really required to be configured until ramstage. This change moves
GPIO_24 configuration to happen in ramstage.

BUG=b:159832123

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I6949dcd7c866df2fa028c7b2e7f347cec988e309
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42952
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-01 19:32:01 +00:00
Furquan Shaikh ffbf5d9818 mb/google/zork: Fix pad configurations for wake signals
This change updates the pad configurations for wake lines as
follows:
1. Pen eject wake signal needs to be configured as PAD_WAKE i.e. wake
using GPIO controller block. This is because pen eject signal is not
dual routed and the trigger filtering is set by the kernel driver
differently for S0 and S3 wake. Hence, it cannot use SCI GEVENT and
instead has to fall back to using GPIO controller wake.
2. All other wake signals (EC, trackpad, fingerprint) need to be
configured as SCI. This allows OS to enable/disable wake from these
sources if required. Example: powerd disables wake from trackpad when
in tablet mode. Hence, all other wake sources use SCI.

BUG=b:159832123
TEST=Verified wake using pen eject and EC.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Id8cd5926f223db51a689ed8948040b8070cf1680
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42951
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-01 19:31:48 +00:00
Sumeet R Pawnikar 15311d246f mb/google/dedede: set tcc_offset value to 10
Set tcc_offset value to 10 in devicetree for Thermal Control
Circuit (TCC) activation feature.

BUG=None
BRANCH=None
TEST=Built for dedede platform and verified the MSR value

Change-Id: I53d1bd413c64643cf8bdaef266bde25a2f3a97ee
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42906
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-01 19:04:30 +00:00
Angel Pons ca18073861 nb/intel/ironlake: Drop copy-pasted and unused macro
Tested with BUILD_TIMELESS=1, packardbell/ms2290 remains identical.

Change-Id: I78856707864563e392626a494f0e77eec9802002
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-07-01 18:15:58 +00:00
Angel Pons 8308e2b9fa nb/intel/ironlake: Use `pci_update_config32()`
Change-Id: I7d36165e61e6399458479d47a33fe708eba7ea86
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-07-01 18:15:33 +00:00
Angel Pons 68ab745086 nb/intel/ironlake: Simplify BAR handling
Currently, northbridge BARs are 32-bit values. We don't have any use
case for BARs above 4 GiB in early stages, so handling possibly 64-bit
values seems unnecessary, which currently is a noisy way to write zero.

Tested with BUILD_TIMELESS=1, packardbell/ms2290 remains identical.

Change-Id: I93d1740b961f6a5962757d9a1e960b3f1014a0c6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-07-01 18:15:15 +00:00
Angel Pons dd6a3d841b nb/intel/ironlake/ironlake.h: Clean up
Align values and drop copy-pasted, wrong and unused definitions.

Tested with BUILD_TIMELESS=1, packardbell/ms2290 remains identical.

Change-Id: I44f96982c8a38e1933cd78a976e18a8a11fb4096
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-07-01 18:14:44 +00:00