Commit Graph

35667 Commits

Author SHA1 Message Date
Anna Karas 907ddc3e07 tests: Complete lib/string-test test case
Implement unit tests for remaining string library functions. Fix memory leak
in test_strdup().

Signed-off-by: Anna Karas <aka@semihalf.com>
Change-Id: I8ac6a6b2413d9077dc9ea81f638a2b0acd5c8862
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42311
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06 23:47:27 +00:00
Angel Pons 9ce5bee8c0 sb/intel/i82801jx/sata.c: Handle ABAR as a resource
Instead of directly reading ABAR without any checking, do like i82801ix
and treat it as a resource. This prevents problems if ABAR is not set.

Change-Id: I4f888b748204860b0a7e1bf5611f5f3e487e8081
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-07-06 23:34:21 +00:00
Angel Pons 6ab28b465a src/**/acpi/smbus.asl: Drop dead code
The `ENABLE_SMBUS_METHODS` symbol is not defined anywhere, so this code
isn't even being tested. So, throw it into the bitbucket before it rots
any further. If anyone needs that code ever again, it's in git history.

Change-Id: I22e3f1ad54e81f811c9660d54f3765f3c6b83f01
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-06 23:11:08 +00:00
nick_xr_chen f446b81f8f mb/google/volteer: Enable HotPlug on PCIe root port for the SD express
Enable HotPlug for the PCIe root port that the SD express is on so the
OS can re-train the link without needing a reboot if it goes down
unexpectedly at runtime.

BUG=b:156879564
BRANCH=master
TEST=enable HotPlug on Volteer Root Port 7 (SD express) and check in
linux that it is identified as a HotPlug capable root port

Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com>
Change-Id: Ie9d427dd297567f06123119a670b5ed2e1f73701
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42897
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06 20:32:11 +00:00
Angel Pons d9dea65615 soc/intel: Drop unused `#include <reg_script.h>`
In some cases, the SoC did not even select `REG_SCRIPT` in Kconfig.

Change-Id: I617f332b80c534997e06a91247d1be90a85573be
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-07-06 19:29:07 +00:00
Patrick Rudolph 7d28f20051 pgtblgen: Update comment to match what the code does
Change-Id: Ib87c804b139a96a4173a6f392f0f99a77d32fc01
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-07-06 17:24:59 +00:00
Kyösti Mälkki b2a10f8264 devicetree: Remove weak declarations for ops
Make it compulsory to build with all the drivers that are
visible in the board devicetree.cb file.

Change-Id: Ifb783e2f733d5c65c615e5c1879e3e4c7a83e049
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-06 16:11:02 +00:00
Kyösti Mälkki 18d41e1c45 mb/amd/mandolin: Drop SPD eeproms in devicetree
Even with previous platforms, these entries were not
utilised for raminit.

Change-Id: I9a9a1a292bad8c4c89cbacb826c80f4098cae00f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-07-06 15:18:52 +00:00
Nico Huber 06b68d1097 prog_loaders: Fix ramstage loading on x86
A regression sneaked in with 18a8ba41cc (arch/x86: Remove RELOCATABLE_
RAMSTAGE). We want to call load_relocatable_ramstage() on x86, and
cbfs_prog_stage_load() on other architectures. But with the current
code the latter is also called on x86 if the former succeeded. Fix
that and also balance the if structure to make it more obvious.

TEST=qemu-system-x86_64 boots to payload again.

Change-Id: I5b1db5aac772b9b3a388a1a8ae490fa627334320
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43142
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06 09:36:15 +00:00
Patrick Georgi 8008c530e7 mb/google/volteer: Rename remaining pmc_mux/con to conn
CB:43090 renamed con to conn to avoid issues when building on Windows.
CB:42905 introduced more uses of the old name.

Adapt the latter to comply with the former.

Change-Id: I723141add5452fc541f67cb8591793f2d64cc231
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43141
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06 09:35:52 +00:00
Keith Hui 698647a8c0 mb/asus/p8z77-m_pro: Remove PS/2 keyboard & mouse duplicate
PS/2 keyboard and mouse devices are declared twice in the DSDT, once
in mainboard and once in southbridge. It would appear in Windows
Device Manager as two PS/2 keyboards and two PS/2 mouses, all with
resource conflicts. This change drops the declaration from mainboard.

The issue was discovered when this setup was copied for p8z77-m and
being boot tested.

Change-Id: I746a960aaf3992acbcb6a7364641fc4fd12002d2
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41225
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06 06:30:56 +00:00
Paul Menzel 01c1815eae drivers/ipmi: Increase BMC waiting message level from DEBUG to INFO
As the booting the system can be delayed for a noticeable amount of
time, often 60 seconds is the default, this is not a debug message.
Chose log level BIOS_INFO.

Change-Id: I941792148820c0e1d3fbc80197125fee8cedf09f
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2020-07-06 06:30:14 +00:00
Keith Hui 572d66abb6 nb/intel/i440bx: Add PMCR register to ACPI code
p3b-f suspend code is going to use it.

Change-Id: Iebc17257e9f690115ec35d94c7c36df39341f0df
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41092
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06 06:27:36 +00:00
Keith Hui 8ba85deb8f nb/intel/i440bx: Refactor ACPI code
Bring DRB7 OpRegion and top-of-memory indicator inside NB device.

Use more concise ASL 2.0 syntax for TOM calculations.

Change-Id: I2c74ef30a9bb48e02154f963b1ca3a4f5f3004df
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-07-06 06:26:55 +00:00
Keith Hui 562279e6ca sb/intel/i82371eb: Don't fill \_SB.PCI0.MBRS
Only two mainboard groups use this southbridge:

emulation/qemu-i440fx: Nothing creates or consumes this ACPI path.
asus/p2b: It only fills the (mostly static) PIIX4E PM/SMBus I/O
resources, which are being declared in DSDT.

It is not doing anything useful and causes ACPI errors in Linux
kernel[1][2], so it has to stop.

[1] https://review.coreboot.org/c/coreboot/+/38601
[2] https://review.coreboot.org/c/coreboot/+/38304

Change-Id: I770047610e02c08191613b57c989b3bc1d464684
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-07-06 06:23:44 +00:00
Arthur Heymans c73ad35e39 mb/intel/dg43gt: Don't redefine MMCONF_BASE_ADDRESS
Change-Id: I4d62a04778c8f634b48eee459808f640451b9b48
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-07-06 06:19:30 +00:00
Kyösti Mälkki 18a8ba41cc arch/x86: Remove RELOCATABLE_RAMSTAGE
We always have it, no need to support opting-out.

For PLATFORM_HAS_DRAM_CLEAR there is a dependency of ramstage
located inside CBMEM, which is only true with ARCH_X86.

Change-Id: I5cbf4063c69571db92de2d321c14d30c272e8098
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43014
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06 06:17:47 +00:00
David Wu 7c040adc8c mb/google/volteer/var/voxel: Update gpio settings and overridetree.cb
Based on schematic and gpio table of voxel, generate gpio settings
and overridetree.cb for voxel.

BUG=b:157879197,b:155062762
TEST=FW_NAME=voxel emerge-volteer coreboot chromeos-bootimage
Verify that the image-voxel.bin is generated successfully.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I49c1923e63d87f11de362fd893905ac2f1137bba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-07-06 06:15:27 +00:00
Julius Werner 63358eaff6 libpayload: cbgfx: Fix add_fractions() overflow reduction
log2(1) is 0 and log2(0) is -1. If we have the int64_t 0xffffffff then
log2(0xffffffff >> 31) = log2(0x1) = 0, so the current reduction code
would not shift. That's a bad idea, though, since 0xffffffff when
interpreted as an int32_t would become a negative number.

We need to always shift one more than the current code does to get a
safe reduction. This also means we can get rid of another compare/branch
since -1 is the smallest result log2() can return, so the shift can no
longer go negative now.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ib1eb6364c35c26924804261c02171139cdbd1034
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Joel Kitching <kitching@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-07-06 06:14:57 +00:00
Chris Wang a94136f082 mb/google/zork: Apply cereme telemetry settings for dalboz
Currently, the telemetry settings are not for the pollock platform
and might causethe power and performance issue. so applied the Pollock
reference board settings to Dalboz to improve the performance,
and the values need to be updated after the SDLE test finished.

BUG=b:157961590,b:152922299
TEST=Build.

Change-Id: I0da5b81afaa5814c13ec0257dc0eb3471be94c29
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2228257
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42998
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06 06:14:31 +00:00
Chris Wang 1e3e528d23 mb/google/zork: Apply USB2 default phy tune parameter for Zork family
Apply the default USB2 phy tuning parameter for Zork family

BUG=b:155132211
TEST=Build, verified the default value been applied on trembyle
and the USB2 device works well.

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I1f00b04173796d70147e232bafa405487b0761e1
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2260216
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42997
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06 06:14:17 +00:00
Chris Wang 04dfc26f94 mb/google/zork: Add USB2 phy tuning parameter for SI tuning
Add the USB2 phy tuning parameter to adjust the USB 2.0 PHY driving strength.

BUG=b:156315391
TEST=Build, verified the tuning value been applied on Trembyle.

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I3d31792d26729e0acb044282c5300886663dde51
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2208524
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com>
Tested-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-06 06:14:07 +00:00
Caveh Jalali 6e62223f01 mb/google/volteer: Add support for passive USB-C daughterboard
The USB-C SBU and HSL orientation configuration depends on the USB
daughterboard used on the system. This patch adds an additional
configuration for supporting passive USB daughterboards using "probe"
directives to select the appropriate configuration at runtime.

BUG=b:158673460
TEST=verified active USB DBs enumerate at USB3 speeds in linux

Signed-off-by: Caveh Jalali <caveh@chromium.org>
Change-Id: Ia4bd97de8f974531f97469a5e47ecf4d948beca9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-06 06:12:14 +00:00
Karthikeyan Ramasubramanian 11715d8dc6 mb/google/dedede: Create Boten Legacy variant
Upcoming builds of boten will use 16 MiB SPI ROM. So create a legacy
Boten variant to support the builds that use 32 MiB SPI ROM.

BUG=None
TEST=Build the boten and boten_legacy variant.

Cq-Depend: TBD
Change-Id: Idf7732768aa7fbf2281a4cbf47b7b5b4f8ef51da
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-07-06 06:11:45 +00:00
Karthikeyan Ramasubramanian dab20f887e mb/google/dedede: Create Drawcia Legacy variant
Upcoming builds of drawcia will use 16 MiB SPI ROM. So create a legacy
Drawcia variant to support the builds that use 32 MiB SPI ROM.

BUG=None
TEST=Build the drawcia and drawcia_legacy variant.

Cq-Depend: TBD
Change-Id: Ifb5a4778abe38a396e35963a3270b0d3cc9809e0
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-07-06 06:11:37 +00:00
Kyösti Mälkki 8d119fcfba soc/amd/common: Fix missing gpio_banks.h include
Change-Id: I2c92280f3bbd80bd7a0d3abfb2fddcef997e144e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-06 06:09:28 +00:00
Raul E Rangel 30d7b54742 soc/amd/picasso/memlayout: Verify bootblock is 16-bit aligned
The bootblock must be 16-bit aligned for it to boot.

BUG=b:159081993
TEST=Made sure trembyle still compiles.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I29c244a3f08df46c5992fe81683b9c0d740ff248
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-06 06:08:55 +00:00
Maulik V Vaghela e927d9b3ad soc/intel/jasperlake: set SerialIoUartDebugMode to skip Uart Init
Since coreboot is initializing uart for debug logs, fsp should not reinitialize it.
Thus we need to set FSP UPD to skip Uart init in FSP and use settings done by coreboot

BUG=None
BRANCH=None
TEST=FSP is able to push debug logs on UART with this setting

Cq-Depend: TBD
Change-Id: I0fda2ace3b1f63159e9809d6a3044a3bad452f07
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2020-07-06 06:08:24 +00:00
Ronak Kanabar a8b80942a0 vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2194
The FSP-M/S headers added are generated as per FSP v2194.

BUG=b:159193895
BRANCH=None
TEST=Build and boot JSLRVP

Cq-Depend: TBD
Change-Id: I0cd84fdb0089bf8ea3f4440e89fdee7f11119751
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42471
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06 06:08:03 +00:00
Marshall Dawson 4d38c7546c soc/amd/picasso: Use PSP Sx command only for S3
Skip sending MboxBiosCmdSxInfo for sleep states other than S3.  The
PSP only acts on S3 and ignores all others.  As a result, the command
register is not cleared upon return and coreboot reports a timeout.

BUG=b:153622879
TEST=Use halt from command line, verify command skipped.

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Ic47b8507e29e4c53898e88fb46e532b71df87d07
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-06 03:32:54 +00:00
Paul Menzel 6663ad99cf arch/x86: Support x86_64 exceptions
*   Doesn't affect existing x86_32 code.

Tested on qemu using division by zero.
Tested on Lenovo T410 with additional x86_64 patches.

Change-Id: Idd12c90a95cc2989eb9b2a718740a84222193f48
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-05 19:56:09 +00:00
Furquan Shaikh d9c6862809 mb/google/zork: Drop check for ENV_RAMSTAGE in mainboard_ec_init
This change drops the check for ENV_RAMSTAGE in mainboard_ec_init()
since it is included only in ramstage. Also, the content of
ramstage_ec_init() is moved into mainboard_ec_init().

Change-Id: I282fb07a80f4de6064a544f6dd58e8f973a597b9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43118
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05 18:35:00 +00:00
Furquan Shaikh 484f107ac4 mb/google/zork: Drop mainboard_ec_init() from romstage
mainboard_ec_init() does nothing in any stage other than ramstage. So,
this change drops the call to mainboard_ec_init() from
romstage.c. Additionally, it also drops ec.c from romstage and
verstage.

Change-Id: Iae0be4d678b0780cf532000a6c0fff1bce333c0e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43117
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05 18:34:51 +00:00
Furquan Shaikh fa78dd16bf mb/google/zork: Drop unused function variant_romstage_entry()
This change drops the function `variant_romstage_entry()` which is
unused on zork.

Change-Id: I140ab3e837971c4c7dbef5d27616043b5fc6c2c9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43116
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05 18:34:31 +00:00
Furquan Shaikh 8b6b07b942 ec/google/chromeec: Drop codec.asl
This change drops codec.asl file from Chrome EC since it is now
unused.

Change-Id: I6c2f3e53b14aaf76b9c6d038a732e79a4d7bb2f1
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43043
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05 18:34:23 +00:00
Furquan Shaikh e284bff9cf mb/google/zork: Use SSDT generator for Chrome EC audio codec device
This change drops the inclusion of codec.asl in DSDT for `GOOG0013`
device and instead uses the newly added Chrome EC audio codec driver
for filling in the device node in SSDT.

TEST=Verified that following node gets generated:
Scope (\_SB.PCI0.LPCB.EC0.CREC)
{
	Device (ECA0)
	{
		Name (_HID, "GOOG0013")  // _HID: Hardware ID
		Name (_UID, One)  // _UID: Unique ID
		Name (_DDN, "Cros EC audio codec")  // _DDN: DOS Device Name
		Method (_STA, 0, NotSerialized)  // _STA: Status
		{
			Return (0x0F)
		}
	}
}

Change-Id: I3e626ce01a3735ac2c966c0e95310be4c828b241
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43042
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05 18:34:12 +00:00
Furquan Shaikh 31b816b42f ec/google/chromeec: Add driver for audio codec device
This change adds driver for audio codec device (HID `GOOG0013`) living
behind Chrome EC. This driver generates the required ACPI node for the
codec device. In a later change, GOOG0013 device will be dropped
the .asl file.

Change-Id: Ib2759eac60265ef81df70af1d4f1f72bd9d987e8
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43041
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05 18:34:02 +00:00
Furquan Shaikh dfd7e9d560 ec/google/chromeec: Move if EC_GOOGLE_CHROMEEC to i2c_tunnel/Kconfig
This change moves `if EC_GOOGLE_CHROMEEC` from chromeec/Kconfig to
chromeec/i2c_tunnel/Kconfig. This is done to make it clear that the
Kconfig file in i2c_tunnel is sourced unconditionally, but the configs
in i2c_tunnel/Kconfig are conditionally defined based on the
evaluation of if condition.

This change addressed the feedback received on
https://review.coreboot.org/c/coreboot/+/40515/11/src/ec/google/chromeec/Kconfig#200.

Change-Id: I66cd91d6b1813ff6d0fb7be719e2da65ac6ac23b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43040
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05 18:33:53 +00:00
Furquan Shaikh ee68b88bab mb/google/kahlee: Drop macro H1_PCH_INT
This change drops H1_PCH_INT macro for GPIO_9 since it is the same
across all variants. Also, the name differed from the schematics
version `H1_PCH_INT_ODL` creating confusion.

Change-Id: I7b038426a984d8abc460a0da3ee1dc5559d7ad5f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-07-05 18:33:47 +00:00
Angel Pons aff9f54e6b arch/x86/Makefile.inc: Drop unused reset.c rule
No x86 mainboard has a reset.c file.

Change-Id: I167629c7addf485944926d57cf0228606c0f32e5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42582
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05 17:04:18 +00:00
Angel Pons 06a70e0a7c mb/supermicro/x9scl: Select IPMI_KCS
Needed for `chip drivers/ipmi` in the devicetree.

Change-Id: Ice70aab7cedaeb91a33dd90d763c5a487f190b8f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41687
Reviewed-by: Michael Niewöhner
Reviewed-by: Jonathan Kollasch <jakllsch@kollasch.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05 11:32:34 +00:00
Kyösti Mälkki 9cc6493e8f drivers/pc80/tpm: Remove support code if TPM is disabled
Change-Id: I7015d4bf6f536c5cea8e1174db81f09f756ae0e5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41873
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Michael Niewöhner
2020-07-05 11:32:17 +00:00
Kyösti Mälkki 1be23b0733 mb/lenovo/x230s: Add MAINBOARD_HAS_LPC_TPM
With devicetree listing drivers/pc80/tpm, it is compulsory
to have the corresponding driver included in the build.
Followup work will drop the associated weak function
declaration that util/sconfig currently generates.

Change-Id: Ife8deb2c973ab7c7b820244b6f72efd3b56570ae
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43047
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05 11:31:09 +00:00
Kyösti Mälkki f91cd6970e mb/google/poppy-nocturne: Add SX9310 driver unconditionally
Change-Id: I11b02cc5f8b59559443329fe0c49a6fb82b7862a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41726
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05 11:29:21 +00:00
Patrick Rudolph 56fdafbaff drivers/pc80/tpm/tis: Add x86_64 support
Fix integer with different size to pointer conversion on x86_64.

Change-Id: Ic06a32d549b694310f4c724246f28fed15acf83f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42983
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05 08:52:56 +00:00
Patrick Rudolph 34a5a9b3e6 include/cpu/x86/lapic: Add support for x86_64
Fix integer with different size to pointer conversion.

Change-Id: I9c13892b2d79be12cc6bf7bc0a5e3a39b64032a1
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42984
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05 08:52:33 +00:00
Tim Wawrzynczak e414ce4532 drivers/intel/pmc_mux: Rename con driver to conn
For historical reasons, Windows has issues with certain names being
used for files and directories, 'con' or 'CON' being one of
them. Therefore, rename the pmc_mux/con driver to pmc_mux/conn in
order to work around this issue.

TEST=built volteer (only user of this driver as of now)

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ia78dc4efe647c96a7169a3b95fc3b8944d052c83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-07-04 21:59:00 +00:00
Patrick Georgi 54be395a9b smbios: TYPE_NONE and TYPE_OTHER are already taken
Change-Id: Ic66f7c919a71cb53773d5056e5f756cd6faf4909
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43135
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-04 20:39:10 +00:00
Sindhoor Tilak e5f25cee1c post_code: reorganize order of postcode defines
Currently, the certain postcode values aren't in increasing
order of values.

The change, just reorganzies the defines in increasing order
of the values

Signed-off-by: Sindhoor Tilak <sindhoor@sin9yt.net>
Change-Id: Id5f0ddc4593f689829ab9a7fdeebd5f66939bf79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-07-04 11:36:04 +00:00
Johnny Lin ad0ccb336d drivers/ocp/dmi: Add OCP_DMI driver for populating SMBIOS from IPMI FRU data
It implements the SMBIOS IPMI FRU mapping table defined in
https://www.opencompute.org/documents/facebook-xeon-motherboard-v31
22.3 SMBIOS FRU mapping table.
Mainboard needs to configure the correct values for FRU_DEVICE_ID and BMC_KCS_BASE.

For type 11 string 1 to 6 are common and implemented in this driver, the
rest are project dependent and can be added in the mainboard code.

Tested on OCP Tioga Pass.

Change-Id: I08c958dfad83216cd12545760a19d205efc2515b
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40308
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-04 11:31:16 +00:00