Commit Graph

37722 Commits

Author SHA1 Message Date
Divya Sasidharan 49d74de969 src/ec/google/chromeec: Get Type-C Mux info from EC (TCPM)
EC being the TCPM decides the mux configuration after negotiating with the
port partner on the Type-C port. The APIs added here will give the
current essential mux state information for a given port.

BUG=None
BRANCH=None
TEST=Built coreboot image and verified that using this patch mux is being
set for display during boot

Change-Id: If994a459288ef31b0e6da8c6cdfd0ce3a0303981
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-14 05:37:40 +00:00
Brandon Breitenstein 9faab3122e soc/intel/common/block: Enable PMC IPC driver
In order for USB Type-C devices to be detected prior to loading Kernel
PMC IPC driver API is needed to send IPC commands to the PMC to update
connection/disconnection states.

BUG=b:151731851
BRANCH=none
TEST=built coreboot image and booted to Chrome OS

Change-Id: Ide3528975be23585ce305f6cc909767b96af200f
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-14 05:37:17 +00:00
Bora Guvendik 7377cda608 mb/intel/tglrvp: Enable Pcie WWAN m.2
Enables Pcie M.2 support for WWAN and disable M.2 USB.
RP4 is already on and PcieRpEnable[3] is enabled. Clock source 2 is already
configured. Added missing gpio configuration.

BUG=none
TEST=Boot to OS, check WWAN functionality

Change-Id: Ie9b7915062b2ef65d881d478e64322c0b8765614
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45828
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14 05:36:57 +00:00
Rob Barnes d1095c7ed7 mb/google/zork: Enable wake on wireless lan
Add generic wifi ACPI entry for wake on lan event.
Change configuration of GPIO 2/WIFI_PCIE_WAKE_ODL to SCI.

BUG=b:162605108
TEST=$ iw phy phy0 wowlan enable disconnect
     $ cat /proc/acpi/wakeup | grep WF
       WF00	  S3	*enabled   pci:0000:01:00.0
     $ powerd_dbus_suspend
     Reboot wifi router, DUT wakes up
BRANCH=zork

Change-Id: Idbeb2cfbc4995b8382ffc26cbe7b53764fc9252d
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45745
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14 04:47:39 +00:00
Subrata Banik 0aed4e577d soc/intel/alderlake: Enable TME for Alder Lake
List of changes:
1. Select CONFIG_INTEL_TME from SoC Kconfig
2. Set TmeEnable FSP-M UPD based on Kconfig.

TEST=Able to build and boot ADLRVP and verified from Chrome OS
that TME is enable.

Change-Id: I6992957bd2999a2efbae7b6d9c825c43bd118f72
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46296
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14 03:39:00 +00:00
Subrata Banik 8e251f7fce vc/intel/fsp/fsp2_0/adl: Update FSP header to version 1332.01
List of changes:
- Add FSP-M UPD 'TmeEnable'

TEST=Build and boot ADLRVP platform.

Change-Id: Ic5fad998e880e9302b068fc78c28074fa432f1ba
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46295
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14 03:38:49 +00:00
Duncan Laurie 6f58b991de soc/intel/tigerlake: Enable and use USB4 PCIe driver
This change enables the USB4/Thunderbolt common layer for Intel SOC,
and enables the Intel USB4 PCIe driver.  This moves the _DSD variables
from the DSDT into the SSDT and allows them to be configured for each
board if necessary.

Change-Id: I2564512d951046e015c148db42fdaf2d4b8b81dd
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44917
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14 02:55:35 +00:00
Duncan Laurie ce3a9740f1 soc/intel/common: Add SSDT generation for Intel USB4 PCIe ports
This driver will generate the ACPI _DSD for the USB4 PCIe root port
properties instead of using static ASL.

It assigns the USB4 port number and marks the port as external and
hotplug capable.

Change-Id: I7086b06346ce63fab6bef4077fb76ae1d30dc1eb
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44915
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14 02:55:20 +00:00
Duncan Laurie d6331e0884 soc/intel/common/block: Add common support for USB4/Thunderbolt
This common intel driver will add the requried ACPI _DSD entries for
enabled USB4/Thunderbolt ports' DMA devices the SSDT instead of using
hardcoded values in the DSDT.

Change-Id: Ic4a58202d4569cf092ea21a4a83a3af6c42ce9d0
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-14 02:54:58 +00:00
Tim Wawrzynczak 950305de0a soc/intel/common: Add PCI driver for USB4 ports
In order to enable SSDT generation for the DMA component of Intel USB4
ports, a PCI driver is required. This patch more or less adds a
`scan_bus` callback that will handle non-PCI devices downstream.

Change-Id: Ib9da051307b883eb99e500114378c9fd842ffc92
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-14 02:54:23 +00:00
Tony Huang 72464a4795 mb/google/puff/var/dooly: Enable Ambient Light Sensor (ALS)
Enable ALS ACPI devices for dooly.

BUG=b:168426118
BRANCH=puff
TEST=Ensure that ALS devices are enabled in ACPI tables.

Change-Id: Idd44d6ae1e7b62939fdfc3a0ab01924d2c1714aa
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-10-14 02:21:59 +00:00
Julius Werner 87feced195 sc7180: Enable bootblock compression
This patch enables bootblock compression on SC7180. In my tests, that
makes it boot roughly 10ms faster (which isn't much, but... might as
well take it).

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ibbe06eeb05347cc77395681969e6eaf1598b4260
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45855
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-13 22:41:19 +00:00
Julius Werner 6b8305d240 drivers: snsn65dsi86: Fix link rate parsing
DP link rates are reported in an array of LE16 values. The current code
tries to parse them as 8-bit which doesn't get very far, causing us to
always drop into the fallback path. This patch should fix the issue
(+minor whitespace cleanup).

BUG=b:170630766

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I1e03088ee2d3517bdb5dcc4dcc4ac04f8b14a391
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
2020-10-13 22:41:05 +00:00
Michael Niewöhner b73d2476dc soc/intel/common: rewrite and clarify the Legacy 8254 Timer Kconfig
The current Kconfig help text is confusing because it talks about
enabling the Kconfig for disabling a UPD for disabling power gating.

Rewrite and clarify the help text.

Change-Id: I9637c549db1ce29f259708f316852fc2ae9e7c38
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-13 22:21:36 +00:00
Felix Singer 63975f0e68 MAINTAINERS: Add Felix Singer to mb/clevo
Change-Id: I1d4547d02cf0d27db5c3b0c0ae46b730a198c814
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46316
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-13 22:15:56 +00:00
Angel Pons 587699822c nb/intel/ironlake: Put DMIBAR/EPBAR registers into separate files
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.

Change-Id: Ib1da100ba24de30256b3e80e380deb9c9ef4879e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-10-13 21:10:28 +00:00
Angel Pons 63c0dc9dba nb/intel/sandybridge: Improve cbmem_top_chipset calculation
Lock bit in TSEGMB register wasn't accounted for in `cbmem_top_chipset`.
Align down TSEG base to 1 MiB granularity to avoid surprises.

Change-Id: I74882db99502ae77c94d43d850533a4f76da2773
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-10-13 21:10:13 +00:00
Furquan Shaikh e31506cd51 drivers/wifi/generic: Do not generate SAR tables for non-Intel WiFi
CBFS SAR and SAR tables in ACPI are currently supported only by Intel
WiFi devices. This change adds a check in `emit_sar_acpi_structures()`
to ensure that the PCI vendor for the device is Intel before
generating the SAR tables.

BUG=b:169802515
BRANCH=zork

Change-Id: Ibff437893a61ac9557cff243a70230f101089834
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46040
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-13 18:45:00 +00:00
Furquan Shaikh 44f14509ed drivers/wifi/generic: Limit scope of ACPI-related functions to generic.c
This change limits the scope of `wifi_generic_fill_ssdt()` and
`wifi_generic_acpi_name()` to generic.c since they are not used
outside of this file anymore. Also, since there is no need to split
SSDT generator into two separate functions,
`wifi_generic_fill_ssdt_generator()` is dropped and `.acpi_fill_ssdt`
directly points to `wifi_generic_fill_ssdt()`.

BUG=b:169802515
BRANCH=zork

Change-Id: I2cbb97f43d2d9f9ed6d3cf8f0a9b13a7f30e922e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46038
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-13 18:44:46 +00:00
Furquan Shaikh 8262a2c718 drivers/{intel/wifi,wifi/generic}: Drop separate Intel WiFi driver
Currently, drivers/intel/wifi is a PCI driver (provides `struct
pci_driver`) as well as a chip driver (provides `struct
chip_operations`). However, there is no need for a separate chip
driver for the WiFi device since drivers/wifi/generic already provides
one.

Having two separate chip drivers makes it difficult to multi-source
WiFi devices and share the same firmware target without having to add
a probe property for each of these devices. This is unnecessary since
the WiFi driver in coreboot is primarily responsible for:
1. PCI resource allocation
2. ACPI SSDT node generation to expose wake property and SAR tables
3. SMBIOS table generation

For the most part, coreboot can perform the above operations without
really caring about the specifics of which WiFi device is being used
by the mainboard. Thus, this change drops the driver for intel/wifi
and moves the PCI driver support required for Intel WiFi chips into
drivers/wifi/generic. The PCI driver is retained for backward
compatibility with boards that never utilized the chip driver to
support Intel WiFi device. For these devices, the PCI driver helps
perform the same operations as above (except exposing the wake
property) by utilizing the same `wifi_generic_ops`.

This change also moves DRIVERS_INTEL_WIFI config to
wifi/generic/Kconfig.

BUG=b:169802515
BRANCH=zork

Change-Id: I780a7d1a87f387d5e01e6b35aac7cca31a2033ac
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46036
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-13 18:44:31 +00:00
Elyes HAOUAS 37509d7b0c mb/*/*/dsdt.asl: Drop useless comments in DefinitionBlock()
Change-Id: I1e0489ec6730760f74102cdd00e4aaa66975d69a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-10-13 18:27:23 +00:00
Elyes HAOUAS 2bfaabc610 mainboard/*/*/dsdt.asl: Make DefinitionBlock's AMLFileName uniform
Make output AML file name uniform.

Change-Id: Ic6cac4748a6159c695888b2737ada677d91f4262
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-13 18:27:13 +00:00
Elyes HAOUAS 90d00dea55 {src/mb,util/autoport}: Use macro for DSDT revision
Change-Id: I5a5f4e7067948c5cc7a715a08f7a5a3e9b391191
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-10-13 18:27:04 +00:00
Karthikeyan Ramasubramanian 2d49f220ea vendorcode/google/dram_part_num: Lower the severity of debug statement
DRAM part number may not be provisioned in CBI during early stages of
development. Logging the debug statement with error severity interferes
with some of the test tools. Lower the severity of debug statement to
BIOS_DEBUG.

BUG=b:170529094
TEST=Build and boot to ChromeOS in Drawlat.

Change-Id: Ib0c707ec6478060d6e18ea01cc467dfda00a6d42
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46299
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-13 18:26:40 +00:00
Wisley Chen 4744ca7d05 volteer: Create elemi variant
Create the elemi variant of the volteer reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.2.0).

BUG=b:170604353
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_ELEMI

Change-Id: I6013b6d8b28610a79f5ec49d373b2897799bffef
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-10-13 18:26:26 +00:00
Elyes HAOUAS c766d7ca56 mb/google/zork: Convert to ASL 2.0 syntax
Change-Id: I71ee54116ade4d6826dffc31ee879a70d3fc967f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2020-10-13 18:25:34 +00:00
Furquan Shaikh f223863261 wifi: Move addition of CBFS SAR file to wifi/generic/Makefile.inc
This change moves the addition of CBFS SAR file from
intel/wifi/Makefile.inc to wifi/generic/Makefile.inc to keep it in the
same sub-directory as the Kconfig definition.

BUG=b:169802515
BRANCH=zork

Change-Id: I7ee33232b6a07bbf929f3a79fabe89130fb6fa6f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-10-13 17:39:00 +00:00
Furquan Shaikh 5e0033987e drivers/{wifi/generic,intel/wifi}: Drop dependency on HAVE_ACPI_TABLES
This change drops the dependency of DRIVERS_WIFI_GENERIC on
HAVE_ACPI_TABLES as the driver provides operations other than the ACPI
support for WiFi devices. Since the dependency is now dropped, ACPI
operations in generic.c are guarded by CONFIG(HAVE_ACPI_TABLES).

BUG=b:169802515
BRANCH=zork

Change-Id: I16444a9d842a6742e3c97ef04c4f18e93e6cdaa9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46037
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-13 17:38:50 +00:00
Furquan Shaikh a266d1e63a mb, soc/intel: Switch to using drivers/wifi/generic for Intel WiFi devices
This change switches all mainboard devices to use drivers/wifi/generic
instead of drivers/intel/wifi chip driver for Intel WiFi
devices. There is no need for two separate chip drivers in coreboot to
handle Intel and non-Intel WiFi devices since the differences can be
handled at runtime using the PCI vendor ID. This also allows mainboard
to easily multi-source WiFi chips and still use the same firmware
image without having to distinguish between the chip drivers.

BUG=b:169802515
BRANCH=zork

Change-Id: Ieac603a970cb2c9bf835021d1fb0fd07fd535280
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-13 17:38:38 +00:00
Furquan Shaikh a1ddd2a15d drivers/wifi/generic: Add support for generating SMBIOS data
This change adds support in generic WiFi driver in coreboot to
generate SMBIOS data for the WiFi device. Currently, this is used only
for Intel WiFi devices and the function is copied over from Intel WiFi
driver in coreboot. This change is done in preparation for getting rid
of the separate chip driver for Intel WiFi in coreboot.

BUG=b:169802515
BRANCH=zork

Change-Id: If3c056718bdc57f6976ce8e3f8acc7665ec3ccd7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-13 17:38:26 +00:00
Elyes HAOUAS 288426d35c include/acpi/acpi.h: Add ACPI_DSDT_REV_1 macro
Change-Id: Ie044f786e5deae3a1317091de67dc03c74531bfb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-13 17:34:11 +00:00
Paul Menzel f710bf65dc superio/nuvoton/common: Collapse two if statements
There are more devices requiring this code, so avoid duplicating the if
block over and over.

Change-Id: Ib4f787e3c883b1fec941de77bc8e19ccf0d5224c
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45970
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-13 17:16:19 +00:00
Angel Pons a2118c7b54 mb/asrock/h110m/romstage.c: Drop invalid SPD addresses
Pictures on the internet show that the Asrock H110M-DVS (Kconfig.name)
only has two DIMM slots. Since the vendor's website advertises support
for dual channel memory, drop the SPD addresses for the second slot of
each channel. The result is the same as several other two-slot boards.

Change-Id: I4b62e9196bfa3a688016399d7e025ca995f3c12c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-13 10:32:23 +00:00
Angel Pons d89d086045 mb/asrock/h110m/romstage.c: Correct FSP-M UPDs
The DQ and DQS byte maps do not apply to DDR4 configurations, and the
RCOMP resistor and target values are not correct for SKL-S (or KBL-S).
Drop the byte maps and use RCOMP values for the correct platform type.

RCOMP resistor values for all non-socketed platforms are listed in the
Platform Design Guide, and also appear in schematics. For SKL-S, the
RCOMP resistors are on the CPU and their values have been confirmed
by measuring them on an i5-6400, and match the PDG values for SKL-H.

RCOMP target values can be guessed from Intel Document #573387 and some
of them are also present in datasheet volume 1, under DC specifications.

Change-Id: I699d46b9b516be8946367e6d9b24883ae1e78d03
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-13 10:32:12 +00:00
Jingle Hsu 5b24c6d304 mb/ocp/deltalake: Update SMBIOS type 9 information
Update Slot Designation strings and add SSD0_M2_Boot_Drive for config A.

TEST="dmidecode -t 9" to verify the results are expected.

Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com>
Change-Id: I3fc03a14ff7dc43d6ddf5aa36710c99dbc648afa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-13 10:16:50 +00:00
Benjamin Doron 2b2dc0c6ae acpi: Support MSDM table signature as SLIC
Accept an MSDM table (a newer revision of SLIC, with similar
ACPI structure) to advertise SLIC support.

Tested, Windows registers the digital license.

Change-Id: Ic3a1374c8a4880111a30662823c3be99008eedd3
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44995
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-13 10:16:22 +00:00
Angel Pons 12d48cdf67 src: Rename EM100Pro-specific SPI console Kconfig option
To avoid confusion with `flashconsole` (CONSOLE_SPI_FLASH), prefix this
option with `EM100Pro`. Looks like it is not build-tested, however.

Change-Id: I4868fa52250fbbf43e328dfd12e0e48fc58c4234
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-13 08:40:52 +00:00
Aaron Durbin 0b418bd287 lib/cbfs: deserialize cbfs_stage objects correctly
cbfstool emits cbfs_stage objects in little endian encoding.
However, big endian targets then read the wrong values from
these objects. To maintain backwards compatibility with existing
cbfs objects add in the little endian deserialization.

Change-Id: Ia113f7ddfa93f0ba5a76e0397f06f9b84c833727
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Marty E. Plummer <hanetzer@startmail.com>
2020-10-13 08:28:14 +00:00
Tony Huang f60ce24ad0 mb/google/puff/var/dooly: Update devicetree for audio and display configuration
1. Add speaker amplifier ALC1015

2. Enable dmic+ssp registers for speaker and camera DMIC

3. Correct I2C#2 to LVDS, I2C#3 to Touchscreen

BUG=b:170273526
BRANCH=puff
TEST=Build and check DUT function status

Change-Id: I5f6f19b40c6fcce8dca9b010ae97ea6e3eeb1473
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46289
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-13 06:12:06 +00:00
Tony Huang fb256a3c10 mb/google/puff/var/dooly: Update devicetree to remove unused devices
Remove unused device in Dooly
  no SD card reader
  no built-in LAN

BUG=b:170273526
BRANCH=puff
TEST=Build and check DUT function status

Change-Id: I8ab1e156031bfb4d5ea30048d8a10400f2a49411
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-10-13 06:11:44 +00:00
Tony Huang 51f016409a mb/google/puff/var/dooly: Update devicetree for USB configuration
Dooly has USBA*2 and USBC*2

BUG=b:170273526
BRANCH=puff
TEST=Build and check DUT function status

Change-Id: Icb66a8d5382ca9664e7f0b3660f446aeb3cf1dd3
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46126
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-13 06:11:16 +00:00
Tony Huang a6fba3b07c mb/google/puff/var/dooly: Update GPIO table for project change
Override unused device
SD card reader, built-in LAN

ALC1015 speaker amplifier SPK_AMP_ON

Update touchscreen/lvds gpio pin

BUG=b:170273526
BRANCH=puff
TEST=Build and check DUT function status

Change-Id: Ife14adf59609870abe9f4ba1eabe2573cb6e92dd
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-10-13 05:49:23 +00:00
Elyes HAOUAS 727fc397eb mb/intel/adlrvp/dsdt.asl: Use macro for DSDT revision
Change-Id: I6f4d0bf9adc1cce4942a16675a072ffea00bd2e0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46244
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-10-13 05:49:01 +00:00
Elyes HAOUAS 7f53ec6bfc include/acpi/acpi.h: Introduce ACPI_DSDT_REV_2 macro
This to replace DSDT revison number with macro so we can adapt all boards
at once if needed.

Change-Id: I9e92a5f408f69aa1a6801bc2cba8ddfe2180b040
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-13 05:46:32 +00:00
Elyes HAOUAS dcc1355de7 mb/{51nb/x210,razer/blade_stealth_kbl}/dsdt.asl: decrease DSDT revision from 0x5 to 0x2
DSDT revision 2 is used for ACPI v2 and greater.

Change-Id: Ia019358be6574db1b2b06a8a7d52ae996cf45571
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-10-13 05:46:08 +00:00
Subrata Banik 299689c85f mb/intel/latest mainboards: Get rid of power button device in coreboot
Refer to commit d7b88dc (mb/google/x86-boards: Get rid of power button
device in coreboot)

This change gets rid of the generic hardware power button from all
intel mainboards and relies completely on the fixed hardware power
button.

Change-Id: I8f9d73048041d42d809750fdb52092f40ab8f11f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-13 03:53:09 +00:00
Benjamin Doron bbb8123d66 soc/intel: Configure PAVP at compile-time
Expose configuration of Intel PAVP (Protected Audio-Video Path, a
digital rights protection/management (DRM) technology for
multimedia content) to Kconfig.

Per the FSP default, this was always being enabled previously.

Change-Id: I2aae741bb30e3be3c64324cd6334778bd271a903
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-12 23:11:04 +00:00
Matt DeVillier ceeeadb890 util/superiotool: Add EC registers for IT8728F
Add support for dumping registers, default values for
EC on ITE IT8128F. Taken from datasheet 'IT8728F V0.4.2'

Test: 'superiotool -d -e' on board with IT8728F Super IO

Change-Id: I7074b740565edf458d6894c066b61c083a657cb8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-12 21:43:12 +00:00
Angel Pons bda02b0f2b soc/intel/cannonlake: Align cosmetics with Ice Lake
By ironing out cosmetic differences between Cannon Lake and Ice Lake,
comparing actual code differences using a diff tool becomes simpler.

Tested with BUILD_TIMELESS=1, Prodrive Hermes remains identical.

Change-Id: I4d9f882f9f8af1245e937b0d47bc7e993547365f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2020-10-12 20:59:17 +00:00
Michael Niewöhner 8c8b34996d mb/clevo/l140cu: clean up memcfg
The DQ and DQS byte maps do not apply to DDR4 configurations, thus
simply drop them.

Also drop ECT, as it's already initialized to zero and can't be used on
DDR4 anyway.

Further, trim down all the meaningless and/or wrong comments.

Change-Id: I32f1b7bb46eaaf0f0ecad1df310f5de988f64c85
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46249
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12 19:20:44 +00:00