Commit Graph

32467 Commits

Author SHA1 Message Date
Wonkyu Kim 8d6eae5d6d mb/tglrvp: update gpio pin mux for NVMe
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board from NVMe

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ib4b85db667c27d266d2ed5a4aa4f4dffa3dd527e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38286
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-17 06:28:52 +00:00
Aaron Durbin 5abeb06a73 drivers/spi/spi_flash: organize spi flash by sector topology
By grouping the spi flash parts by their {vendor, sector topology}
tuple one can use a common probe function for looking up the part
instead of having per-vendor probe functions. Additionally, by
grouping by the command set one can save more space as well. SST
is the exception that requires after_probe() function to unlock the
parts.

2KiB of savings in each of verstage, romstage, and ramstage
on Aleena Chrome OS Build.

Change-Id: I9cc20ca0f3d0a1b97154b000c95ff2e7e87f3375
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-01-17 05:49:09 +00:00
Aaron Durbin a6c73c8987 drivers/spi/spi_flash: introduce common spi_flash_part_id object
To further drive to a common approach for describing the spi flash
parts in the drivers add spi_flash_part_id object. All the drivers
are updated to utilize the new object. Additionally, the driver_private
is also not needed in the spi_flash object.

A Chrome OS build of Aleena provides 960 byte saving of text. A subsequent
patch will save more memory.

Change-Id: I9c0cc75f188ac004ab647805b9551bf06a0c646b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-01-17 05:48:52 +00:00
Aaron Durbin ae43f32458 drivers/spi/spi_flash: remove continuation byte support
There was code to handle the case of continuation bytes for identifying
the manufacturer id to a jedec rdid command. However, all the parts that
currently supported have this defined to be 0. Remove the unused
continuation byte support.

Change-Id: Ia7c63162e4ef9dc46ef916ca8c31ebd721cbeca7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38361
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-17 05:48:24 +00:00
Krishna Prasad Bhat 1bfa2c79f8 /mb/google/hatch/variants/helios: Remove MAX98357A devicetree entry
Helios does not have MAX98357A speaker amplifier, so remove the devicetree
entry.

BRANCH=firmware-hatch-12672.B

Change-Id: Id02410553f018385d407086b2f9bc3ee1e7a5f40
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Signed-off-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Shelley Chen <shchen@google.com>
2020-01-16 19:21:25 +00:00
Subrata Banik 2fff391513 soc/intel/{cnl,icl,skl, tgl}: Move SOC_INTEL_COMMON_BLOCK_THERMAL into SoC specific Kconfig
This patch moves common pch code SOC_INTEL_COMMON_BLOCK_THERMAL Kconfig selection
into SoC specific Kconfig selection as PCH thermal device is not available
with latest PCH (i.e. TGP and JSP).

Also added TODO for TGL thermal configuration as applicable.

TEST=Able to build and boot TGL RVP with this CL

Change-Id: Ibce17cc9f38fb666011ccd8f97bee63033ff5302
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38444
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-16 16:28:09 +00:00
Aaron Durbin 937931ea04 drivers/spi/spi_flash: add missing status() command callbacks
The adesto, amic, atmel, and stmicro spi flash drivers didn't have
the status() call back. These parts do support the status command
retrieval. Fill them in accordingly.

Change-Id: Ie0e63bec844b8e01e292ef8c4df707494df02e69
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-16 15:21:35 +00:00
Aaron Durbin f584f19efc drivers/spi/spi_flash: separate out protection ops
Put the write protection into its own object. This allows
for easier future reuse of objects in future consolidation
patches. It's also possible to eliminate the code implmementing
these in the future if the platform doesn't require it. For now
leave current behavior as-is.

The names of the callbacks were shortened as they are now in
the spi_flash_protection_ops object which is a new field in the
spi_flash object.

Change-Id: I2fec4e4430709fcf3e08a55dd36583211c035c08
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-16 15:21:08 +00:00
Aaron Durbin cb01aa586f drivers/spi/spi_flash: assume spi_flash read callback exists
spi_flash_erase() and spi_flash_write() already assume their
respective callbacks are supplied in the spi_flash_ops object.
Make the same assumption in spi_flash_read(). In order to do this
the spi_flash_ops objects from the drivers need to reference the
the previously used fallback read command, spi_flash_read_chunked().
This function is made global and renamed to spi_flash_cmd_read() for
consistency.

By doing this further dead code elimination can be achieved when the
spi flash drivers aren't included in the build.

A Hatch Chrome OS build achieves a further text segment reduction of
0.5KiB in verstage, romstage, and ramstage.

Change-Id: I7fee55e6ffc1983657c3adde025a0e8c9d12ca23
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-16 15:20:49 +00:00
Paul Menzel 56258ff92b autoport: Improve formatting of EC ASL code
Change-Id: I7fe3e798346e760eebb357f20e55ee1a71a1e31a
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-01-16 13:21:56 +00:00
Felix Held aa30d6237e nb/intel/sandybridge: sort LANEBASE_* defines by their address
Change-Id: I32fcd36298f41d3b6d8b3e16b6641b9404220461
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-16 08:40:10 +00:00
Felix Held fb19c8aae0 nb/intel/sandybridge: add macros for byte lane register offsets
This patch doesn't change the resulting binary of a timeless build.

Change-Id: Ife0e70699df3efa162f8f6c0fd8c2928887fda2d
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-16 08:40:01 +00:00
Felix Held 283b446612 nb/intel/sandybridge: refactor code around lane_base[]
This is to get a uniform format that matches the macros added in the
next patch, so that said follow-up patch won't change the output binary.

lenovo/x230 still boots with this patch.

Change-Id: Ibfbeb847cab09427a57bef3cbd2069036de5a21e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-16 08:37:53 +00:00
Piotr Kleinschmidt 941c9ac074 mb/pcengines: Enable SuperIO LDN 0xf for GPIO soft reset
LDN 0xf keeps registers with open-drain configuration of the GPIO.
Enabling the LDN is required for proper GPIO soft reset operation
by the SuperIO driver.

Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ia769e3d8e66015297942bddf328a6fde0bb27ce6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-01-15 18:54:40 +00:00
Piotr Kleinschmidt b52f7c7c46 superio/nuvoton/nct5104d: Add soft reset GPIO functionality
So far, only hard power off could reset GPIOs state to defaults:
IN, Open-drain. Now, defaults are set with every boot to ensure
that GPIOs are not in unknown/unwanted state.

Change-Id: I67878dbab2ddf0deaaa8f5d79416368c6164ba1d
Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-01-15 18:54:33 +00:00
Aaron Durbin bd467d1481 soc/intel/common/block/fast_spi: don't include all spi flash drivers
The fast spi driver implements hardware sequencing which abstracts away
the underlying spi flash commands in the hardware block. It also has its
own spi flash probe function to intercept the spi flash ops. As such it's
not necessary to include all spi flash drivers.

On a hatch Chrome OS build this saves 9.5KiB of text in each of verstage,
romstage, and ramstage.

Change-Id: Ifb1b962cde3a6a02353ddf83279234057a9ec2fa
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-15 16:34:31 +00:00
Aaron Durbin 3e7f006280 drives/spi/spi_flash: add option to not select all drivers
Add a new Kconfig option, SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS,
to make it easier for other parts of the code base to indicate that
all spi flash drivers should not be included.

Change-Id: Ibf2c4f1d2b8a73cff14bb627ddf759d7970920ea
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-15 16:34:13 +00:00
Ravi Sarawadi fbd6869f91 soc/intel/tigerlake: Update header files
Modify header files to update/include tigerlake:
  - IOMAP BARs according to silicon reference code
  - Update Serial IO devices according to PCH EDS
  - Add board types

BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I185f2c22c54a6ae386527069606abb52cce1ec80
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-01-15 14:30:07 +00:00
Paul Menzel 607ee30403 autoport: Use HTTPS URLs
Update the two flashrom URLs to use HTTPS. All other URLs are already
using HTTPS.

Change-Id: I8e9861b2748289522ab418960a463ae55ab0d2d3
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-01-15 14:24:19 +00:00
Felix Held 3b90603668 nb/intel/sandybridge: refactor lane_registers[]
Rename array and use defines for the values.

The patch doesn't change the resulting binary when using BUILD_TIMELESS=1

Change-Id: I774373d231a0f4a2fe82ab7c6f1318fc56bcc678
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38405
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-15 13:21:37 +00:00
Felix Held 331d71bad8 nb/intel/sandybridge: drop LyCx(r, x, y) macro
LyCx(r, x, y) was a duplicate of the CxLy(r, x, y) with different order
of computation, so that the big refactoring doesn't change the output
binary of a timeless build. Now this workaround can be dropped.

Tested on lenovo/x230: still boots

Change-Id: I251b4dd383f954b27f392190092e06a9a06668e2
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-15 13:21:30 +00:00
Matt DeVillier c84f73aec5 mb/google/slippy: update VBT
The current BIOS-extracted VBT breaks backlight control
with Tianocore, so replace it with one that does. Settings
were exported using Intel BMP tool and the overlayed onto
a GOP-format (vs BIOS format) VBT file.

Test: boot google/wolf with both SeaBIOS and Tianocore payloads,
verify backlight control functional under both Linux and Windows.

Change-Id: Id6281c8dfb6e0001be8c4d9be1013f2d4bbb5880
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-01-15 13:12:38 +00:00
Angel Pons b31d1d76e7 nb/intel/sandybridge: Repurpose HOST_BRIDGE macro
There are more instances of PCI_DEV(0, 0, 0), so use the macro for them.
Note that the resulting code with PCI_DEVFN(0, 0) is weird. It shall be
replaced with config_of_soc() in a follow-up.

Tested with BUILD_TIMELESS=1, resulting binary is identical.

Change-Id: Ia50965a108a734d192b584291a0796a2f2bc3a55
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38338
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-15 13:09:30 +00:00
Felix Held bfafa9e037 Documentation: document non-Docker sphinx installation and usage
Also update the known-good versions of the needed tools.

Change-Id: I0f63860beb0a8a00360752318236e302c7170977
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37952
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-14 18:29:41 +00:00
Karthikeyan Ramasubramanian 7bc90bce36 mb/google/dedede: Add dedede mainboard
Add mainboard stubs for Dedede. More functionalities will be added later.

BUG=b:144768001
TEST=Build test.

Change-Id: I7e6cb8adaee7b6bb95e9a96f96466646a78bd0fc
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38277
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-14 18:28:50 +00:00
Wonkyu Kim 23140933b7 mb/intel/tglrvp: Update Kconfig
Updating Kconfig to add Chrome OS support with
both internal and external EC

BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ia63c06e3b4b4effcace7a8458b1066a615de2008
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38148
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-14 18:27:21 +00:00
Ravi Sarawadi ebb2d3c8b7 mb/intel/tglrvp: Add initial mainboard code
This is a initial mainboard code aimed to serve as base for
further mainboard check-ins.

This is a copy patch from icelake_rvp as on commit ID:
I64db2460115f5fb35ca197b83440f8ee47470761

Below are the changes done over the copy patch:

 1. Rename "Icelake" with "Tigerlake".
 2. Replace "icelake_rvp" with "tglrvp".
 3. Rename "icl" with "tgl".
 4. Remove unwanted SPD file, add empty SPD as
    placeholder.
 5. Replace "soc/intel/icelake" with "soc/intel/tigerlake".
 6. Empty romstage_fsp_params.c, to fill it later with
    SOC specific config.
 7. Empty GPIO configuration, to be filled as per board.
 8. Change copyright year to 2019.
 9. Add board support namely BOARD_INTEL_TGLRVP_UP3
 10. Replace icl_u and icl_y variant with tglrvp variant.
 11. Remove basebord gpio.c and rely on variant override.
 12. Remove HDA verb table and config support.

Changes to follow on top of this:
 1. Add correct memory parameters, add SPDs.
 2. Clean up devicetree as per tigerlake SOC.
 3. Add GPIO support.
 4. Update chromeos.fmd to make 32MB BIOS region.
 5. clean up and make empty devicetree setting

TEST=Build tigerlake rvp board

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I86ada611de1cf28a1b872eea35cf41c0dc1c57f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-01-14 18:26:02 +00:00
Yu-Ping Wu a26986e1a7 libpayload: cbgfx: Support drawing a box with rounded corners
A function draw_rounded_box() is added to draw a box with rounded
corners. In addition, this function is different from draw_box() in 2
ways:
- The position and size arguments are relative to the canvas.
- This function supports drawing only the border of a box (linear time
  complexity when the thickness is fixed).

BRANCH=none
BUG=b:146105976
TEST=emerge-nami libpayload

Change-Id: Ie480410d2fd8316462d5ff874999ae2317de04f9
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-01-14 18:25:36 +00:00
Hung-Te Lin 8eef3bf3ca mb/google/kukui: Support panels using ANX7625
For Kukui followers using ANX7625 eDP bridge to access panel.

BUG=b:140132295
TEST=make # board = kukui

Change-Id: I7dc9c68d076fd0ba4e963cde9414d25c17b332cb
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-01-14 18:24:58 +00:00
Eric Lai 40d816e964 mb/google/drallion: Enable dynamic sar
Drallion will use two sar table for tablet and clam shell mode.

BUG=b:140469407
TEST=Build and check the config has enable
BRANCH=none

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I0367741e795a3b00c490ecb1972d22b9f454134f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2020-01-14 18:23:09 +00:00
Keith Hui 9b4b33ac37 sb/intel/i82371eb: Add PIIX4 definitions
These new definitions will be used by two other changes.

Change-Id: I242244c444f36af188c871dce037a7a9250206cd
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38367
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-14 18:19:14 +00:00
Kyösti Mälkki f555a58abc sb/intel/common: Declare common smbus_base() and enable_smbus()
This avoids including platform-specific headers with different
filenames from common code.

Change-Id: Idf9893e55949d63f3ceca2249e618d0f81320321
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-14 18:18:26 +00:00
Kyösti Mälkki 542fa6de38 soc/intel/baytrail: Add SOUTHBRIDGE_INTEL_COMMON_SMBUS
Change-Id: Ie026b8c57046d951752158fd28277e338ed1421c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38236
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-14 18:16:48 +00:00
Kyösti Mälkki 8dd2d485b8 intel/nehalem,ibexpeak: Move enable_smbus() call
Change-Id: I6e43f7696b289ce9e0319afdcc73889ddabd4db1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-01-14 18:13:34 +00:00
Kyösti Mälkki ffa520fc13 intel/sandybridge,bd82x6x: Move enable_smbus() call
Change-Id: Icc6b572fea0c2097a7ed19b3f76c1e658cf32a9a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-01-14 18:13:24 +00:00
Kyösti Mälkki 1cfafe25e3 intel/{gm45,x4x},i82801{ix|jx}: Move enable_smbus() call
Change-Id: Idc7631abb550b31af722ccf3b69afdc01fdb616e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38268
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-14 18:13:15 +00:00
Kyösti Mälkki 7adc370dc7 intel/{i945,pineview},i82801gx: Move enable_smbus() call
Change-Id: I7a9e613f9a142e04030672f85ea80c56151be3c5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38296
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-14 18:11:01 +00:00
Kyösti Mälkki a28ee1b186 drivers/pc80/rtc: Clean up some POST_CODE_EXTRA use
Change-Id: I5ecfa0860a28547f76a72592a8d07bca67822217
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38188
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-14 18:09:30 +00:00
Kyösti Mälkki 10bc806ab3 console/post: Split parts to arch/
Both IO port and cmos are currently arch/x86 only features.

Change-Id: I010af3f645c0be38dd856657874c36103aebbdc2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38187
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-14 18:08:49 +00:00
Elyes HAOUAS 40f539f8c4 crossgcc: Upgrade cmake to version 3.16.2
Change-Id: I2012f0adcb348a3ea6c50c361a49a0a600d3db3d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-01-14 17:59:51 +00:00
Elyes HAOUAS eda12901fa util/crossgcc: Add comment on IASL version
Change-Id: I81c6f4134610bcd35e173cdb002ef821788b0538
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-01-14 17:59:33 +00:00
Jonathan A. Kollasch a1114f608b autoport: Add Xeon E3-1200 v2 memory controller ID
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Change-Id: Ic5f18669a04397f570d49c1ff056cd90b3eb04a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-01-14 17:02:30 +00:00
Angel Pons 63ae8dec79 nb/intel/sandybridge: Drop 'or zero' instances
Change-Id: Icd0dfdf311ac141992ec6a6026ca92e54e8d2094
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-14 12:39:37 +00:00
Subrata Banik 2883f7af94 soc/intel/cannonlake: Fix ASL compilation remarks
This patch fixes below ASL compilation remarks

1. dsdt.asl    495:   Method (_DSM, 4)
Remark   2119 -              ^ Control Method marked Serialized (Due to use of Switch operator)
2.
dsdt.asl    721: Name(GPMB, Package(5) {0})
Remark   2063 -                    ^ Initializer list shorter than declared package length

Change-Id: Iabd6c39025713dda7aa69cb479f003fbec8855b3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-14 07:26:19 +00:00
Joe Moore 159cd3f421 vc/amd/agesa: Fix out of bounds read
ByteLane is used unitialized from prior for statement,
creating a potential out-of-bound read of RxOrig[MaxByteLanes].
PassTestRxEnDly[MaxByteLanes] never appears as rvalue; all for
loops have ByteLane < MaxByteLanes exit condition.

Change-Id: Icd18a146aba6b6120d37518d8c40c7efbc05afa3
Signed-off-by: Joe Moore <awokd@danwin1210.me>
Found-by: Coverity CID 1241804
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
2020-01-13 11:22:40 +00:00
Elyes HAOUAS 04e49425ec mb/packardbell/ms2290/acpi_tables: Remove unneeded includes
Change-Id: Iba380cf96991c9e1fec96aa3d793818524388897
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-13 11:21:40 +00:00
Elyes HAOUAS db10892a17 mb/lenovo/thinkcentre_a58/acpi_tables: Remove unneeded includes
Change-Id: I8f8e43d0f146b1050eb68da197504441b60a4120
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-13 11:21:24 +00:00
Elyes HAOUAS 9e17b749d2 mb/intel/*/acpi_tables.c: Remove unneeded includes
Change-Id: I3b110ab749992d1c1793b1d4de43c1d2e8ca15ac
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-13 11:21:14 +00:00
Elyes HAOUAS 615ef58a29 mb/asus/*/acpi_tables.c: Remove unneeded includes
Change-Id: Iba39673a81f235204d6ae9fe9e18239e5b81b17f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-13 11:20:51 +00:00
Elyes HAOUAS 7a4e5e3988 mb/gigabyte/ga-g41m-es2l/acpi_tables.c: Remove unneeded includes
Change-Id: I4b3b2d801698305dc6c214c58d367772ea2096a3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/26894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-13 11:20:24 +00:00