Commit Graph

38707 Commits

Author SHA1 Message Date
Roger Lu a5f472bf57 soc/mediatek/mt8192: add spmfw loader
This patch adds support for loading spm firmware from cbfs to spm sram.
Spm needs its own firmware to enable spm suspend/resume function which
turns off several resources such as DRAM/mainpll/26M clk when linux
system suspend.

BUG=b:159079649
TEST=suspend with command `powerd_dbus_suspend` and
     wake up the DUT by powerkey

Signed-off-by: Roger Lu <roger.lu@mediatek.com>
Change-Id: I6478b98f426d2f3e0ee919d37d21d909ae8a6371
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-12-10 03:22:36 +00:00
Yidi Lin eb69dd60ef soc/mediatek/mt8183: Use mtk_init_mcu to init SSPM
Use mtk_init_mcu API to load and run sspm firmware.

TEST=emerge-kukui coreboot

Change-Id: I63c4b99342bdebb2a94cbf0c6380b0a6817853e7
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-12-10 03:22:24 +00:00
Yidi Lin c221d56478 soc/mediatek/mt8183: Add DRAM_DMA section
mtk_init_mcu uses DRAM_DMA section as CBFS buffer.
The change "mediatek/mt8183: Remove DRAM_DMA section" is reverted
for using mtk_init_mcu.

On mt8173 and mt8192, this region is used by DMA hardware and is
marked as non-cacheable resource. On mt8183, this region is reserved
as CBFS buffer, so it is not necessary to be marked as non-cacheable
resource.

Change-Id: I7ce9f68883e2787ee7f3c5066f4c47c5ca315633
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-12-10 03:22:01 +00:00
Yidi Lin 7ba3775114 soc/mediatek/common: Add common API for loading firmwares
Add mtk_init_mcu to load the firmware to the specified memory address
and run the firmware. This function also measures the load time and the
blob size. For example:

mtk_init_mcu: Loaded (and reset) dpm.pm in 15 msecs (14004 bytes)

Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: Ie94001bbda25fe015f43172e92a1006e059de223
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-12-10 03:21:19 +00:00
Michael Niewöhner 6bc1296cbd mb/supermicro/x11ssm-f: enable AER for PCIe root ports
Follow vendor and enable Advanced Error Reporting for PCIe root ports.
This enabled the Linux AER driver, which handles PCIe error conditions.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I9d9b5afca0ca891e2812445db1d42a46ba16199e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48369
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10 02:27:53 +00:00
Michael Niewöhner 0bae5a72c5 mb/supermicro/x11ssm-f: add subsystem ids to PCI ports and devices
Add the subsystem ids to PCI ports and devices, which were dumped on
vendor firmware using `lspci`.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: Idb36c5c72e1b0b8303439ae5dce772822f551d2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48368
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10 02:27:40 +00:00
Michael Niewöhner fb7a06b5b7 mb/supermicro/x11ssm-f: enable LTR for all root ports
Follow vendor and enable LTR on all root ports to optimize for devices'
latency requirements and also optimize power management while preventing
failure due to wrongly guessing idle states, which happens without LTR.

Tested successfully. No errors show up in dmesg.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I8f72087c71e291d2412dc7b3e16ee7f419e2ca0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48367
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10 02:27:08 +00:00
Michael Niewöhner ffa2f4fb35 mb/supermicro/x11-lga1151-series: drop HAVE_ACPI_RESUME
All X11 boards currently supported have Intel SPS without support for
S3/S5. Thus, drop it from Kconfig.

Note: not all X11 boards are server boards. When a X11 desktop or
workstation board should be added, this can be selected by the boards,
where S3/S5 work.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: Ie75c9217078d38c42eba2b30c078b8bb1c2ca694
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-10 02:26:58 +00:00
Michael Niewöhner f105c4164e mb/supermicro/x11ssm-f: (re)configure unconnected pads
Correct unconnected pads that are configured different currently by
copying vendor configuration while porting the board.

Add internal pull resistors to all unconnected pads, that do not have an
external pull resistor, to prevent floating.

The pads have been determined by dissecting a dead board. This commit
only changes pads, that are not connected at all and don't have any via,
so we can be absolutely sure there is no other connection.

Change-Id: I991fe270b42f430f7447712236e0f80b3d5bba2a
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-10 02:26:22 +00:00
Michael Niewöhner 7f623f8e46 mb/supermicro/x11ssm-f: (re)configure and document various pads
(Re)configure various pads found by dissecting a dead board and vendor
firmware, as well as the BMC firmware:

- GPP_B14: input connected to jumper JBR1 - could be used to implement
  "BIOS Recovery" ("Top-Block Swap") functionality; external pull-up

- GPP_C20: output to BMC alert CPU_THROTTLED# - can be used to notify
  the BMC about a thermal throttling event. Not implemented in vendor
  firmware.

- GPP_C23: input connected to the CPU's CATERR# output; external pull-up
  Not actively used by vendor firmware.

- GPP_D1: output connected to on-board and front panel power LEDs

- GPP_D18: output connected to PERST# of both CPU PCIe Slots. Can be
  used for testing/debugging only, since it resets both slots at once.
  Not actively used by vendor firmware.

- GPP_D19: output connected to PERST# of both PCH PCIe Slots. Can be
  used for testing/debugging only, since it resets both slots at once.
  Not actively used by vendor firmware.

- GPP_D22: input connected to the BMC enable/disable jumper JPB1; Will
  be used later in CB:48096 and CB:48097; external pull-up

- GPP_G0 - GPP_G3: dedicated/integrated CPU switching; probably not
  useful, since the IGD is not connected to any ports on this board.
  External pulls ensure correct function of a dGPU even without driving
  the gpios. Not used by vendor firmware.

- GPP_G12 - GPP_G16: inputs for binary SKU_ID; external pulls

- GPP_G20: PWRFAIL# input from JPI2C1 (pin 3); external pull-up; Not
  used by vendor firmware.

Also add comments for documentation. While at it, mark ME-owned pads as
reserved.

Change-Id: I9f9328e9ce6f7e291b171f776bb98bc617b64b93
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-12-10 02:25:13 +00:00
Felix Held 5d7fa16c5c soc/amd/picasso/reset: use port and bit defines from cf9_reset.h
The register name and the name of one bit are slightly different, but
have the same functionality.

Change-Id: I025f1c7b2c7643afe245f2275ae6ef45e64b951a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48487
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10 01:22:06 +00:00
Felix Held 1e63e361c6 soc/amd/picasso/reset: remove leftover PCI includes
On Stoneyridge some PCI registers were accessed in this compilation
unit, but on Picasso this is no longer the case.

Change-Id: Ifbf65f9724a14d4847af98930759c865453775b4
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48486
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10 01:21:53 +00:00
Xi Chen 63eb64be26 Makefile.inc: Fix empty output when processing C struct files in CBFS
When passing $(@) to eval command, $(@) is replaced by empty string,
Also, the $(@) in cbfs-files-processor-struct is a temporary file name,
so we should quote it by an extra '$' or use the arg ($1 or $2)
directly.

For example:
  cbfs-files-processor-struct= \
      $(eval $(2): $(1) $(obj)/build.h $(KCONFIG_AUTOHEADER); \
		# **  $(@) is empty string instead of $(2)   **
		printf "    CC+STRIP   $(@)  \n"; \
		# **  $(1) contains the name of source file  **
		printf "    CC+STRIP   $(1) \n"; \
	......)

Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: Id6a66e25d7dfe8fe6410e517593ed22a438d2f82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48201
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09 23:18:10 +00:00
Sheng-Liang Pan 5c08c31775 mb/google/volteer/variant/volta: add Synaptics touchpad.
add new Synaptics touchpad for volta.

BUG=b:174802144
TEST=emerge-volteer coreboot and check touchpad function work.

Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I7fc8d08b8b2229ca9252618f159fc9c6f91f9d7f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48395
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09 21:54:40 +00:00
Felix Held 10252035ce soc/amd/cezanne: print APU family and model in bootblock_soc_init
Change-Id: I457188c905167affc1ebcea835a36df822ecb23c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-09 18:44:51 +00:00
Felix Held 153f92adbe soc/amd/cezanne: add basic early FCH initialization to bootblock
Change-Id: I1c6d32a5498a7adcee3c8c3145f85e9dba26bf7e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-09 18:44:40 +00:00
Felix Held 4be064a1d8 soc/amd/cezanne: add common SMBus code to build
Since the IOAPIC in the FCH gets set up in the SMBus code, also select
IOAPIC in Kconfig.

Change-Id: I4163e28ca9e68e5fd36421d90aafc20bce43a174
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48474
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09 18:42:59 +00:00
Julius Werner 34cf073220 cbfs: Allow mcache to be found after the first lookup
This patch addresses the same problem as CB:48429, but hopefully this
time correctly. Since the mcache is not guaranteed to be available on
the first CBFS lookup for some special cases, we can no longer treat it
as a one-time fire-and-forget initialization. Instead, we test
cbd->mcache_size to check if the mcache has been initialized yet, and
keep trying on every lookup if we don't find it the first time.

Since the mcache is a hard requirement for TOCTOU safety, also make it
more clear in Kconfig that configurations known to do CBFS accesses
before CBMEM init are incompatbile with that, and make sure we die()
rather than do something unsafe if there's a case that Kconfig didn't
catch.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I4e01e9a9905f7dcba14eaf05168495201ed5de60
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-09 17:44:52 +00:00
Julius Werner d2777b8485 Revert "cbfs: Skip mcache in post-RAM stages before CBMEM is online"
This reverts commit b652aaef99. It was
dumb and didn't actually fix anything.

Change-Id: I074135dd12face1226105e0706c78ae8ecba18e0
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-09 17:44:28 +00:00
Felix Held 4911c3e352 soc/amd/cezanne: call bootblock_main_with_basetime in bootblock_c_entry
Change-Id: Iaac661fcb7581236ace4b5bf057b3e70289f1c8b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-09 17:42:08 +00:00
Felix Held 0645347d0b soc/amd/picasso,stoneyridge: drop unused BIOSRAM offset defines
The two Socs don't use this functionality and biosram.c in the common
code is the only place where those defines are used, but it doesn't
include soc/iomap.h and has its own definitions instead.

Change-Id: I973df4ab39a94e89ea2ed6ffb639c5a85b8df456
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-09 15:28:12 +00:00
Raul E Rangel f56b784227 soc/amd/picasso: Rename SD_EMMC_EMMC_DDR_52 to SD_EMMC_EMMC_DDR_104
The number at the end actually means the max MiB/s. So 52 MHz clock @ 8x
data width, sampled on each clock edge = 104 MiB/s.

According to JEDEC Standard No. 84-B51A (JESD84-B51A), maximum bandwidth
& clock frequency for various MMC bus speed modes are (at x8 bus width):
MMC_Legacy: 26 MB/s at 26 MHz Single Data Rate (SDR)
MMC_HS: 52 MB/s at 52 MHz SDR
MMC_DDR52: 104 MB/s at 52 MHz Dual Data Rate (DDR)
MMC_HS200: 200 MB/s at 200 MHz SDR
MMC_HS400: 400 MB/s at 200 MHz DDR

BUG=b:159823235
BRANCH=zork
TEST=build zork

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7818d8cb5ed5974c60a900477a0aa2ecc904db0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48309
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09 14:25:19 +00:00
Kyösti Mälkki b3621f811d soc/amd: Remove Kconfig BOOTBLOCK_ADDR
Due the location of X86_RESET_VECTOR, the anchor point
for linking the bootblock is at the end, which equals
ROMSTAGE_ADDR.

Change-Id: I2d25911582393c9a10fd3afa1a484eda2604d95a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-09 14:23:43 +00:00
Kyösti Mälkki 8d187f4d22 soc/amd: Remove Kconfig X86_RESET_VECTOR
The architectural requirement is for the address to be
located at the end of bootblock -0x10 bytes, so the
definition was redundant with other Kconfig variables.

Change-Id: Ia014470cfadf0b401a12a2de6dce3b1fc1862137
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-09 14:23:31 +00:00
Srinidhi N Kaushik 8dcd62d705 soc/intel/common/dmi: Add support for locking down SRL
This change adds support to lock down the DMI configuration
in dmi_lockdown_cfg() by setting Secure Register Lock (SRL)
bit in DMI control register.

BUG=b:171534504

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I98a82ce4a2f73f8a1504e5ddf77ff2e81ae3f53f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48258
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09 14:23:22 +00:00
Srinidhi N Kaushik 876b422641 soc/intel/common/dmi: Move DMI defines into DMI driver header
Move definitions of DMI control register and Secure Register
Lock (SRL) bit into common/block/dmi driver header file.

BUG=b:171534504

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Iefee818f58f399d4a127662a300b6e132494bad0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48257
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09 14:23:15 +00:00
Furquan Shaikh 640f0ce93f mb/google/volteer: Reorganize FMAP
This change reorganizes FMAP for volteer to make use of the lower
16MiB of the SPI flash for RW_SECTION_A and RW_MISC in addition to
RW_LEGACY. This is now possible because TGL supports memory mapping of
BIOS region greater than 16MiB.

Following changes are made in chromeos.fmd as part of this:
1. Move RW_SECTION_A and RW_MISC to lower 16MiB.
2. Reduce size of RW_LEGACY to 2MiB since we longer need to use it as
a placeholder in the lower half of the SPI flash.
3. Reduce size of RW_ELOG to 4KiB as coreboot does not support a
larger region for ELOG.
4. Increase WP_RO to 8MiB to allow larger space for firmware
screens. GBB size is thus increased to 448KiB.

BUG=b:171534504

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I0c3c0af94183a80c23d196422d3c8cf960b9d9f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-12-09 14:23:06 +00:00
Furquan Shaikh ba75c4cc49 soc/intel/tigerlake: Enable support for extended BIOS window
This change enables support for extended BIOS window by selecting
FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW and providing base and size of the
extended window in host address space.

BUG=b:171534504

Cq-Depend: chromium:2566231
Change-Id: I039155506380310cf867f5f8c5542278be40838a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
2020-12-09 14:22:58 +00:00
Stanley Wu f078ce1e46 mb/google/dedede: Update Boten GPIO setting for PEN detection.
AP_PEN_DET_ODL isolated by a diode and need to pull up internally.

BUG=b:160752604
BRANCH=dedede
TEST=Build and confirm waveform by google EE parter.

Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I85f3d0209094af07891a5c0cc218443da586e6e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48294
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09 13:31:36 +00:00
John Su e1c7cd9fb7 mb/google/zork/var/vilboz: Update telemetry settings
Update telemetry settings.

VDD Slope : 32643 -> 26939
VDD Offset: 208   -> 125
SOC Slope : 22742 -> 20001
SOC Offset: -83   -> 168

BUG=b:171668654
BRANCH=zork
TEST=1. emerge-zork coreboot
     2. pass AMD SDLE test report

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Ic63e069310aa4a66cd4c9058790dbed37e6967f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48288
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09 10:19:23 +00:00
V Sowmya a6051440e2 mb/intel/adlrvp: Add PMC.MUX.CONx device config for Conn2
This patch adds the PMC MUX and CONx devices for adlrvp for
conn2.

BUG=b:170607415
TEST=Built and booted adlrvp. Verified the PMC.MUX CONx objects
in SSDT tables.

Change-Id: I52afbd429750cfa416f4ed93aeb1be590f8c3a5c
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48230
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09 08:22:16 +00:00
Tim Chen 2082196e95 mb/google/dedede/var/metaknight: Support Elan/Synaptics touchpad
Add Elan and Synaptics touchpad settings.

BUG=b:169813211
BRANCH=None
TEST=build metaknight firmware

Change-Id: Ice0a86cd5610db269d44acb1d51cb652110d9b0c
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raymond Wong <wongraymond@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-12-09 06:55:53 +00:00
Tim Chen 187f9d157a mb/google/dedede/var/metaknight: Add audio related settings
Add HDA,speaker codec and speaker amp settings.

BUG=b:169813211
BRANCH=None
TEST=build metaknight firmware

Change-Id: I9b1057eac94b568914f17fcccee58a0e403ccec0
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raymond Wong <wongraymond@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-12-09 06:55:26 +00:00
Felix Held f46105f099 soc/amd/picasso/southbridge: drop unused sb_enable
Change-Id: I10a16c8f9db994ff33407619a7ab6e453b026b15
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-09 02:13:27 +00:00
Felix Held 187f59accb soc/amd/picasso: split southbridge into bootblock and ramstage code
The ramstage parts gets renamed to fch.c and the bootblock one to
early_fch.c. No functionality from the old southbridge file is used in
romstage, so don't link it there.

Change-Id: I7ca3b5238c3b841191dd0459996b691edd76fbf8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-09 02:13:02 +00:00
Felix Held 64de2c151d soc/amd/cezanne: select common ACPIMMIO block
Change-Id: I7f7d11d84733a43500b0135e565d91fe5c493279
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-09 02:12:06 +00:00
Felix Held 37609852f7 soc/amd: factor out functionality to print last reset source
Change-Id: I5cec38dac7ea27aa316f5dd4f91ed84627a0f937
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-09 02:11:53 +00:00
Felix Held 20a4874445 soc/amd/common/block/acpimmio: use all-y for mmio_util target
Since mmio_util gets also linked into verstage on PSP, all-y can be used
here.

Change-Id: I03572d760b485938f0d00b6cead00746eda6ca09
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48436
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09 02:11:24 +00:00
Felix Held 26935d1ecc soc/amd: factor out legacy I/O and cf9 decode enable functions
Replace sb prefix with fch prefix, since those are all FCHs and no south
bridges any more. Verstage on PSP uses the I/O access mechanism instead
of the MMIO one, so keep a separate function for that, but also move it
to the common mmio_util file to have them all in one place.

Change-Id: I47dac9ee3d9e27f7b7a5fddab17cf4fc10de6c3e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48435
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09 02:10:58 +00:00
Felix Held 240f99c1c3 soc/amd/common/block/smbus: refactor fch_smbus_init
Move the setup of the base address to a separate function and explicitly
set the SMBUS and ASF I/O port decode even though it is expected to
already be set after reset.

Change-Id: I8072ab78985021d19b6528100c674ecdd777e62e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-09 02:10:28 +00:00
Felix Held 6b519b230e soc/amd: factor out PM_DECODE_EN register definitions
Change-Id: I005709a8780725339e7c08fbfff94e89c8ef26da
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-09 02:10:12 +00:00
Felix Held eb04fcbd15 soc/amd: remove unused PM_ISA_CONTROL definitions
ACPIMMIO_DECODE_REGISTER_04 is the definition in the common ACPIMMIO
code block that actually gets used. Also fix the indentation of the
ACPIMMIO register decode defines in the common code.

Change-Id: Ib2c460541be768fe05d8cc3d19a14dbd9c114a45
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48432
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-09 02:10:02 +00:00
Felix Held 8ce68ea846 soc/amd/stoneyridge/southbridge: make sb_disable_4dw_burst static
sb_disable_4dw_burst is only used in the same compilation unit, so no
need to make it externally visible.

Change-Id: I6c7c96f67b98fb8ed808f45a7685c4d72a10d32c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-09 02:09:44 +00:00
Furquan Shaikh 797b1cc9cf mb/google/deltaur: Restrict RW_DIAG to lower 16MiB
This change restricts RW_DIAG region to lower 16MiB to ensure that the
extended BIOS checker for FMAP does not complain about 16MiB boundary
crossing.

I haven't updated any other regions to occupy the newly freed space
but it is fine since this board is dead and should be dropped from
coreboot soon.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I19ab204fbe3e020e42baf68bfa350dcff32066a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-08 22:58:38 +00:00
Furquan Shaikh 68ca21ae3d mb/intel/tglrvp: Restrict SI_ME region to lower 16MiB
This change restricts SI_ME region to live below the 16MiB boundary to
ensure that no regions cross the 16MiB boundary as the extended BIOS
window checker for FMAP complains about it.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ib0838ff4c63b06b8dc169b40d3022965b2f2f8f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-12-08 22:58:31 +00:00
Srinidhi N Kaushik 28e1d0ea55 soc/intel/common/fast_spi: Add Lockdown of extended BIOS region
This change adds support to Lock down the configuration of
extended BIOS region. This is done as part of
fast_spi_lockdown_cfg() so that it is consistent with the
other lockdown.

Change includes:
1. New helper function fast_spi_lock_ext_bios_cfg() added that
will basically set EXT_BIOS_LOCK.

BUG=b:171534504

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I730fc12a9c5ca8bb4a1f946cad45944dda8e0518
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48068
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08 22:58:22 +00:00
Srinidhi N Kaushik 4eb489fb0f soc/intel/common/fast_spi: Add support for configuring MTRRs
This change enables caching for extended BIOS region.
Currently, caching is enabled for the standard BIOS region
upto a maximum of 16MiB using fast_spi_cache_bios_region,
used the same function to add the support for caching for
extended BIOS region as well.

Changes include:
1. Add a new helper function fast_spi_cache_ext_bios_window()
which calls fast_spi_ext_bios_cache_range() which calls
fast_spi_get_ext_bios_window() to get details about the
extended BIOS window from the boot media map and checks for
allignment and set mtrr.
2. Make a call to fast_spi_cache_ext_bios_region() from
fast_spi_cache_bios_region ().
3. Add new helper function fast_spi_cache_ext_bios_postcar()
which does caching ext BIOS region in postcar similar to 1.
4. If the extended window is used, then it enables caching
for this window similar to how it is done for the standard
window.

BUG=b:171534504

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I9711f110a35a167efe3a4c912cf46c63c0812779
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47991
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08 22:57:54 +00:00
Srinidhi N Kaushik 237afda813 src/soc/intel/tigerlake: Add SPI DMI Destination ID
This change adds the SPI-DMI Destination ID for tigerlake
soc. This is needed for enabling support for extended
BIOS region. Also, implements a SOC helper function
soc_get_spi_dmi_destination_id() which returns SPI-DMI
Destination id.

BUG=b:171534504

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I0b6a8af0c1e79fa668ef2f84b93f3bbece59eb6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-08 22:57:45 +00:00
Srinidhi N Kaushik 609490854e soc/intel/common/fast_spi: Add extended decode window support
This change enables support for configuration of extended BIOS
region decode window. This configuration needs to be performed
as early as possible in the boot flow. This is required to
ensure that any access to the SPI flash region below 16MiB in
coreboot is decoded correctly. The configuration for the extended
BIOS window if required is done as part of fast_spi_early_init().

Changes include:
1. Make a call to fast_spi_enable_ext_bios() before the bus master
and memory space is enabled for the fast SPI controller.
2. Added a helper function fast_spi_enable_ext_bios() which calls
fast_spi_get_ext_bios_window() to get details about the extended
BIOS window from the boot media map.
3. Depending upon the SPI flash device used by the mainboard and
the size of the BIOS region in the flashmap, this function will
have to perform this additional configuration only if the BIOS
region is greater than 16MiB
4. Adddditionally, set up the general purpose memory range
registers in DMI.

BUG=b:171534504

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Idafd8be0261892122d0b5a95d9ce9d5604a10cf2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47990
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08 22:57:35 +00:00
Srinidhi N Kaushik 63afea54f4 soc/intel/common/dmi: Add DMI driver support
This change allows configuring the General Purpose
Memory Range(GPMR) register in BIOS to set up the decoding in DMI.

This driver provides the following functionality:
1. Add a helper function dmi_enable_gpmr which takes as input base,
limit and destination ID to configure in general purpose memory range
registers and then set the GPMR registers in the next available
free GMPR and enable the decoding.
2. Add helper function get_available_gpmr which returns available free
GPMR.
3. This helper function can be utilized by the fast SPI driver to
configure the window for the extended BIOS region.

BUG=b:171534504

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I34a894e295ecb98fbc4a81282361e851c436a403
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47988
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08 22:56:31 +00:00