Commit Graph

5249 Commits

Author SHA1 Message Date
Rudolf Marek aa55f3768a Trivial, cleanup of GPIO comments.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Rudolf Marek <r.marek@assembler.cz>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6256 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-16 16:23:51 +00:00
Patrick Georgi c3dc8f8ebc Disable CMOS recovery code for ROMCC boards as the CBFS code used for
that feature is not ROMCC compatible.
Fixes build errors introduced in r6253.


Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6255 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-14 08:36:34 +00:00
Patrick Georgi ef3296542a Improved GPIO setup for roda/rk886ex, and some documentation
on what the GPIOs are used for.

Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6254 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-14 07:41:42 +00:00
Patrick Georgi a865b17eff Allow coreboot to initialize CMOS if checksum is invalid.
If a file "cmos.default", type "cmos default"(0xaa) is in CBFS,
a wrong checksum leads to coreboot rewriting the first 128 bytes
(except for clock data) with the data in cmos.default, then
reboots the system so every component of coreboot works with the
same set of values.

Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6253 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-14 07:40:24 +00:00
Patrick Georgi 4c8e269841 Default to CRT on Kontron/986lcd-m. "default display" doesn't always
select the right output device.

Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Joseph Smith <joe@settoplinux.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6252 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-13 11:40:38 +00:00
Patrick Georgi 9144304771 Improve compatibility of YABEL with real-world VGABIOSes
Some of them do weird things to the option rom region (mapping
registers there or so) which failed as we handled these memory
region in emulation. As they were copied back to real memory
after the emulation was done, we can just as well use real
memory directly for these regions.

This affects IVT, BDA, and option ROM space.

Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Joseph Smith <joe@settoplinux.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6251 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-13 11:38:46 +00:00
Aurelien Guillaume fe7d6b9a4a Add "cbfstool extract" function.
It dumps everything you ask for, but you might not
get what you expect if the file is compressed or
otherwise converted (eg. payloads in SELF format).
(Originally it would only extract "raw" files.
This is a change by me, as filetypes are commonly used
to differentiate raw data files --Patrick)

Signed-off-by: Aurelien Guillaume <aurelien@iwi.me>
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6250 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-13 09:09:21 +00:00
Stefan Reinauer fb433bea6a drop unused files
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6249 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-12 21:09:25 +00:00
Kerry She 09e0e9a68b change a readable way to fix SB800 CIMX "multi-character constant warning".
by using 'Int32FromChar' macro, instead of the ASCII code.

Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6248 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-11 02:15:57 +00:00
Marc Bertens 965c43b4db Various Nokia IP530 fixes.
- Correct default ROM image size for this board (512KB is correct).

 - devicetree.cb: Add AUX I/O config (mainly GPIO settings).
   This allows you to control the LEDs in the front panel and JP900/JP901
   can be read.

 - irq_tables.c: Rework PIRQ table to make more onboard devices work.
   Also, avoid IRQ9.

 - mainboard.c: Drop unneeded functions, everything is done in devicetree.cb.

Signed-off-by: Marc Bertens <mbertens@xs4all.nl>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6247 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-06 23:03:46 +00:00
Zheng Bao 69436e1a8c Fix some settings fo AMD MCT. It is based on BIOS test suite.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6246 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-06 02:18:12 +00:00
Stefan Reinauer da712f3f45 uart_init is only used in romstage.
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6245 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-05 02:40:53 +00:00
Stefan Reinauer 1b342263f0 move single options out of main menu and remove stray "options"
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6244 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-05 02:27:53 +00:00
Stefan Reinauer 355632bc31 fix compilation of mconf on some systems.
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6243 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-05 02:10:50 +00:00
Stefan Reinauer 6c28522ec1 fix "make clean"
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6242 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-05 01:37:48 +00:00
Uwe Hermann c7f0c8feab MCP55: Cosmetic fixes, switch to u8 et al.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6241 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-04 19:51:33 +00:00
Uwe Hermann 7e2fbd5dd3 CK804: Cosmetic fixes, switch to u8 et al.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6240 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-04 17:36:55 +00:00
Kerry She ecab12a09e Trivial:
add missed CIMx file to romstage. in order to link them into romstage, move all CIMx table to .rodata section.
 Run dos2unix on Makefile.inc, which is not upstream CIMx code

Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Kerry She <kerry.she@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6239 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-04 06:39:29 +00:00
Kerry She 7917f430b2 Trivial: use the IO_APIC_ADDR constant defined in ioapic.h, and spell check
Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Kerry She <kerry.she@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6238 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-04 06:15:46 +00:00
Uwe Hermann e925965034 src/southbridge/amd/cimx_wrapper: Run dos2unix on the files.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6237 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-01 23:36:03 +00:00
Uwe Hermann d6a1373da2 AMD SB800: Drop component prefix from filenames.
We did the same with other chipsets in r6150.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6236 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-01 23:30:37 +00:00
Uwe Hermann f9bd9ae9eb Add detection support for the ITE IT8721F.
Tested on hardware by me.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6235 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-01 22:05:57 +00:00
Uwe Hermann 48b8b92439 AMD Bimini: Use mptable_init() in mptable.c.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6234 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-01 18:58:39 +00:00
Uwe Hermann 26c182340f AMD Bimini: Small fixes, and updates to recent trunk conventions.
- Move CACHE_AS_RAM_ADDRESS_DEBUG #define to Kconfig, where it was renamed
   to HAVE_DEBUG_CAR in r5898.

 - Move QRANK_DIMM_SUPPORT to Kconfig, see r6028.

 - Drop obsolete/unused COMPRESS, see r6145.

 - Drop obsolete SET_NB_CFG_54, see r6086.

 - Move SET_FIDVID/SET_FIDVID_CORE_RANGE to Kconfig, see r6077.
   Actually, the default for SET_FIDVID_CORE_RANGE is 0, so drop it.

 - Rename some GENERATE_* options to HAVE_*, see r6027.

 - Drop "select CACHE_AS_RAM", this is now set in the socket, see r6151.

 - Drop ACPI_SSDTX_NUM, the global default is 0 already.

 - Random whitespace and coding style fixes.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6233 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-01 18:40:02 +00:00
Uwe Hermann f7e7519ff5 AMD Bimini: Drop duplicate ASL files as we did for other boards.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6232 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-01 18:10:07 +00:00
Kerry She ee5fcacba7 Add support for the AMD Bimini eval mainboard.
Signed-off-by: Kerry She <Kerry.she@amd.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6231 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-01 18:04:42 +00:00
Kerry She 84f59aee3c Add AMD SB800 southbridge support via cimx_wrapper.
Signed-off-by: Kerry She <Kerry.she@amd.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6230 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-01 17:52:34 +00:00
Kerry She 799fed98ea Add AMD SB800 southbridge CIMx code.
The main CIMx code is in a src/vendorcode directory and should not be
changed with regard to coding style etc. in order to remain easily syncable
with the "upstream" AMD code.

Signed-off-by: Kerry She <Kerry.she@amd.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6229 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-01 17:44:07 +00:00
Jonathan Kollasch 123edb0f68 Use $(MAKE) instead of make when cleaning for SeaBIOS.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6228 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-31 19:20:23 +00:00
Zheng Bao 40992d33b8 Add RS785(RS880) support. Just few pci_ids.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6227 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-31 01:46:12 +00:00
Zheng Bao 6d81646314 Add detection of Nuvoton WPCM450.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6226 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-31 01:38:45 +00:00
Nils Jacobs 8098e42944 Remove duplicated GX2 processor IIOC mode setting on CS5535 southbridge code
and fix CIS mode comments.

Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6225 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-30 19:23:29 +00:00
Nils Jacobs 8cf54c9f23 Use die() to assure the processor can't wake up from an interrupt.
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6224 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-30 19:21:08 +00:00
Stefan Reinauer f1939bb29b Per default, use SeaBIOS payload instead of no payload.
Add choice to use stable or master version of seabios repository

Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6223 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-30 17:39:50 +00:00
Stefan Reinauer d7ce71d58f superiotool: Don't skip probing on a port if a a chip was detected on another port.
Only skip probing if chip was found on the same port already to avoid
duplicates.
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6222 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-30 16:57:58 +00:00
Nils Jacobs 84be0f59b7 -Change the remaining GLIU1 port 5 register names from VIP (Video Input Port)
to FG (FooGlue). As the GX2 has no VIP port.
-Change the Memmory setup MSR register names so they correspond better to the
       databook. (Part1)
       This is less confusing for beginners.
-Add a MSR printing function to northbridge.c like in the Geode LX code.
-Remove the AES register names.(GX2 has no AES registers)
-Delete some unused code.
-Clean up GX2 northbridge code  to match Geode LX code.
-Add missing copyright header to northbridge.c.
-Move hardcoded IRQ defining from northbridge.c to irq_tables.c .


Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6221 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-29 21:12:10 +00:00
Stefan Reinauer cdcf9833e8 fix i810 boards with ram init debugging disabled.
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6220 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-29 21:02:50 +00:00
Nils Jacobs ef15ff4de4 -Clean up some comments.
-Remove some white spaces.
-Remove some leading zeros.
-Fix a typo in LX code.

Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6219 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-29 20:31:31 +00:00
Stefan Reinauer fc01e5e3bb proper printk handling in src/northbridge/intel/i82810/raminit.c
and drop some romcc relics in 440bx code too

Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6218 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-27 14:31:05 +00:00
Stefan Reinauer 50e7233689 __PRE_RAM__ is defined by the makefile
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6217 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-27 13:30:39 +00:00
Stefan Reinauer 1c2c75098e dump_spd_registers() is only defined when ram init debugging is on.
Most boards unconditionally call this. Fix it in header file instead of each single romstage.c

Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6216 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-27 13:29:38 +00:00
Stefan Reinauer 3c0bfaf7da Fix most CONFIG_DEBUG_RAM_SETUP issues.
The intel/xe7501devkit is still broken, I think the (romcc) image is too big to
fit in the bootblock if CONFIG_DEBUG_RAM_SETUP is enabled. It would make sense
to convert all CPU_INTEL_SOCKET_MPGA604 to CAR, but I have no hardware to test.

Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6215 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-27 11:34:57 +00:00
Stefan Reinauer acda2fc9ac Intel SCH: make state machine binary selection available in Kconfig for now.
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6214 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-27 08:21:23 +00:00
Stefan Reinauer a35eb2c5e2 All the values should stay untouched or be set automatically by the resource
allocator. If that does not work out, they should be set in the code. Setting
them in Kconfig is the worst possible thing to do.

Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6213 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-26 16:49:57 +00:00
Uwe Hermann 2d1d9cebff Random fixes for TI pci1x2x / Nokia IP530 / others.
- nokia/ip530/devicetree.cb, southbridge/ti/pci1x2x/pci1x2x.c:
   - Fix SMSC FDC37B787 name (was a typo).
   - Disable PS/2 keyboard/mouse LDN, the IP530 doesn't have either.
   - Fix typo: s/PCI_DEVICE_ID_TI_1420/PCI_DEVICE_ID_TI_1520/.
   - All of these are confirmed by Marc Bertens on IRC.
 
 - Fix a few CHIP_NAME HP board names.
 
 - Random whitespace and coding-style fixes.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6212 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-26 14:12:38 +00:00
Nils Jacobs 19d69e3bab Move Geode GX2 UMA video memory size to Kconfig
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6211 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-26 05:24:50 +00:00
Nils Jacobs 642509c965 Remove dead and unused Geode GX2 code
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6210 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-26 05:21:18 +00:00
Nils Jacobs 3344743215 Replace Geode GX2 MSR addresses for GLCP on GLIU1 with names
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6209 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-26 05:16:47 +00:00
Nils Jacobs 1c6d4e6055 Clean up Geode GX2 comments, whitespace and coding style. Trivial.
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6208 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-26 05:12:49 +00:00
Uwe Hermann 88929f9bf4 Nokia IP530: Add missing "select SDRAMPWR_4DIMM".
This is needed for all Intel 440BX boards with 4 DIMM slots (such as this one).

Thanks Marc Bertens <mbertens@xs4all.nl> for bringing up the issue and
for the success report for this fix on IRC.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6207 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-25 22:54:41 +00:00