Commit Graph

21978 Commits

Author SHA1 Message Date
Kyösti Mälkki aeadd84e7b asrock/imb-a180: Switch away from AGESA_LEGACY_WRAPPER
Change-Id: I5e6e4cabe2b93c41da19412ec3ae2dfaa114bcc0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-24 10:30:28 +00:00
Kyösti Mälkki a84e34be25 msi/ms7721: Switch away from AGESA_LEGACY_WRAPPER
Change-Id: I39a0b4acbe44dca8be63201502be739d954c8a33
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-24 10:30:18 +00:00
Kyösti Mälkki ffa527002a asus/f2a85-m: Switch away from AGESA_LEGACY_WRAPPER
Change-Id: I5a6373ac03d942cd16905c9e8360f7179b8eea61
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20712
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-24 10:30:03 +00:00
Kyösti Mälkki 8176af91e8 amd/torpedo: Switch away from AGESA_LEGACY_WRAPPER
Change-Id: Iac0998a56b4e297c512fcba98d3dbb4253c9b526
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-24 10:29:52 +00:00
Tim Chen 1f3af89895 mb/google/coral: Copy devicetree.cb from baseboard
It is a copy from baseboard/devicetree.cb  (coreboot.org ToT)

BUG=b:64880573
BRANCH=master
TEST=emerge-coral coreboot chromeos-bootimage

Change-Id: I5db730c1974a96547fe7fda63689b7c5bfaefc66
Signed-off-by: Tim Chen <Tim-Chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/21130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-24 03:19:11 +00:00
Subrata Banik f5fe3590af soc/intel/skylake: Usable dram top calculation based on HW registers
This patch ensures that entire system memory calculation is done
based on host bridge registers.

BRANCH=none
BUG=b:63974384
TEST=Build and boot eve and poppy successfully with below configurations
1. Booting to OS with no UPD change
2. Enable ProbelessTrace UPD and boot to OS.
3. Enable PRMRR with size 1MB and boot to OS.
4. Enable PRMRR with size 32MB and boot to OS.
5. Enable PRMRR with size 2MB and unable to boot to OS due to
unsupported PRMRR size.

Change-Id: I9966cc4f2caa70b9880056193d5a5631493c3f3d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-23 17:56:50 +00:00
Martin Roth 89942a5aa7 Update depthcharge stable to upstream master
Updating from commit id 5a086f5c - Tue Jul 11 23:57:30 2017:
(ps8751: enable software sync.)

to commit id a843f262 - Wed Aug 16 23:37:52 2017:
(kahlee: select emmc boot first if available)

This brings in 20 new commits.

This matches with the updated vboot submodule.

Change-Id: If030bc3e75dd470838590540880213bd841154b8
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-08-23 16:33:05 +00:00
Martin Roth 66dce275e5 Update vboot submodule to upstream master
Updating from commit id 8b714252 - 2017-07-18 02:36:16
(crossystem: Remove defunct sw_wpsw_bootfield)

to commit id 8c4b8285 - 2017-08-14 20:37:45 -0700
(detachables: Skip "Enable Developer Mode" in DEV mode)

This brings in 6 new commits.

Change-Id: I7769035453796a162c6313cd0c87661ef1e64f89
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-08-23 16:32:52 +00:00
Subrata Banik d3f0243299 soc/intel/common: Early system agent library access in postcar stage
BRANCH=none
BUG=b:63974384
TEST=Build and boot eve successfully.

Change-Id: Ie5558cdb7acacc34451e1cf63a3e4239e7901c67
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-23 16:17:19 +00:00
Subrata Banik bd6ac22f48 soc/intel/common: Add functions into common system agent library
This patch to add helper functions for memory layout design
based on PCI Host Bridge/DRAM registers.

BRANCH=none
BUG=b:63974384
TEST=Build and boot eve successfully.

Change-Id: I95250ef493c9844b8c46528f1f7de8a42cba88a2
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-23 16:17:04 +00:00
zhaojohn 53461ad1f8 src/mainboard/intel/cannonlake: Add gpio support for cannonlake
Add gpio pins configuration for cannonlake rvp u/y boards.

Change-Id: Ia077a070979401fe7bd23bda110d2b66a038d9fc
Signed-off-by: john zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-23 15:53:10 +00:00
Kane Chen 5bddcc48b8 soc/intel/apollolake: Allow overriding dev tree settings by board
This change provides interface to override dev tree settings per
board due to many projects share same devicetree.cb.

BUG=b:64880573
TEST=Verify that dev tree settings can be overridden in mainboard
     on coral

Change-Id: I349b1678d9e66022b586b6c7f344b831ed631c74
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/21142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-23 15:52:48 +00:00
Bill XIE a0d31d8d7d mb/lenovo/t430s: Enable libgfxinit
Tested on T430s with an external screen connected to every one of the
DP ports (miniDP on mainboard, two DP ports on dock), the GRUB payload
can display on both the external screen and the internal LVDS screen.

This is a copy-paste of I8f270d55 "mb/lenovo/x230: Enable libgfxinit".

Change-Id: Ifb1471ecb18927c30c61c64011cbb0e20a465558
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/21070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-23 08:36:55 +00:00
Kyösti Mälkki 538a570c98 sb/via/k8t890: Define ACPI sleep states
Change-Id: I9afd5eaab5f8e897dea037f32e1666ad31b0f8df
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-08-23 03:39:54 +00:00
Kyösti Mälkki bbd60e31be soc/amd/stoneyridge ACPI: Sync sleepstates.asl definitions
Sync file with southbridge/amd/common/sleepstates.asl.

SSFG was meant to be used as a mask to enable sleepstates
_S1 thru _S4. However as a logical instead of bitwise 'and'
operation was used, all the states were enabled if only
one was marked available.

Change-Id: I674953f1a5add74e16ddd84c252e8d21501ffefd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-08-23 03:39:06 +00:00
Kyösti Mälkki fb94585554 sb/amd/amd8111: Define ACPI sleep states
Note that against the specs, these definitions repeat
the sleep type also in the reserved fields 3 and 4.
For consistency, don't fix it here now.

Entry for \_S3 is now masked off if HAVE_ACPI_RESUME=n.

Change-Id: Icdc4c81d07fe7a99d5b0f8fa23e9443f58a40ab9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-08-23 03:36:15 +00:00
Kyösti Mälkki 714709fde6 AMD fam10 ACPI: Use common fixed sleepstates.asl
SSFG was meant to be used as a mask to enable sleepstates
_S1 thru _S4. However as a logical instead of bitwise 'and'
operation was used, all the states were enabled if only
one was marked available.

Note that all boards incorrectly had SSFG == 0x0D that previously
enabled ACPI S3 sleep state even when it was not available.

Change-Id: Ia948becff079383cbf861468da9e8a3ebbf213cb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-08-23 03:36:05 +00:00
Kyösti Mälkki 390ba044dc AGESA binaryPI: Consolidate and fix sleep states
SSFG was meant to be used as a mask to enable sleep states
_S1 thru _S4. However as a logical instead of bitwise 'and'
operation was used, all the states were enabled if only
one was marked available.

State _S3 is now set conditionally if HAVE_ACPI_RESUME=y.
For pi/hudson this had been fixed already preprocessor.

Note that all boards had SSFG == 0x0D that previously
enabled ACPI S3 sleep state even when it was not available.
States _S1 and _S2 still appear enabled in ASL/AML
but may not actually work.

TEST: 'cat /sys/power/state' and notice choice 'mem' was
removed from the list of available sleep states.

Change-Id: I27d616871c1771f0c87d8fba23d4ce1569607765
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-08-23 03:35:58 +00:00
Kyösti Mälkki 1438245334 AMD K8 fam10-15: Tidy up CAR stack switch
Return to empty stack before making the switch.

Change-Id: I6d6f633933fac5bc08d9542c371715f737fb42cf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2017-08-22 20:25:15 +00:00
Kyösti Mälkki 90e07b460c AMD K8 fam10-15: Consolidate post_cache_as_ram call
Change-Id: I5e7890aafbc8c80716ee49690e306482a482a863
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20573
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2017-08-22 20:24:38 +00:00
Kyösti Mälkki b98391c0ee AMD K8 fam10-15: Tidy up CAR disable
Avoid conflicting disable_cache_as_ram() declaration and tidy
up include for inlined function.

Change-Id: Iba77c711f5eb023566b7d8ba148583948661bc99
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-22 20:24:31 +00:00
Mariusz Szafranski a429761b7b vendorcode/intel/fsp/fsp2_0/denverton_ns: Add FSP header files for Denverton_NS SoC
This change adds the FSP header files for FSP version 2.0 (15D50)
for the Intel Denverton_NS SoC.

Change-Id: I9672610df09089c549e74072345781bea0b4d06f
Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com>
Reviewed-on: https://review.coreboot.org/20805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
Reviewed-by: Brenton Dong <brenton.m.dong@intel.com>
2017-08-22 19:11:23 +00:00
Pratik Prajapati 0f2f069b4f soc/intel/cannonlake: Define soc_intel_cannonlake_config
- Populate soc_intel_cannonlake_config
- Add usb.h and vr_config.h for CannonLake

Change-Id: I2a6e737594da1e766b157a38942e19a4f7fb9dfa
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-22 18:01:39 +00:00
Patrick Georgi 4bd68b8e4f ec/google: Detect keyboard backlight at runtime
This enables adding the backlight driver to boards that may or may not
come with a keyboard backlight function.
It's the responsibility of the EC to report if that feature exists, but
that's not a big extra burden given that it already keeps track of
everything else related to the backlight.

BUG=b:64705535
BRANCH=none
CQ-DEPEND=CL:620595
TEST=configured KBLE manually and noticed the presence/absence of
/sys/devices/platform/GOOG0002:00/ on a Chrome OS Linux kernel,
corresponding to the value reported by the EC.

Change-Id: Idc36bfaa6e69581ba19b52d37af6956f63cfdb8f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-22 17:59:20 +00:00
Barnali Sarkar fbf1018805 soc/intel/skylake: Lock sideband access in coreboot and not in FSP
The Sideband Acces locking code is skipped from FSP by setting an
FSP-S UPD called PchSbAccessUnlock. This locking is being done in
coreboot during finalize.c.

This is done because coreboot was failing to disable HECI1 device
using Sideband interface during finalize.c if FSP already locks
the Sideband access mechanism before that.

So, as a solution, coreboot passes an UPD to skip the locking
in FSP, and in finalize.c, after disabling HECI, it removes the
Sideband access.

BUG=b:63877089
BRANCH=none
TEST=Build and boot poppy to check lspci not showing Intel ME
controller in the PCI device list.

Change-Id: I8dba4c97480200507969b0f2873337f97bd2ff6a
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-08-22 17:35:38 +00:00
Akshu Agrawal f7cd2f5b94 google/kahlee: Enable ALS connected to EC
Kahlee has an ambient light sensor connected to the EC.

TEST=Can see the device in /sys/bus/iio
BUG=b:62030268

Change-Id: Id1138a0fc5270489a734bdf8b1f4ac02d358c0df
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/21146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-22 17:21:33 +00:00
Pratik Prajapati ee9168737f mainboard/intel/cannonlake_rvp: remove redundant devicetree.cb
devicetree.cb of cannonlake-u and y variant gets picked up
from src/mainboard/intel/cannonlake_rvp/variants/cnl_[u/y]

Change-Id: I83f636c93407a6fe17114582506397c46d1b4e20
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-22 17:18:51 +00:00
Pratik Prajapati 3c15a39ea1 mainboard/intel/cannonlake-y: populate PCI devices
Define and populate PCI devices in devicetree for CNL-Y RVP

Change-Id: I311437798274dd48b0898f0832bf03d86fd9d3a6
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-08-22 14:51:59 +00:00
Pratik Prajapati 1785f8b2f5 mainboard/intel/cannonlake-u: populate PCI devices
Define and populate PCI devices in devicetree for CNL-U RVP

Change-Id: Id04f5efe77a04c180b5dd392da777195bd9fb7a3
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-08-22 14:51:55 +00:00
Harry Pan 4a2cef4ef7 mainboard/google/coral: Overwrite family code for coral models.
This patch assigns the code of coral family, such that,
the 'mosys platform family' returns 'Google_Coral'.

BUG=b:64467244, b:64501879
BRANCH=none
TEST=Examine 'mosys platform family' w/ new firmware.

Change-Id: I1d8f8ca2166a1d80855608cf5b64b0cc7bf3dc93
Signed-off-by: Harry Pan <harry.pan@intel.com>
Reviewed-on: https://review.coreboot.org/21136
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-22 14:51:27 +00:00
Maciej Suminski 3a44b6a34c util/msrtool: Exit program after displaying the help message
In case there is no mode selected, sys and cpu variables are not
initialized, causing a segfault on exit (goto done).

Change-Id: I4a183c267e306598627c1612f4633f1e19019f3c
Signed-off-by: Maciej Suminski <maciej.suminski@cern.ch>
Reviewed-on: https://review.coreboot.org/21026
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2017-08-22 10:10:49 +00:00
Maciej Suminski d5fb99eab6 util/inteltool: Remove duplicated error message, switch to snprintf
Passing a string containing output from strerror() to perror() causes
double error message display. It is also causing segfaults when the
error message is longer than temp_string capacity.

To fix the problems, sterror() call has been removed so the error
message is printed only once. This could be enough to avoid segfaults,
but it is a good practice to limit output size with snprintf().

Change-Id: I5ccc37e404f278cafae0a451c5acaa27d7907cce
Signed-off-by: Maciej Suminski <maciej.suminski@cern.ch>
Reviewed-on: https://review.coreboot.org/21025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-08-22 10:10:34 +00:00
Lijian Zhao b3dfcb863c soc/intel/cannonlake: Enable common PMC code for CNL
This update changes Cannonlake to use the new common PMC code. This
will help to reduce code duplication and streamline code bring up.

Change-Id: Ia69fee8985e1c39b0e4b104c51439bca1a5493ac
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-21 20:37:57 +00:00
Pratik Prajapati 7a357eb865 soc/intel/skylake: Fix SGX init sequence
Configure core PRMRR first on all the cores and then follow
the SGX init sequence. Second microcode load would run the
MCHECK. To pass MCHECK, PRMRR on all cores needs to be
configured first. Hence, PRMRR configuration would be called
from soc_core_init while MP init for each core and then from
soc_init_cpus, BSP would call sgx_configure for each core
(including for itself). This code flow satisfies the MCHECK
passing pre-conditions; and apparently this patch fixes the
behavior of calling configure_sgx() “again” for BSP. (So
removed the TODO comment also).

Change-Id: I88f330eb9757cdc3dbfc7609729c6ceb7d58a0e1
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21007
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-21 19:46:43 +00:00
Pratik Prajapati 53d68b4ffb intel/common/block/sgx: Refactor SGX common code
To correct the SGX init sequence; PRMRR on all cores first
needs to be set, then follow the SGX init sequence. This
patch would refactor the common SGX code (and add needed
checks in the init sequence) so that SOC specific code can
call SGX init in correct order.

Change-Id: Ic2fb00edbf6e98de17c12145c6f38eacd99399ad
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-21 19:46:34 +00:00
Pratik Prajapati 9cd6a265e2 intel/common/mp_init: Refactor MP Init code to get rid of microcode param
Remove passing microcode patch pointer as param while calling
 - soc_core_init()
 - soc_init_cpus()

Also change callbacks in apollolake/geminilake and skylake/kabylake
common code to reflect the same function signature.

Change-Id: Ib03bb4a3063d243d97b132e0dc288ef3868a5a7b
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21010
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-21 19:25:40 +00:00
Keith Hui 641370e1dc superio/winbond/w83627*: Remove deprecated code
Early serial for W83627[HF|EHG] superios are handled by
superio/winbond/common/early_serial.c. Remove code
thus deprecated.

Build tested on select affected mainboards.

Change-Id: Idad6e0281f7a272e184feff686ce1407825429c7
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-21 17:02:53 +00:00
Keith Hui bb73c98d24 Boards w/ Winbond superios: Use common config entry code
Six mainboards with Winbond superios directly configure
them in romstage.c. All use the common Winbond romstage
code. Change them to use the common config entry code to
allow for code refactoring such as [1]. Build tested.

[1] https://review.coreboot.org/20988

Change-Id: Icecd52ec622b9da86edb07c52893f4db001e5562
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-21 17:02:45 +00:00
Iru Cai 928c6c6336 mainboard/asrock: add ASRock B75 Pro3-M
Tested:

- i5-3550 and DIMM configurations: 2+0+2+2, 0+2+2+2, 2+2+2+2, 4+2+4+2
- debug output from serial port, EHCI debug port not found
- Arch Linux (Linux 4.11.5) loaded from SeaBIOS, GRUB2, and Linux payload
- all PCI and PCI Express slots

Issues:

- sometimes the machine fails to boot, with serial debug output it can
  be seen it stucks after SMM initialization, and more likely to fail
  to boot when serial cable is attached
- no S3 resume (not tested in vendor firmware)

Change-Id: I94fbfcee06921538b32aa3c23efa642e7e405ef6
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/20227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-21 17:02:19 +00:00
Nicola Corna b016f144cc libpayload: add time()
Change-Id: I97e393537ccc71ea454bb0d6cdbbb7ed32485f1e
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/21011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-21 16:53:20 +00:00
Patrick Rudolph 7f395fe95b ec/lenovo/h8: Add panic method
Add two additional LED IDs.
Add Kconfig menu entries to allow selecting the action
to execute on death.
Overwrite weak die_notify method to notify user on death.
Flash all LEDs and play beep code 10 depending on Kconfig
options.

Successfully tested on:
Tested on Lenovo T500.
Tested on Lenovo X200.

Tested on Lenovo T430, but only LEDs are flashing.

Change-Id: Id34d399f154952a48c1f4ccb0c41a238b2d7ccb8
Signed-off-by: Patrick Rudolph <siro@das-labor.org
Reviewed-on: https://review.coreboot.org/19695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-21 16:51:12 +00:00
Kevin Chiu a9117770e9 google/snappy: Add Raydium touch screen support
Current coreboot does not create ACPI device for OS to recognize Raydium
touchscreen.

List the touch screen in the devicetree so that the correct ACPI device
are created.

BUG=b:64821783
BRANCH=reef
TEST=emerge-snappy coreboot
Change-Id: I8852e38f01f82b80c2c9718b93baf5894dbd745b
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/21083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-08-21 16:40:40 +00:00
Kevin Chiu 215beb028b google/snappy: Add MELFAS touch screen support
Current coreboot does not create ACPI device for OS to recognize MELFAS
touchscreen.

List the touch screen in the devicetree so that the correct ACPI device
are created.

BUG=b:64779224
BRANCH=reef
TEST=emerge-snappy coreboot
Change-Id: If2bc910d641e0cf2b120ed883c5788542959f568
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/21067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-21 16:40:17 +00:00
Pratik Prajapati 57f8386a2b intel/common/sgx: Use intel_mp_current_microcode() to get microcode pointer
Get microcode patch pointer from intel_mp_current_microcode() api
of mp_init and change sgx_configure function signature to drop
microcode_patch param.

Change-Id: I9196c30ec7ea52d7184a96b33835def197e2c799
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21009
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-21 16:32:18 +00:00
Subrata Banik 226065834b soc/intel/cannonlake: Add support for all UART port index
Select LPSS UART Base address based on LPSS UART port index.

Change-Id: I31b239e7e6b7e9ac8ea2fcfbcbd8cb148ef9e586
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-21 16:30:24 +00:00
Subrata Banik 7e9cb92815 soc/intel/skylake: Add support for all UART port index
Select LPSS UART Base address based on LPSS UART port index.

Change-Id: I306d3d299f8d6a890ae519c74008f9d0d9dd1a76
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-21 16:29:55 +00:00
Subrata Banik ce4c9ec4f6 soc/intel/cannonlake: Add Kconfig option to select UART index
Cannonlake SOC has two possible ways to make serial
console functional.

1. Legacy IO based access using Port 0x3F8.
2. LPSS UART PCI based access.

This patch to provide option to select index for LPSS
UART port: 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2

PCI based LPSS UART2 is by default enabled for Chrome Design.

Change-Id: I7afa5ab2c5eb06e6df8eeb1cb1cd0de00d2b2a28
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-21 16:22:51 +00:00
Subrata Banik 19a7adeffe soc/intel/skylake: Add Kconfig option to select UART index
Skylake/Kabylake SOC has two possible ways to make serial
console functional.

1. Legacy IO based access using Port 0x3F8.
2. LPSS UART PCI based access.

This patch to provide option to select index for LPSS
UART port: 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2

PCI based LPSS UART2 is by default enabled for Chrome Design.

Change-Id: I9647820fe59b5d1a1001a611b9ae3580946da0ae
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-21 16:13:10 +00:00
Aaron Durbin d6bd825d6c soc/intel/apollolake: remove duplicate gpio GPE defines
Remove the duplicate MISCCFG_GPE0_DW* macros that are already present
in the common gpio code.

Change-Id: Iad75e5f7e276b37b5861f0c9a3bb0bb2824a638c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-21 16:00:40 +00:00
Pratik Prajapati f771de445d intel/common/cpu: Add function to get microcode patch pointer
Add mp_current_microcode() function to get the microcode patch pointer.
Use this function to avoid reading the microcode patch from the boot
media. init_cpus() would initialize microcode_patch global variable to
point to microcode patch in boot media and this function can be used
to access the pointer.

Change-Id: Ia71395f4e5b2b4fcd4e4660b66e8beb99eda65b8
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-21 15:58:42 +00:00