Commit Graph

41475 Commits

Author SHA1 Message Date
Jakub Czapiga ec8eef0a6b tests/lib/bootmem-test: Add initialization of lb_mem fields
Add missing initialization of tag and size fields. Include initial size
value in assertion in test_bootmem_write_mem_table().

Found-by: Coverity CID 1452250
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I27678a4eb01a0e6bedd0ba8c4b22a1b01afeaf12
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-04-13 16:03:27 +00:00
Michael Niewöhner 64d31f48d2 lint: MAINTAINERS: check path matches to not only cover the directory
Gerrit is able to add reviewers based on entries in the `MAINTAINERS`
file. For inclusion and exclusion matches either paths or regular
expressions can be used. The syntax is described in the header of the
file.

When matching a path, there are two sensible possibilities:
  - `path/to/file`  matches a file.
  - `path/to/dir/`  matches a folder including its contents recursively.
  - `path/to/dir/*` matches all files in that folder, without recursing
                    into its subfolders.

The trailing slash in the second example is essential. Without it, only
the directory entry itself matches when, for example, the folder gets
deleted, renamed or its permissions get modified. Reviewers in the list
won't get added to changes of any files or directories below that path.

Thus, add a linter script to ensure a path match on a directory always
ends with `/` or `/*` as shown above.

Change-Id: I9873184c0df4a0b4455f803828e2719887e545db
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-04-13 14:29:43 +00:00
Angel Pons 2b4da16ea4 mb/hp/280_g2/romstage.c: Correct CaVrefConfig setting
With DDR4, CA Vref goes to channel 0, and CH1 Vref goes to channel 1.

Change-Id: I64606824b4f82affb0fcfc78e68ba29859a1cc69
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-04-13 08:24:29 +00:00
Tim Wawrzynczak 7f7c3882a6 dptf: Move platform-specific information to `struct dptf_platform_info`
DPTF HIDs are different per-platform going forward, so refactor these
into SoC-specific structures which the DPTF driver can query at runtime
for platform-specific information.

Change-Id: I6307f9d28f4274b851323ad69180ff4ae35053da
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-04-13 08:22:49 +00:00
Yidi Lin 24ea3f3364 soc/mediatek/mt8195: Add a stub implementation of the MT8195 SoC
TEST=boot from SPI-NOR and show console message at bootblock stage.

Change-Id: Ia93430006096b7410393ab31fee4ea40598d0b34
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-13 06:07:54 +00:00
Nico Huber 2bb361f0f5 nb/intel/x4x: Refactor sync DLL programming (part 2)
Instead of counting consecutive matches (in `j`), check for a second
match directly in the control flow. Also, add some dedicated variables:

* `tap`: Keeps track of the tap value that resulted in a match and
         is eventually programmed into the hardware.

* `tap2`: Is just temporarily used to search for another edge.

Keeping `tap` sync'ed with the hardware has the benefit that we don't
need to read the programmed value back for later fixups.

Change-Id: I3ae541c39efdc695f5ca74bc757b2f009239ec93
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-04-12 20:42:08 +00:00
Nico Huber a20a02e82a nb/intel/x4x: Refactor sync DLL programming (part 1)
Extract some common code patterns into functions.

Change-Id: I5f8d40bb55d4b4f0639e0287881ae0ecde298590
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-12 20:41:53 +00:00
Nico Huber b6a2ebe5ef nb/intel/x4x: Sort code in program_dll()
Move the last block of the sync DLL programming up. It's independent
of the switch/case statement that it's moved around.

Change-Id: I71bc1ca1c629e4f2f4a13474c7e2c22d1a3b65d9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-12 20:41:43 +00:00
Eric Lai 67d099a7f2 mb/google/mancomb: Temporary fix to set eSPI mux
BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ief59bdea392ab3f141ccf7444c608aef99701d2e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-04-12 17:26:52 +00:00
Kangheui Won 082be1073e chromeec: make ssfc optional in fw_config
When EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG is enabled and SSFC is
not set, all fw_config is invalidated. But for some platform this may
not be necessary, we can treat missing SSFC as zero and use other 32
bits of firmware config.

BUG=b:184809649
TEST=boot and check fw_config is not -1 even if ssfc is not set
BRANCH=zork

Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I21c7b0d449a694d28ad7b3f14b035e3a5830030a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-12 17:11:40 +00:00
Michael Niewöhner c5f1dc96bf mb/*: drop LPC generic range for port 80
Port 80 (actually 0x80-0x8f) is a fixed I/O range and thus does not have
to be set up as generic range. Drop the entries from the devicetrees.

Change-Id: I8a54d3c35a321a2d57bd846662f7339eff53e5a8
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-04-12 16:52:19 +00:00
Felix Held c1ec940eba mb/amd/majolica/port_descriptor: use GPIO number define
TEST=Timeless build results in identical binary.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie39dc99bef4eb3776388d7406239bac6031bfaaf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-12 15:46:39 +00:00
Eric Lai 141f33de54 mb/google/mancomb: add DXIO and DDI descriptors
Sync from guybrush.

BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ica4e6511a5106a958567565b96d5888b8c829ff2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-04-12 14:59:00 +00:00
Ritul Guru 7dccf47fdd mb/amd/bilby: Use Picasso VBIOS as default
use PicassoGenericVbios.bin as default instead of raven VBIOS for
Bilby.

Change-Id: I99621173a33a1154f8bb4929d199288265bbe04d
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52209
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-12 14:58:12 +00:00
Aseda Aboagye c8b79b9606 mb/google/dedede: Enable HECI
This commit enables HECI such that interface can be used from
userspace on the dedede mainboards.

BUG=b:184219504
TEST=Build and flash drawcia, verify that Intel Flash Programming Tool
can communicate with the Converged Security Engine.

Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Change-Id: I5b28c471d6554a5e14538073d48ef47da05936fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-11 21:07:22 +00:00
Felix Held a643e212c2 soc/amd/common/block/gpio: remove SoC type check in gpio_fill_wake_state
Verified that all accessed registers exist in all SoCs that use this
code (Carrizo, Mullins, Stoneyridge, Picasso and Cezanne at the moment)
and that the bit definitions match as well. Also at the time of writing
this patch only Picasso calls gpio_fill_wake_state, so dropping the
check won't change behavior. This also avoids having SoC specific code
that doesn't get selected by Kconfig options in the common AMD SoC
directory and also avoids having to add a check for SOC_AMD_CEZANNE to
support this functionality on Cezanne in a follow-up patch.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If770780a67776daf81744db1b635ffd402653a47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52223
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-11 21:06:45 +00:00
Felix Held 70d1c723f7 sb/amd/pi/hudson: remove unused Bolton PI FCH code
There is no nb/amd/pi northbridge left in coreboot that could be paired
with the Bolton FCH, since the remaining nb/amd/pi northbridges all use
an integrated FCH (Avalon on Mullins and Kern on Carrizo) while Bolton
is a discrete FCH. I ran into this when verifying if the common soc/amd
GPIO functionality that gets added by selecting
SOC_AMD_COMMON_BLOCK_BANKED_GPIOS is valid for all chips selecting it
and that code isn't valid for Bolton that uses the old GPIO 100
interface.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iffe876bee96e42645e1be10730b78959b1c06d59
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52222
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-11 21:06:29 +00:00
Frank Wu dfd9a62a90 mb/google/zork/vilboz: Update register parameters for sx9324 tuning
To update the sx9324 registers after RF team fine-tuned the parameters.

BUG=b:172397658
BRANCH=firmware-zork-13434.B
TEST=build coreboot and verify the sx9324 function

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Ief85bc61952144a1d7a151100d89938517078ab4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51936
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-11 21:06:08 +00:00
Jakub Czapiga 13145e5d18 tests/lib/malloc-test: Fix possible memory overrun
Coverity reported false-positive possible memory overrun
in setup_calloc_test(). Change memset address to use actual
buffer instead of pointer stored in symbol value in order
to silence Coverity.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I19f0718c657d565e515157e66367573e08f51254
Found-by: Coverity CID 1452005
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52136
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-11 21:05:25 +00:00
Angel Pons 69e3fde5e4 spd.h: Move `DIMMx` macros to i440bx/raminit.h
These macros aren't needed anywhere else, so reduce their visibility.

Change-Id: Ie8d14849b4fb86d34a841d4a13ee3bbb46f9f71c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52061
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-11 21:05:00 +00:00
Angel Pons 527b68219f sb/intel/x/smbus.c: Correct register access width
The register is 16 bits wide.

Change-Id: I58d44a17613965e0a27aab5246dcdce68e1a8201
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-04-11 21:04:46 +00:00
Matt DeVillier 544d7e2b91 payloads/tianocore: Fix compilation for UEFIPAYLOAD option
Upstream edk2 dropped separate 32-bit support for UefiPayloadPkg, and
removed the architecture suffix from the package dsc filename.

Test: build/run qemu with CONFIG_TIANOCORE_UEFIPAYLOAD selected.

Change-Id: I40077f1d370f0cb5627645b305b57e6c71e44095
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2021-04-10 20:24:50 +00:00
Arthur Heymans af13a6ed28 mb/prodrive/hermes: Fix eeprom reading
The logic for bytes to copy to the function input pointer was wrong.
What it did was to loop over all 2 bytes that need to be read and only
copy the first byte.

Change-Id: Ic08cf01d800babd4a9176dfb2337411b789040f3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2021-04-10 20:23:24 +00:00
Sridhar Siricilla fce0954f45 mb/intel/shadowmountain: Enable Bluetooth config in the devicetree
The patch enables Bluetooth config in the devicetree and removes
non-existent Bluetooth PCI interface.

TEST=Verified by checking Garfield Peak controller's PID:VID(8087:0033) in
the lsusb ouput.

Output of lsusb:

Bus 004 Device 003: ID 0bda:8153 Realtek Semiconductor Corp. USB 10/100/1000 LAN
Bus 004 Device 002: ID 0bda:0411 Realtek Semiconductor Corp. 4-Port USB 3.0 Hub
Bus 004 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub
Bus 003 Device 003: ID 0781:55a9 SanDisk Corp. Dual Drive
Bus 003 Device 004: ID 413c:2113 Dell Computer Corp. Dell KB216 Wired Keyboard
Bus 003 Device 002: ID 0bda:5411 Realtek Semiconductor Corp. 4-Port USB 2.0 Hub
Bus 003 Device 005: ID 8087:0033 Intel Corp.

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I7a54d344ef1b0418bee56e7308977a61604b954a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52182
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10 20:23:07 +00:00
Karthikeyan Ramasubramanian f62bbc8388 soc/amd/cezanne: Set Power state after power failure
Configure the power state to return to when the power is re-applied
after power failure.

BUG=b:183739671
TEST=Build and Boot to OS in Majolica and Guybrush. By default when the
power fails the device turns on after power is re-applied. When the
POWER_ON_AFTER_POWER_FAILURE is disabled, the device remains off even
after the power is re-applied.

Change-Id: I21c5da08c82156d6239450ef6921771da74cbaa1
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52049
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10 20:22:54 +00:00
Karthikeyan Ramasubramanian 2429557350 soc/amd/common: Handle power resume after power failure
Introduce a power management library to handle the power resume after
power failure. Enable HAVE_POWER_STATE_AFTER_FAILURE config when this
library is enabled.

BUG=b:183739671
TEST=Build Guybrush and Majolica mainboard.

Change-Id: Iea4ea57d747425fe6714d40ba6e60f2447febf28
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-04-10 20:22:40 +00:00
Eric Lai 65b0afe9a6 soc/amd/cezanne: Add GRXS and GTXS method
Add GRXS and GTXS support. Move the gpio method into common place.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I8ba377179d6976cf26ed0dc521d8e4eff051dc85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-04-10 20:22:27 +00:00
Alex Levin 6ada39e790 mb/google/brya: Change GPP_E16 default to high
To enable WWAN we want to release it from reset start.

BUG=b:180166408
TEST=WWAN enumerates on brya

Change-Id: I4f9884d3b2fc8822dda1a6fe743c863aa6c696da
Signed-off-by: Alex Levin <levinale@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52199
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10 20:22:06 +00:00
Angel Pons a67a3227f8 soc/intel/alderlake: Drop unreferenced `InternalGfx`
This option is not referenced anywhere. Drop it.

Change-Id: Ie59de5399a9b1713109bf334d4ad1d7f7efb91f9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52104
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10 20:21:51 +00:00
Angel Pons 7811a45553 cpu/intel/haswell: Use new fixed BAR accessors
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: I5fb31f88bbf7c2f1e44924ca2d3169257a9598dd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-04-10 16:04:59 +00:00
Angel Pons 528b471f94 mb/dell/optiplex_9010: Use new fixed BAR accessors
Change-Id: I4d949d252ca24ebd4e4ed9c7dd17ede3810a8bfd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-04-10 16:04:49 +00:00
Angel Pons 1d4044ae88 nb/intel/i945: Use new fixed BAR accessors
Tested with BUILD_TIMELESS=1, Getac P470 remains identical.

Change-Id: Ifea441ad95293ad93d11a5f2521370cfd387289b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-04-10 16:04:32 +00:00
Angel Pons 3f1f8ef931 nb/intel/gm45: Use new fixed BAR accessors
Tested with BUILD_TIMELESS=1, Roda RK9 remains identical.

Change-Id: I18f40d1bc3172b3c1b6b4828cefdb91aea679ba2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51880
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10 16:04:20 +00:00
Angel Pons 677ac69868 nb/intel/gm45/gm45.h: Guard `CxDRC1_NOTPOP` macro parameters
Wrap `r` in parentheses to avoid unexpected behavior with compound
expressions. Fortunately, all uses of this macro do not cause issues.

Tested with BUILD_TIMELESS=1, Roda RK9 remains identical.

Change-Id: Id0f05a507c5e7e8c50e9765261d86bae73c7b5a6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-04-10 16:04:07 +00:00
Angel Pons a5146f3239 nb/intel/x4x: Use new fixed BAR accessors
Some cases break reproducibility if refactored, and are left as-is.

Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical.

Change-Id: I163995c0b107860449c2f36ad63e4e4ca52decb2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51878
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10 16:03:46 +00:00
Angel Pons 93aab51ec1 nb/intel/x4x: Correct and use macros for CLKCFG
The `CLKCFG_UPDATE` macro is copied from gm45 and unused. Correct it and
use the CLKCFG macros instead of magic values.

Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical.

Change-Id: I17e972eba21282ac84c7afe10b7149cd1131fd07
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51877
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10 16:03:09 +00:00
Angel Pons 70dc0a8cc3 nb/intel/x4x/dq_dqs.c: Avoid breaking strings over multiple lines
Breaking strings across multiple lines hurts greppability. Refactor the
code a bit to drop one indentation level, and then reflow the strings.

Change-Id: I0accdfd0d2c5f58e4da493ba0d4b5c6a067d92c3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51876
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10 16:03:00 +00:00
Angel Pons e82191451c nb/intel/x4x: Add missing newlines to log message
Change-Id: I67f38bcb1ec0fbbfb7f2f3fcfaf2f9bf2d9ac92c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51875
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10 16:02:27 +00:00
Angel Pons dd7ce4e1d3 nb/intel/x4x: Reflow long lines
Try to unbreak long lines and user-visible strings.

Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical.

Change-Id: I1bbf08cf665157840380517302ca581718e3cbe4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51874
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10 16:02:03 +00:00
Angel Pons 5c3160ed80 nb/intel/x4x/dq_dqs.c: Fix typo in variable name
Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical.

Change-Id: I143e69446614ddc80562e5931c260329257fd3cb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51873
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10 16:00:45 +00:00
Angel Pons c024c14790 nb/intel/x4x: Correct sync DLL phase search
Bit 4 needs to be set then polled for after changing sync DLL taps.

Change-Id: I61b73998dec84710eec0d2561a6f4d88068e3373
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51872
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10 16:00:32 +00:00
Angel Pons 11cabea60d nb/intel/pineview: Replace remaining BAR accessors
These changes are not reproducible for some reason.

Change-Id: If1fcd0285c3a14686f7deb70d83a4c63d57d62fe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51871
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10 16:00:10 +00:00
Angel Pons 0aeaee7d9d nb/intel/pineview: Use new fixed BAR accessors
Some cases break reproducibility if refactored, and are left as-is.

Tested with BUILD_TIMELESS=1, Foxconn D41S remains identical.

Change-Id: I484f04455fe4baa69888645554fcd72881ba197d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51869
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10 15:54:55 +00:00
Angel Pons dea722b36c nb/intel/ironlake: Use new fixed BAR accessors
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.

Change-Id: Ia0a086bd28b796d2cbe1c7a056922721c95612b8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51868
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10 15:54:39 +00:00
Angel Pons 0acfe22380 nb/intel: Replace remaining BAR accessors
These changes are not reproducible for some reason.

Change-Id: I43b445b8af8871db87fb86747db8a35cec75716a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51867
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10 15:54:25 +00:00
Angel Pons 66780a0c9f nb/intel/sandybridge: Use new fixed BAR accessors
One instance in northbridge.c breaks reproduciblity when changed.

Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical.

Change-Id: I2148183827bcacc9e6edb91b26ad35eb2dae5090
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51866
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10 15:53:52 +00:00
Angel Pons 2e397aebad nb/intel/haswell: Use new fixed BAR accessors
There are some cases in `northbridge_topology_init` where condensing the
operation using one macro changes the binary, and have been left as-is.

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: I59c7d1f8d816b95e86d39dcbf7bc7ce8c34f0770
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51865
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10 15:53:28 +00:00
Angel Pons 936536cd2b nb/intel/common/fixed_bars.h: Add new read/write accessors
The {MCH,DMI,EP}BAR macros can be used for both reading and writing.
While this can sometimes be useful, compile-time overflow checking is
limited. Moreover, and-masks need to be bit-wise negated, which is easy
to forget and may result in spurious overflow warnings, and silencing
them with a cast also suppresses true integer overflow issues.

To address these limitations and for consistency with the existing MMIO
API (arch/mmio.h and device/mmio.h), these macros will be replaced with
prefixed wrappers around MMIO API functions. However, existing platform
code needs to be refactored, and the risk of introducing regressions is
substantial. To minimize the risk of breakage, the bulk of the platform
code changes will be verified using reproducible builds.

This patch introduces the new accessors, to be put to use in follow-ups.
These accessors are implemented as macros so that subsequent commits can
be verified using reproducible builds. They will be replaced with actual
functions after refactoring all platforms.

Change-Id: I85376a9e2f6cd042b41036f90de7f9edc7ad4508
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51864
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10 15:53:17 +00:00
Angel Pons 7720f1da36 nb/intel: Factor out remaining MCHBAR macros
Except for some formatting differences, the macros are equivalent.

Change-Id: I5dc4f115b0873fb96683263ecd152d3d1504647d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51863
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10 15:52:45 +00:00
Subrata Banik 8cbe43b8d7 soc/intel/alderlake: Skip D3Cold for TBT
Check TBT NVM FW Ready (INFR) bit to skip D3Cold for TBT when device
is in disconnected state.

Not adhering this recommendation is blocking the S0ix state transition.

BUG=b:183670327
TEST=S0ix state transition occurs with TBT disconnected.

Change-Id: Ib9b9ceee4393aeba37fdcb4e05d1b279a6ff72d2
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-04-10 12:00:33 +00:00