Commit Graph

26250 Commits

Author SHA1 Message Date
Seunghwan Kim aef592d9b6 mb/google/poppy/variants/nautilus: Set grip sensor threshold
Set threshold parameter for grip sensor STH9321
.ProxCtrl6: 75
.ProxCtrl7: 99

BUG=b:113303916
BRANCH=poppy
TEST=Built and verified  parameter passed to driver

Change-Id: I8a410a23b5e3831fc8e90118b810fc2409a026eb
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/28381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Enrico Granata <egranata@chromium.org>
2018-08-30 18:59:10 +00:00
Lijian Zhao d145c95208 soc/intel/cannonlake: Fix comment errors for SMBUS
On CannonLake PCH, SMBUS stays at Bus 0 Device 31 and Function 4,
previous comment in southbridge.asl mention it as Function 3 that was a
mistake.

BUG=N/A
TEST=N/A

Change-Id: I29786457379809b6fcb592e1136ff612539e24dc
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-08-30 14:48:43 +00:00
Xiang Wang 0e788c985c riscv: update the definition of intptr_t/uintptr_t
These RISC-V ABIs defined by GCC : ilp32 ilp32d ilp32f lp64 lp64d lp64f.
Through this we know that the length of the long's bit is equal to pointer.
So update this code. This's more flexible.

Change-Id: I16e1a2c12c6034df75dc360b65acb1b6affec49b
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/27768
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-30 14:48:26 +00:00
Martin Roth b69ae97ada util/abuild: Use env to find bash
FreeBSD doesn't have bash in /bin, so use env to find it.  This is
already done in many other scripts that are used in the actual build
path.

Change-Id: If6fb6bc3c55835e2144599fea1cdb2f7abefb0fc
Signed-off-by: Martin Roth <martinr@coreboot.org>
Reviewed-on: https://review.coreboot.org/28364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
2018-08-30 14:48:09 +00:00
Richard Spiegel 6635b3d9a1 soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port()
Function pci_ehci_dbg_set_port() used NDA register DEBUGPORT_MISC_CONTROL,
which was deprecated in favor of a public PCI register (though only the
bits to enable debug port became public) 0x90. Therefore code needs to be
updated.

BUG=b:69231009
TEST=Build and boot grunt.

Change-Id: Ibb25992729d984b8570712f91a03a7cd1e9b8643
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-30 14:47:52 +00:00
Angel Pons 8120759d90 Documentation/nb/intel/sandybridge/nri_registers.md: Fix mistake
According to a comment on fa1a07b, the 100MHz clock is the Ivy Bridge
only clock, not the 133MHz one.

Change-Id: I28fed4a9264b96f93b9e88325f547a5db512514c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28377
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-30 14:47:41 +00:00
Shamile Khan 0805cbe6ae mb/google/octopus: Add missing IOstandy settings.
Also removed internal pull ups for CX_PREQ_L and
CX_PREQ_L signals as they have external pull ups.

BUG=b:110654510
TEST=On Yorp Proto 2, flashed image and verified that it boots to OS.
Checked Wake-on-Wifi works with both cnvi and pcie modules. 
Also executed a few suspend resume cycles. 

Change-Id: I0a76cd2a1481c828fc092aaf7e870a411624879c
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/28328
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-30 14:47:23 +00:00
Maulik V Vaghela 9b08a18966 soc/intel/cannonlake: Update PMC base address for CNP H and LP
PMC base address is different for CNP LP pch and CNP H pch.
Added logic to determine PMC base addrress dynamically based on PCH ID.

BUG=none
BRANCH=none
TEST=Boot Coffeelake U RVP board and check if PMC base address is
determined correctly.

Change-Id: I833395260e8fb631823bd03192a092df323250fa
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/27523
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-30 14:47:04 +00:00
Nico Huber 58344fc2e7 drivers/intel/gma: Fix OpRegion Mailbox3 backlight change
We should always update BCLP, no matter if the driver is ready yet to
process the request. This way it will hold the current value when the
driver initializes.

Change-Id: I4b091d744f95da39abe542966f0a8589a187573b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-30 14:45:50 +00:00
Alexander Couzens 661907cdb4 drivers/intel/gma: store uint8_t brightness values in mailbox3
The _BCM function requires a percentage value. While the
brightness in mailbox3 requires a value in uint8_t. Meaning 255 = 100%.
Previous implementation stored the percentage brightness value resulting
in limiting the brightness to ~40% of it's maximum power.

Only affects brightness control using mailbox3.

Fixes: 6838aaebf9 ("drvs/intel/gma/acpi: Add methods to use MBOX3")
Change-Id: I290b5f5b2a8ee406e39e86d3e0de9997798d890d
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/28345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-30 14:45:23 +00:00
Martin Roth 6bbfb3bfd6 mainboard/google/kahlee: Enable EC firmware update screen
Grunt takes a few seconds to update the EC, so display a notification
screen while that's happening.

BUG=b:113286040
TEST=Boot Grunt with old EC firmware, see update screen

Change-Id: I95fc4d3430bac66c09f57a4d34abde08752e5f0e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/28374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-08-29 21:06:14 +00:00
Richard Spiegel 4cafc88619 lib/gpio.c: Validate num_gpio
In function _gpio_base3_value(), if num_gpio is 0 it'll cause the return
of an undefined value, as no for loop will be executed. Assert that it's
not 0.

BUG=b:112253891
TEST=Build and boot grunt.

Change-Id: I2b6537900fa41ebbee0171959f3ce236d360bc80
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-28 15:36:51 +00:00
Tony Huang 78f2343aa2 mb/google/octopus/variants/meep: Add weida touchscreen support
Add weida touchscreen support

BUG=none
BRANCH=master
TEST=emerge-octopus coreboot, and verified that touchscreen works on
meep.

Change-Id: I4352322820237e4c2289410af6643e15109060a1
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-28 15:16:24 +00:00
Lijian Zhao 903c9764a1 soc/intel/cannonlake: Change LPDDR4 to MEMCFG
Modify the previously SOC_CNL_LPDDR4_INIT to SOC_CNL_MEMCFG_INIT, to
make the infrasturture to handle both LPDDR4 and DDR4 cases in the
future. Consider the case of reading SPD from SMBus other than providing
SPD pointer directly.

BUG=N/A
TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a"
compiles successfully.

Change-Id: I2f898147f67dd52b89cc3d9fc4e6b3854fa81f57
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28248
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-28 15:15:26 +00:00
David Wu 5dff396bef acpi: Hide Chrome and coreboot specific devices
Some ACPI interfaces introduced by Chrome or coreboot do not
need drivers outside ChromeOS, for example Chrome EC or
coreboot table; or will be probed by direct ACPI calls (instead
of trying to find drivers by device IDs).

These interfaces should be set to hidden so non-ChromeOS systems,
for example Windows, won't have problem finding driver.

Interfaces changed:
- coreboot (BOOT0000), only used by Chrome OS / Linux kernel.
- Chrome OS EC
- Chrome OS EC PD
- Chrome OS TBMC
- Chrome OS RAMoops

BUG=b:72200466
BRANCH=eve
TEST=Boot into non-ChromeOS systems (for example Windows)
     and checked ACPI devices on UI.

Change-Id: I9786cf9ee07b2c3f11509850604f2bfb3f3e710a
Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/1078211
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Tested-by: Hung-Te Lin <hungte@chromium.org>
Trybot-Ready: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/28333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-28 15:14:42 +00:00
Lucas Chen 216345dd24 eve: Specify a unique ID for PS2 devices
Windows certification tests will fail if the PS2 devices are using Plug
and Play ID (PNP0303). For all Chromebooks we should use GOOG000A.

BRANCH=eve
BUG=b:110066056
TEST=AltOS certification test verify.

Change-Id: I479471fdb3102e3b492612a4e6ad07612273083a
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/1098874
Reviewed-by: Matt Delco <delco@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Trybot-Ready: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/28334
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-28 15:13:46 +00:00
Lijian Zhao f3122426b8 fsp/fsp2_0/coffeelake: Update CFL FSP headers
Coffeelake FSP headers had been updated to version 7.0.3D.60. Original
file location from https://github.com/IntelFsp/FSP/tree/master/
CoffeeLakeFspBinPkg/Include .

BUG=N/A
TEST=Build and flash, able to boot up into OS on whiskeylake rvp
platform.

Change-Id: I656da83e9042642576b785643e423ba47da8dd73
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28286
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-28 15:12:44 +00:00
Tristan Shieh 990d825196 google/kukui: Init SPI bus for EC
Set EC SPI bus config and init SPI bus according to the config.

BUG=b:80501386
BRANCH=none
TEST=EC is not working yet. This makes depthcharge go forward a little.

Change-Id: Id9209b6429417430cfcf7f5a5a1659e7e4bc7866
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/28251
Reviewed-by: Joel Kitching <kitching@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-28 15:12:14 +00:00
Tristan Shieh fdcc0b3915 google/kukui: Set up GPIOs for ChromeOS
Set up EC interrupt GPIO to boot depthcharge. Without this patch,
depthcharge will fail to detect EC interrupt GPIO.

BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui and see in logs, that depthcharge detects
     EC interrupt GPIO.

Change-Id: I0ec2c70c189a059219954e0384aaf98995285728
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/28250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-08-28 15:12:05 +00:00
Tom Hiller 3762e99893 Documentation: Normalize release note headings
Headings are used to populate release note TOC.

Change-Id: I39b018ed4498555044616a3aa660abe1047b5449
Signed-off-by: Tom Hiller <thrilleratplay@gmail.com>
Reviewed-on: https://review.coreboot.org/27720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-28 15:09:36 +00:00
Tom Hiller 2436349a3b Documentation: fix release version linking
Correct links to coreboot release notes and fix related "document
isn't included in any toctree" warnings.

Change-Id: I6563da6f82f5686e54791331312434828c63f5a6
Signed-off-by: Tom Hiller <thrilleratplay@gmail.com>
Reviewed-on: https://review.coreboot.org/27719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-28 15:09:19 +00:00
Elyes HAOUAS 446e4d73cb util/ipqheader: Fix typo
Change-Id: Ibfcb870bb6e7ed747f8875520ab094def49e53cb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-08-28 14:23:09 +00:00
Elyes HAOUAS 8fda8f4ac3 util/romcc: Fix typos
Change-Id: Ia9f0f1f527476900e6c54c60508600e16bea786f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-28 14:22:24 +00:00
Elyes HAOUAS 3db0198358 util/cbfstool: Fix typos
Change-Id: I6967a106ce1286d633ddeeb041f582e65f9ea78c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-28 14:20:15 +00:00
Elyes HAOUAS 7bb53aa386 util/scripts: Fix typo
Change-Id: If906e230c0cb71fc3cd283aeb85f8d1338c303c6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-08-28 14:19:33 +00:00
Elyes HAOUAS 75db596654 util/msrtool: Fix typos
Change-Id: I36ed2c33f9bed3e640871283c2cb163d6800d1d5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-28 14:19:13 +00:00
Mario Scheithauer 403458e7ec siemens/mc_apl1: Extend circuit life by clock gating and power gating
The firmware of devices connected to LPC should deassert the LPC CLKRUN#
signal when there is no bus activity on LPC.

Necessary changes:

- Enable LPC CLKRUN#
- Enable LPC PCE (Power Control Enable)
- Enable LPC CCE (Clock Control Enable)
- Remove I/O decoding range on LPC for COM 3
- Disable I/O UART driver

Change-Id: I2fd80e3fdcf23658f97b8182a77df7e09ddf25d6
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/28268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-28 14:18:40 +00:00
Richard Spiegel 24ad29e83c vendorcode/amd/pi/00670F00: Remove IDS headers
Only Ids.h had definitions still in use, and they were removed or moved to
AGESA.h. Now Ids.h, IdsPerf.h and IdsLib.h can be safely removed.

BUG=b:112885948
TEST=Build grunt

Change-Id: I031ae8eb5f34fee801365fc89ea11a881211e726
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28299
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-28 14:17:41 +00:00
Richard Spiegel 90b3149deb vendorcode/amd/pi/00670F00: Transfer TP_Perf_STRUCT to AGESA.h
Google is creating code to measure AGESA performance, which needs structure
TP_Perf_STRUCT and associated definitions. In preparation to remove IDS
headers, move the necessary definitions to AGESA.h.

BUG=b:112885948
TEST=Build grunt

Change-Id: I941a67a8889a9dbf35c9fd511c7f670623204134
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-28 14:17:10 +00:00
Kevin Chiu 328ff7dee0 google/grunt: Reset BayHub EMMC freq to SD base CLK 50MHz
Bayhub eMMC controller default runs SD base 50MHz at the first power on.
After boot into OS, mmc kernel driver will config controller to HS200/208MHz
and send MMC CMD21 (tuning block).
But Bayhub PCR register 0x3E4[22] (eMMC MODE select) is not clear
after system warm reset.
So eMMC will still run 208Mhz but there is no block tuning cmd in depthcharge.
It will cause two Sandisk eMMC (SDINBDA4-64G-V/SDINBDA4-32G-V) to fail to
load kernel and trap in 0x5B error (No bootable kernel found on disk).

BUG=b:111964336
BRANCH=master
TEST=emerge-grunt coreboot
Change-Id: Ic080682e67323577c7f0ba4ed08f8adafca620cc
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/28353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-28 14:15:57 +00:00
Elyes HAOUAS 6b5c3c2953 src/drivers/pc80/pc: Remove unneeded include
Change-Id: Ic238181d5c26ab8cf549137824a7c5e6c6d80ab1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-28 12:48:50 +00:00
Furquan Shaikh 0c87b55266 drivers/intel/wifi: Make WIFI_SAR_CBFS user visible
This change makes WIFI_SAR_CBFS user selectable option so that it can
be enabled/disabled from menuconfig along with the SAR filepath.

BUG=b:112425861

Change-Id: Idf6feaefe68e7ebf6786c2c36e92a054fba4483c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-27 23:29:29 +00:00
Elyes HAOUAS fcd70085c2 util/nvramtool: Fix typos & remove unneeded whitespace
Change-Id: I0a704cba80d0439ae95db34a6b73df7be5b3b862
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28290
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-27 22:41:57 +00:00
Richard Spiegel 982c7555ad vendorcode/amd/pi/00670F00: Transfer IDS_CALLOUT to AGESA.h
Currently, IDS_CALLOUT macros are only used in stoneyridge callout. In
preparation to remove IDS headers, move the definitions to AGESA.h.

BUG=b:112885948
TEST=Build grunt

Change-Id: Ia9717eb68fed2e568eaf169157c2837bb8232b7e
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-08-27 19:34:01 +00:00
Tom Hiller 993869e3fc Documentation: Fix formatting
Fix formatting and missing close block quotes in nri_registers.md

Change-Id: I5fa0136f4d7f05737a0d53ff9da7d2c77b22d675
Signed-off-by: Tom Hiller <thrilleratplay@gmail.com>
Reviewed-on: https://review.coreboot.org/28327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-08-27 16:53:06 +00:00
Tom Hiller c3e5dd4cd8 Documentation: Fix make rule for sphinx-autobuild
Execute sphinx-autobuild for livesphinx make rule

Change-Id: I725392f1f132101eede8fed75e8d225c972ad1fe
Signed-off-by: Tom Hiller <thrilleratplay@gmail.com>
Reviewed-on: https://review.coreboot.org/28326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-08-27 16:52:46 +00:00
Todd Broch 5e90ef8c35 mb/google/poppy/variants/atlas: Update DPTF parameters
Reduce the CPU passive threshold sample rate from 5 seconds to 1
second so DPTF will react faster to rapid temperature increases.

Signed-off-by: Todd Broch <tbroch@chromium.org>

BUG=b:113101335
BRANCH=atlas
TEST=manual performance/power testing on nocturne.

No longer see messages like below in syslog,
  'CPU0: Package temperature above threshold'

Change-Id: I2dc9d157b54500bae29e123978bb8ad6e05ef619
Reviewed-on: https://review.coreboot.org/28325
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-27 16:52:12 +00:00
Todd Broch 79f99f640c mb/google/poppy/variants/nocturne: Update DPTF parameters
Reduce the CPU passive threshold sample rate from 5 seconds to 1
second so DPTF will react faster to rapid temperature increases.

Signed-off-by: Todd Broch <tbroch@chromium.org>

BUG=b:67459049
BRANCH=nocturne
TEST=manual performance/power testing on nocturne.

No longer see messages like below in syslog,
  'CPU3: Package temperature above threshold'

Change-Id: Ic20c718fd3a496db7c7192feec4f230d924cc458
Reviewed-on: https://review.coreboot.org/28324
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-27 16:51:44 +00:00
Richard Spiegel 65bba289ee vendorcode/amd/pi/00670F00/Include/Ids.h: Remove IDS_ERROR_TRAP
The macro IDS_ERROR_TRAP is only defined, and never used. Also,
IDSOPT_ERROR_TRAP_ENABLED is defined FALSE, so the macro would translate
to nothing. Remove the macro and IDSOPT_ERROR_TRAP_ENABLED.

BUG=b:112885948
TEST=Build grunt

Change-Id: I2c3ca4b0a4a1f96f245ba2f4902fd0051dda77ef
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-08-27 16:19:27 +00:00
Richard Spiegel 4c7349cf85 vendorcode/amd/pi/00670F00/Lib/AmdLib.c: Remove IdsErrorStop
Function IdsErrorStop() is only used within AmdLib.c function
LibAmdMsrRead(), which in turn is only used once within PspBaseLib.c and
three times inside AmdLib.c, all with well defined MSR addresses.
IdsErrorStop() is used as a trap if MSR address is 0 or 0xFFFFFFFF, which
clearly it's not. Therefore it can be safely removed from AmdLib.c.

BUG=b:112885948
TEST=Build grunt

Change-Id: I47ffcbd4fbae28b6d711a340f0ac3f3b007e8e4f
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-08-27 15:59:12 +00:00
Sumeet Pawnikar 837e3387e5 mb/google/octopus/variants/baseboard: Update DPTF parameters
Update TSR1 trip point from 48C to 50C.
Also, change power limit2 minimum value from 8W to 10W.
These are the values as per recent thermal tuning.

BUG=b:79779737
BRANCH=None
TEST=Build coreboot for Octopus board.

Change-Id: I33a9d2dc3e0e5566d95b1f1e46d3922dc8965b2b
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/28187
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-27 15:55:06 +00:00
Marc Jones 7a5f0a9817 lib/nhlt: Use common function to set NHLT version
Set NHLT version with get_acpi_revision(NHLT) to keep all table versions
in sync.

Change-Id: I4ea9d511142e4ea68e651e58c2c985e739c032d9
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/28279
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-27 15:54:34 +00:00
Akshu Agrawal 478f430182 mb/google/kahlee: Fix I2C bus 0 timing for Grunt
This commit fixes the values and thus fixes the issue of
audio device not getting detected on random reboots.

Change-Id: I34a4f62815d192005c3324d4f71b0aba377fe738
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/28280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2018-08-27 15:54:13 +00:00
Elyes HAOUAS 4b2d865820 mb/supermicro/h8qme_fam10: Use common pnp_{enter,exit} functions
Change-Id: Ie3ee4acfd272991133f02a56df6e23aa6071d3e9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-27 15:53:25 +00:00
Elyes HAOUAS 5d4cf36044 mb/kontron/986lcd-m: Use common pnp_{enter,exit} functions
Some unneeded includes are also removed.

Change-Id: Icd518c46d8503d11d24466c30840d7e514e9a05d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-27 15:53:14 +00:00
Marc Jones 8abf6ae757 intel: Use common HPET table revision function
Use get_acpi_table_revision(HPET) to keep all table versions in sync.

Change-Id: Idb5e8ccd49ec27f87a290f33c62df3c177645669
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/28278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-27 15:50:52 +00:00
Marc Jones 4ddd47697e x86/acpi: Update MADT table version
Update the MADT table version to sync with the FADT table version.
All current coreboot FADT tables are set to ACPI_FADT_REV_ACPI_3_0
and the MADT should be set to match.

This error was found by running FWTS:
FAILED [MEDIUM] SPECMADTFADTRevisions: Test 2, MADT revision is not in sync with
the FADT revision; MADT 1 expects FADT 3.0 but found 4.0 instead.

BUG=b:112476331
TEST-Run FWTS

Change-Id: If5ef53794ff80dd21f13c247d17c2a0e9f9068f2
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/28256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-27 15:50:17 +00:00
Marc Jones f9ea7edea8 update all FADT version 3.0 to use the get tables function
Most FADT report using ACPIv3 FADT table. Using the get revision
function keeps the table versions in sync.

Change-Id: Ie554faf1be65c7034dd0836f0029cdc79eae1aed
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/28277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-27 15:49:32 +00:00
Marc Jones 93a51766aa x86/acpi: Add ACPI table revision function
Use a single function to set ACPI table versions. This allows us
to keep revisions synced to the correct levels for coreboot. This
is a partial fix for the bug:

FAILED [MEDIUM] SPECMADTFADTRevisions: Test 2, MADT revision is not
in sync with the FADT revision; MADT 1 expects FADT 3.0 but found 4.0
instead.

BUG=b:112476331
TEST-Run FWTS

Change-Id: Ie9a486380e72b1754677c3cdf8190e3ceff9412b
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/28276
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-27 15:48:30 +00:00
Marc Jones f2592f9bce vendorcode/amd/cimx/sb*: Rename RSDP header
Rename RSDP to RSDP_HEADER to match other AMD vendorcode and
to not pollute the namespace. We will use RSDP in a future patch.

Change-Id: I3b66135ae1732b86b5ebfcdc01a850a0d9d3eb50
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/28294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-27 15:26:33 +00:00