Commit graph

808 commits

Author SHA1 Message Date
Aaron Durbin
b0f81518b5 chromeos mainboards: remove chromeos.asl
Use the ACPI generator for creating the Chrome OS gpio
package. Each mainboard has its own list of Chrome OS
gpios that are fed into a helper to generate the ACPI
external OIPG package.  Additionally, the common
chromeos.asl is now conditionally included based on
CONFIG_CHROMEOS.

Change-Id: I1d3d951964374a9d43521879d4c265fa513920d2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15909
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-30 01:36:32 +02:00
Subrata Banik
89f6d6079e skylake/devicetree: Add LPC EC decode range
Define LPC decode ranges for EC communication.

BUG=chrome-os-partner:55357
BRANCH=none
TEST=Built and boot kunimitsu to ensure no EC timeout error

Change-Id: Idefdd79e67e89a794195c6821fee16550d1eda53
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/15898
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-28 05:17:56 +02:00
Subrata Banik
50b9258a0b skylake/mainboard: Define mainboard hook in bootblock
Move mainboard post console init functionality (google_chrome_ec_init &
early_gpio programming) from verstage to bootblock.

Add chromeos-ec support in bootblock

BUG=chrome-os-partner:55357
BRANCH=none
TEST=Built and boot kunimitsu till POST code 0x34

Change-Id: I1b912985a0234d103dcf025b1a88094e639d197d
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/15786
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-28 05:17:03 +02:00
Furquan Shaikh
0325dc6f7c bootmode: Get rid of CONFIG_BOOTMODE_STRAPS
With VBOOT_VERIFY_FIRMWARE separated from CHROMEOS, move recovery and
developer mode check functions to vboot. Thus, get rid of the
BOOTMODE_STRAPS option which controlled these functions under src/lib.

BUG=chrome-os-partner:55639

Change-Id: Ia2571026ce8976856add01095cc6be415d2be22e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15868
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-28 00:36:22 +02:00
Furquan Shaikh
2a12e2e8da vboot: Separate vboot from chromeos
VBOOT_VERIFY_FIRMWARE should be independent of CHROMEOS. This allows use
of verified boot library without having to stick to CHROMEOS.

BUG=chrome-os-partner:55639

Change-Id: Ia2c328712caedd230ab295b8a613e3c1ed1532d9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15867
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-28 00:36:00 +02:00
Furquan Shaikh
610a33a7f4 skylake: Move CHROMEOS config to SoC
All the mainboards share the same config options for CHROMEOS. Instead
of duplicating those in every mainboard, move the CHROMEOS config to SoC
and make it dependent on MAINBOARD_HAS_CHROMEOS.

BUG=chrome-os-partner:55431

Change-Id: Iafabb6373dfe16aaf0fe2cbc4e978952adeb403e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15822
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-07-25 18:55:21 +02:00
Furquan Shaikh
87b1bcc4af apollolake: Move CHROMEOS config to SoC
All the mainboards share the same config options for CHROMEOS. Instead
of duplicating those in every mainboard, move the CHROMEOS config to SoC
and make it dependent on MAINBOARD_HAS_CHROMEOS.

BUG=chrome-os-partner:55431

Change-Id: I2d54ff6beac9fca7596a8f104e3c1447cada5c05
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15821
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-07-25 18:55:01 +02:00
Furquan Shaikh
b1b465f093 intel/amenia: Add chromeos.c to verstage
BUG=chrome-os-partner:55431

Change-Id: I94fe54c12d7438a71f81a9053cc9785c0aa1e6cf
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15823
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-25 18:54:50 +02:00
sselvar2
9d29c3cc31 intel/amenia: Write protect GPIO relative to bank offset
Update the write protect GPIO reported in ACPI to GPIO_75.
Also update the controller ID to "INT3452:01" which will
point at the goldmont device and includes write protect GPIO.

BUG=none
BRANCH=none
TEST=verify crossystem output for wpsw_cur.

Change-Id: Id6b172e289976072836746c1814e0300544a06cb
Signed-off-by: sselvar2 <susendra.selvaraj@intel.com>
Reviewed-on: https://coreboot.intel.com/7771
Reviewed-by: Sparry, Icarus W <icarus.w.sparry@intel.com>
Reviewed-by: Petrov, Andrey <andrey.petrov@intel.com>
Tested-by: Petrov, Andrey <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15496
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-22 18:59:36 +02:00
Harsha Priya
00aa45391d intel/amenia: Add DA7219 support in acpi
Add DA7219 support in acpi.
DA7219 has advanced accessory detection functionality.
Also add DA7219's AAD as a ACPI data node.

Change-Id: I979275cb2ab1e593ff1e5d360bea83b843e45021
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/15625
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-07-19 21:06:52 +02:00
Shaunak Saha
9b4be0fce0 intel/amenia: Add wake-up from lid open
This patch adds support to wake up from S3 on lidopen.
mainboard.asl has the _PRW defined for the wakeup support
in S3.

BUG = chrome-os-partner:53992
TEST = Platform wakes up from S3 on lidopen.

Change-Id: I48b456baf5f7e1c2f28454fa66bb90ad761bb103
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15618
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-15 21:02:20 +02:00
Andrey Petrov
89e7b49a11 soc/intel/apollolake: Consolidate ISH enabling
Since the Integrated Sensor Hub can be disabled through devicetree.cb
as a PCI device, there is no need for a separate register variable.
Remove handling the register and update mainboards' devicetrees. Also
keep ISH disabled on both Reef and Amenia.

Change-Id: I90dbf57b353ae1b80295ecf39877b10ed21de146
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15710
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15 18:21:54 +02:00
Aaron Durbin
3969df875e mainboards/skylake: use common Chrome EC SMI helpers
Reduce duplicate code by using the Chrome EC SMI helper functions.

BUG=chrome-os-partner:54977

Change-Id: Ie83e93db514aa0e12e71d371d7afab34a70797fd
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15689
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-15 08:36:24 +02:00
Aaron Durbin
1a75560599 mainboards/apollolake: use common Chrome EC SMI helpers
Reduce duplicate code by using the Chrome EC SMI helper functions.

BUG=chrome-os-partner:54977

Change-Id: Iba2ca7185ad7f0566858ce99f5ad8325ecc243cf
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15687
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
2016-07-15 08:35:59 +02:00
Aaron Durbin
9fe0ff2f83 mainboards: remove direct acpi_slp_type usage
Use the acpi_is_wakeup_s3() API instead of comparing
a raw value to a global variable. This allows for
easier refactoring.

Change-Id: I2813b5d275cbe700be713272e3a88fdb5759db99
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15690
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2016-07-15 08:30:53 +02:00
Aaron Durbin
30b0c7adf0 mainboards: align on using ACPI_Sx definitions
The mainboard_smi_sleep() function takes ACPI sleep values
of the form S3=3, S4=4, S5=5, etc. All the chipsets ensure
that whatever hardware PM1 control register values are used
the interface to the mainboard is the same. Move all the
SMI handlers in the mainboard directory to not open code
the literal values 3 and 5 for ACPI_S3 and ACPI_S5.

There were a few notable exceptions where the code was
attempting to use the hardware values and not the common
translated values. The few users of SLEEP_STATE_X were
updated to align with ACPI_SX as those defines are
already equal. The removal of SLEEP_STATE_X defines is
forthcoming in a subsequent patch.

BUG=chrome-os-partner:54977

Change-Id: I76592c9107778cce5995e5af764760453f54dc50
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15664
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15 08:30:31 +02:00
Daisuke Nojiri
0562783182 Google Mainboards: Increase RO coreboot size on flash
Bitmap images will be moved to CBFS from GBB. This patch adjusts the
flash map accordingly for rambi, samus, peppy, parrot, falco, panther,
auron, and strago.

BUG=chromium:622501
BRANCH=tot
TEST=emerge-{samus,falco} chromeos-bootimage
CQ-DEPEND=CL:354710,CL:355100

Change-Id: I6b59d0fd4cc7929f0de5317650faf17c269c4178
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 201a82311ba539b9b02d546ba331ff5bf73e0edf
Original-Change-Id: I0b82285186540aa27757e312e7bd02957f9962ec
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/355040
Reviewed-on: https://review.coreboot.org/15658
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15 00:37:52 +02:00
Shaunak Saha
bc62834306 intel/amenia: Add mainboard SMI handler
This patch adds a mainboard SMI handler file which has
functions to set proper Wake mask before going to sleep
so that system can wake up on lidopen, key press etc.
Also SCI mask is set on boot which will enable timely update
of battery UI on charger connect/disconnect.

BUG = chrome-os-partner:53992
TEST = Amenia platform wakes from S3 on lidopen, key press and also
       sysfs entry for AC is updated on charger connect/disconnect.

Change-Id: If3dc6924c51c228241b7a647566b97398326ec0e
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15616
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-14 06:00:42 +02:00
Harsha Priya
141ce41112 intel/amenia: Add Maxim98357a support
Adds Maxim98357a support for amenia
using the generic driver in drivers/generic/max98357

Change-Id: I333d4e810e42309ac76dd90c19f05cf3e3a518f1
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/15624
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-14 00:04:48 +02:00
Harsha Priya
f0416edc63 intel/amenia: Update gpio config for audio
This changelist updates gpio config for speaker SDMODE pin.
It disables speaker by default.
Audio kernel is expected to enable this when audio rendering starts.

Change-Id: Id33ad29e637bf1fe6b02e8a4b0fd9e220e8983b6
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/15623
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-07-14 00:03:12 +02:00
Aaron Durbin
c79101ab84 mainboard/intel/amenia: use new gpio interrupt macros
Utilize the new interrupt macros in order to specify correct
polarity of the gpio interupts. Some of the interrupts were
working by catching the opposite edge of the asserted interrupt.

BUG=chrome-os-partner:54977

Change-Id: I55bee2c4363cfdbf340a4d5b3574b34152e0069c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15646
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-07-13 21:58:11 +02:00
Jagadish Krishnamoorthy
d41a338d55 intel/amenia: Disable unused PCIe ports
Disable PCIe A0, A1, A2, A3, B1 ports.
Enable B0 port which is used for wifi.

BUG=chrome-os-partner:54288
BRANCH=None
TEST=lspci should show only PCIe B0 device

Change-Id: I266d6eb7ddd56888f6b07b59681c2d9f0a6c0a9e
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Reviewed-on: https://review.coreboot.org/15599
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-13 19:58:12 +02:00
Kyösti Mälkki
b6fc727903 FSP1_0 does not support HAVE_ACPI_RESUME
FSP1_0 places romstage ram stack at fixed location of
RAMTOP in low memory before returning to coreboot proper.
There is no possibility of making a complete backup of
RAMBASE..RAMTOP region and currently such backup is not
even attempted.

As a conclusion, S3 resume would always cause OS memory
corruption.

Change-Id: I5b9dd4069082e022b01b0d6a9ad5dec28a06e8b0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15576
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-13 18:35:03 +02:00
Shaunak Saha
6e5c5a15bc intel/amenia: Add GPE routing settings
This patch sets the devicetree for gpe0_dw configuration
and also configures the GPIO lines for SCI. EC_SCI_GPI
is configured to proper value.

BUG = chrome-os-partner:53438
TEST = Toggle pch_sci_l from ec console using gpioset command
       and see that the sci counter increases in /sys/firmware/acpi/interrupt
       and also 9 in /proc/interrupt

Change-Id: I3ae9ef7c6a3c8688bcb6cb4c73f5618e7cde342c
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15325
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-12 20:38:56 +02:00
Lee Leahy
dc54270210 soc/intel/quark: Pass in the memory initialization parameters
Specify the memory initialization parameters in
mainboard/intel/galileo/devicetree.cb.  Pass these values into FSP to
initialize memory.

TEST=Build and run on Galileo Gen2

Change-Id: I83ee196f5fb825118a3a74b61f73f3728a1a1dc6
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15260
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-08 17:59:20 +02:00
Lee Leahy
5d94c26653 mainboard/intel/galileo: Gen1 - Set correct I2C scripts
Switch the I2C scripts to properly match the I2C address selection for
the Galileo Gen1 board.

TEST=Build an run on Galileo Gen1

Change-Id: I9fc8b59a3a719abb474c99a83e0d538794626da9
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15258
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-08 17:59:06 +02:00
Hannah Williams
7124882aeb board/intel/amenia: Enable LPSS S0ix
This setting will enable S0ix for LPSS

Change-Id: Ie07cb8437d0cee61a03638aa980fd3322fef0c4e
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/15056
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-07-07 17:02:57 +02:00
Saurabh Satija
90e716691d mainboard/intel/amenia: add NHLT support
Add ACPI NHLT table generation that the current hardware
supports as well select the hardware used on the board.

Amenia has support for two audio codecs, Dialog for
headsets and Maxim for speakers.

Change-Id: Iaba9ec81ffb4f128f2e4413dec5174d9ecb856c9
Signed-off-by: Saurabh Satija <saurabh.satija@intel.com>
Reviewed-on: https://review.coreboot.org/15024
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-01 03:21:22 +02:00
Kyösti Mälkki
65e8f647bc intel romstage: Use run_ramstage()
Change-Id: I22a33e6027a4e807f7157a0dfafbd6377bc1285d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15461
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-29 07:32:43 +02:00
Jagadish Krishnamoorthy
2dd226a713 intel/amenia: Configure unused Pads
Configure unused Pads as NC
and sort the pads according to the gpio community.

Move the pad configurations from mainboard to gpio.h

BUG=none
TEST=Boot to OS and check all functionalities.

Change-Id: I8e9eeebf5d75c71c521649c72612c06f3fa43701
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Reviewed-on: https://review.coreboot.org/15327
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-28 20:43:22 +02:00
Jagadish Krishnamoorthy
c58b9c9d76 intel/amenia: disable unused devices
BRANCH=none
BUG=chrome-os-partner:54325
TEST=device off in devicetree should disable the device.

Change-Id: I486a4c5e8970047477068e22b799d06caea03330
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Reviewed-on: https://review.coreboot.org/15338
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-27 22:32:46 +02:00
Duncan Laurie
9482cf6c09 intel/kunimitsu: Move devices from mainboard.asl to devicetree
Declare the mainboard attached devices in the devicetree and enable
the provided device drivers by default to generate the ACPI objects
for these devices.  Then remove the static ACPI objects from the DSDT
in mainboard.asl.

This was tesed on a Chell mainboard since I lack a kunitmisu device.
I used different GPIOs across boots to verify that the different
audio codec devices would be "detected" and generated in the SSDT.

Change-Id: I9b3b2247a84aeb7c07780958377d5bea14417ce6
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15317
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-06-24 20:14:23 +02:00
Kyösti Mälkki
0306e6a8bf intel/sandybridge: Fix builds with System Agent blob
Broken with commit:
  5c10abe nb/intel/sandybridge: increase MMCONF_BASE_ADDRESS

Available sandybridge/systemagent-r6.bin has MMCONF hard-coded
at some places and samsung/lumpy fails at boot here:

  CBFS: Locating 'mrc.bin'
  CBFS: Found @ offset 9fec0 size 2fc94
  System Agent: Starting up...
  System Agent: Initializing

These are the last lines as captured over USB debug.

Change-Id: I441847f0e71a5e1be9c8ef6a04a81eb7bdd8a6d9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15328
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-23 21:52:46 +02:00
Furquan Shaikh
0e820ce745 mainboard: Remove use of IFD_BIOS_START/IFD_BIOS_END
BUG=chrome-os-partner:54563

Change-Id: If07710333cbb84ce70d6d4fa40602a74c898c08a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15293
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-06-22 22:21:13 +02:00
Kyösti Mälkki
15fa992cc8 intel/model_6ex: Prepare for dynamic CONFIG_RAMTOP
Change-Id: I9bfaa53f8d09962d36df1e86a0edcf100bb08403
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15229
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21 00:49:12 +02:00
Kyösti Mälkki
408d392823 intel/car/cache_as_ram_ht.inc: Prepare for dynamic CONFIG_RAMTOP
Change-Id: Idb0f621553e76e771a5d6f2d492675ccd989d947
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15228
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21 00:43:20 +02:00
Kyösti Mälkki
07921540dd intel/car/cache_as_ram.inc: Prepare for dynamic CONFIG_RAMTOP
Change-Id: I02881ce465cb3835a6fa7c06b718aa42d0d327ec
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15227
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-06-21 00:39:47 +02:00
Lee Leahy
db601b6818 mainboard/intel/galileo: Support bootblock in C
Initialize the GPIOs during the boot block to properly route the SOC
UART pins.

TEST=Build and run on Galileo Gen2

Change-Id: I22c24f8c83f04566a0bbd598a141a5209569a924
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15133
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-11 19:17:49 +02:00
Zhao, Lijian
1a718642ea intel/amenia: Program EMMC dll setting
EMMC TX DATA Control needs to be programmed to 0x1A1A to make amenia
system can run stable on EMMC with HS400 mode.

Change-Id: I42c23ff7e6956e75de5e1b1339a570b35d999301
Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com>
Tested-by: Petrov, Andrey <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15092
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-09 20:23:50 +02:00
Duncan Laurie
c8d45ac88e skylake: Move I2C bus configuration to separate structure
Move the existing I2C voltage configuration variable into a new
structure that is equivalent, similar to how USB ports are configured.

This is to make room for additional I2C configuration options like
bus speed and whether to enable the bus in early boot which are coming
in a subsequent commit.

The affected mainboards are updated in this commit so it will build.

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Id2dea3df93e49000d60ddc66eb35d06cca6dd47e
Reviewed-on: https://review.coreboot.org/15104
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-09 17:08:33 +02:00
Duncan Laurie
7f3156dad6 skylake: gpio: Add support for setting 1.8V tolerant
Add the voltage tolerance GPIO attribute for configuring I2C/I2S buses
that are at 1.8V.  This is currently done by passing in a value to FSP
but it is needed earlier than FSP if the I2C bus is used in verstage.

This does not remove the need for the FSP input parameter, that is
still required so FSP doesn't disable what has been set in coreboot.
The mainboards that are affected are updated in this commit.

This was tested by exercising I2C transactions to the 1.8V codec while
in verstage on the google/chell mainboard.

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I93d22c2e3bc0617c87f03c37a8746e22a112cc9c
Reviewed-on: https://review.coreboot.org/15103
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-06-09 17:07:26 +02:00
Ravi Sarawadi
5f8cdc641b mainboard/intel/amenia: Enable VIRT_DEV_SWITCH
Enable virtual dev switch config.

BUG=None
TEST= On Dev FW screen, press SPACE key to boot to normal mode

Change-Id: I0fba36ed85025e4d17da106978dcc88497afee09
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/15080
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-08 22:25:22 +02:00
Zhao, Lijian
1c6c5836bd Intel/amenia: Make the device address more readable
Use central header file to include device address and interrupt
line to avoid confusion.

Change-Id: I9560031d9f6e12c665c8ae12f7028a67b6c8c904
Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com>
Signed-off-by: Rohit Ainapure <rohit.m.ainapure@intel.com>
Reviewed-on: https://chromium.devtools.intel.com/7248
Tested-by: N, Harshapriya <harshapriya.n@intel.com>
Reviewed-by: Petrov, Andrey <andrey.petrov@intel.com>
Reviewed-on: https://chromium.devtools.intel.com/7580
Reviewed-by: N, Harshapriya <harshapriya.n@intel.com>
Tested-by: Petrov, Andrey <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15083
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-08 22:23:53 +02:00
Shaunak Saha
f7f1244bc6 intel/amenia: Add asl code to enable google ChromeEC
This patch adds asl code to include support for Google ChromeEC.
We need this to show the battery icon and notifications like charger
connect/disconnect etc.

BUG = 53096
TEST = Plug/Unplug AC Adapter multiple times and make sure the battery
       connected is charging properly.

Change-Id: Id908f145789402573ea54fc4f15cf7a0e651ebf4
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/14987
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-06-07 19:39:50 +02:00
Lee Leahy
287cd7563e mainboard/intel/galileo: Add CREATE_BOARD_CHECKLIST
Select CREATE_BOARD_CHECKLIST to create the checklist for the Quark SOC
and Galileo board.

TEST=Build and run on Galileo Gen2.

Change-Id: Ieb3e9a5a4c149cf160e11d44a515591b57fe5c83
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15004
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-03 17:30:05 +02:00
Lee Leahy
eb0e7bc976 mainboard/intel/galileo: Set board version
Return the correct board version in SMBIOS.

TEST=Build and run on Galileo Gen2

Change-Id: I97ec7bcd475142eb90930152da0244a3c5d09634
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15041
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-03 17:28:23 +02:00
Lee Leahy
bc518d5cab quark: Enable HSUART0 as console
The use of HSUART0 on galileo requires early initialization of the I2C
GPIO expanders to direct the RXD and TXD signals to DIGITAL 0 and 1
on the expansion connector.

TEST=None

Change-Id: I11195d79e954c1f6bc91eafe257d7ddc1310b2e7
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15010
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31 22:11:51 +02:00
Lee Leahy
fd91dee420 mainboard/intel/quark: Enable reg_access during romstage
Turn on reg_access during romstage.

TEST=Build and run on Galileo Gen2

Change-Id: Iff1616836d6031f43d7741693febefa0bf26b948
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15008
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31 22:10:03 +02:00
Lee Leahy
ca65bb7b4e mainboard/intel/galileo: Use HSUART1 for console
Select HSUART1 for console.

TEST=Build and run on Galileo Gen2

Change-Id: I4425af4dc8b3730b3fa2108d6cc2941bc22c2cdb
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15005
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31 22:02:52 +02:00
Lee Leahy
5e808cb811 mainboard/intel/galileo: Split out enabling FSP1_1
Split out enabling FSP 1.1 support to prepare for enabling FSP 2.0
support.

TEST=Build and run on Galileo Gen2.

Change-Id: Ic4e814bcf61f9480f98e2d7bc7a1648dec43a07d
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15001
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31 22:00:30 +02:00