As on most other boards, use tabs to indent the devicetree.
Change-Id: I1d2fd6e758a3b2dccb8fc43d425f4520fd2e544f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38075
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use subsystemid inheritance, which results in a much more compact
devicetree. In addition, align and correct various comments.
Change-Id: Iafce736691b62ae8f359c2d74f8bd3549493029a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Use lowercase for hex constants, remove registers that default to zero
already and drop outdated comment about AHCI mode.
Change-Id: I6833462ea11e988eaab7913cf98853cebe4c7a9f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
They default to zero already. Moreover, the comment about AHCI mode no
longer applies, as it was made the default mode.
Change-Id: Ife99a79df0289c6db87510ed917438bf47b7f6ca
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Replace a bunch of spaces with tabs, put host bridge and friends above
southbridge, fix "TPM Module" (Trusted Platform Module Module) and add
some empty lines to help the reader.
Change-Id: I3a89893f943057ef7a4f973eaa65dba259e8a49d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This comment seems to have been copied off some QEMU board. As it would
not apply to any veyron variant, drop it.
Change-Id: I70a2923520f5c59ae31d149920cf4b096e5a11d1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Use a consistent spelling for SoC (System-on-a-Chip), and fix a few
minor typos.
Change-Id: I29eacc9e93b2eb686ce945de0173844ef5eae1b9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This touches several mainboards. Replace the macro with C functions.
The presence of bootblock.c is assumed.
Change-Id: I583034ef0b0ed3e5a5e3dd680c57728ec5efbc8f
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Long-term plan is to support loading runtime configuration
from SPI flash as an alternative, so move these prototypes
outside pc80/.
Change-Id: Iad7b03dc985550da903d56b3deb5bd736013f8f1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38192
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch creates a common instance of northbridge.asl inside intel common
code (soc/intel/common/block/acpi/acpi) and changes cnl,icl & tgl soc code to
refer northbridge.asl from common code block.
TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify
Device(MCHC) presence after booting to OS.
Change-Id: Ib9af844bcbbcce3f4b0ac7aada43d43e4171e08b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38155
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B option is no longer
being used in the code. There's a runtime check for supporting
fast read dual output mode of the spi flash. Remove the references
to SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B.
Change-Id: Ie7d9d3f91f29a700f07ab33feaf427a872bbf7df
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38166
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove fixed IccMax values for all domains.
IccMax will be selected by CPU SKU in
fill_vr_domain_config function.
BUG=b:145094963
BRANCH=None
TEST=build coreboot and fsp with enabled fw_debug.
Flashed to device and checked the log.
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Change-Id: I3f623d143f66c4f6ec63705844c9be7173feeb52
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
These are meaningless for boards without SIO devices.
Change-Id: I252bba6ff1a2547fd0661ad3076470376e95bdd6
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
tune eDP delay time to 20 ms ensure satisfy panel spec
BUG=b:147270512
TEST=verify panel sequences by ODM.
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: Ia38fbcb976de55baae480d33c6000c91dc9de6bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38024
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: chris wang <Chris.Wang@amd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The BMC and tools interacting with it depend on metadata placed inside
the ROM in order the flash the BIOS.
Add a new tool smcbiosinfo, integrate it into the build system, and
generate a 128byte metadata file called smcbiosinfo.bin on build.
You need to provide the BoardID for every SMC mainboard through a new
Kconfig symbol: SUPERMICRO_BOARDID
Some fields are unknown, but it's sufficient to flash it using SMC
vendor tools.
Tested on Supermicro X11SSH:
* Flashing using the WebUI works
* Flashing using SMCIPMITool works
No further validation is done on the firmware.
Change-Id: Id608c2ce78614b45a2fd0b26d97d666f02223998
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
These should have been removed together with read_option().
Change-Id: Ia6f268ac4551de14f9821c789844adfdf428b843
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38177
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As on most other boards, use tabs to indent the devicetree.
Change-Id: If95f1ce6a5347658ecc32097a85b1b6bcc6a1114
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Let the linker trim unused net driver symbols when unused
in devicetree rather than being overly zealous in the Kconfig.
BUG=b:146592075,146999042,146999043
BRANCH=none
TEST=Boot to kernel.
Ensure we have ip address and corresponding mac
address with ifconfig.
Ensure ethernet controller shows up with lspci.
Change-Id: Ie98d0f9f9b77cb9ee4e52f6c95b68bcbdd94f2cc
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Clean up devicetree as nothing special is needed here.
BUG=b:142769041
BRANCH=none
TEST=builds
Change-Id: I0790631233fdcaa6a785d2cb41e79b8f2f469d44
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Unlike laptops and some trash cans, desktop boards do not have a lid.
Change-Id: I5f947e411a4c9295a294f55771cd123de6b1e702
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The majority of Socket AM1 APUs [1] - three out of five - have the integrated
VGA with 1002,9830 ID, while only one Sempron has 1002,9836. Since VGA_BIOS_ID
is already defined in fam16kb Kconfig as 1002,9830 ID, drop the value here.
[1] https://en.wikipedia.org/wiki/List_of_AMD_accelerated_processing_units#%22Kabini%22_(2013,_SoC)
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I75c815b13934afcb5be316f85933f7c200d55bbd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33777
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
NIDs 0x18 and 0x19 are flipped, and the verbs for NID 0x1b are instead
applied onto NID 0x1a. Fix that, so that it matches original Chromium
sources for the boards.
Change-Id: I20cc4b282602f8557fa4f25489adf899b7460a09
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Looks like the subvendor verb for codec #3 is erroneously using zero as
its codec number. Fix that.
Change-Id: I760533c229287627dd0548a06300c376e045302c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
