Currently, GPP_H0 gpio input rout is set to GPI_INT.
So, ACPI_GPIO_IRQ is required for GPP_H0 in devicetree
This change also aligns hatch's setting.
BUG=b:131742713
TEST=headset is working
Change-Id: Ie1264641bc4dfa5f98b6dab2d6f2133a6f9cbdb8
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ben Kao <ben.kao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
sarien/arcada:
GPIO_COMM_0/2/3/4: Enable gpio community all PM configuration
GPIO_COMM_1: Disable RCOMP clock gating due to GPP_D18 IRQ mapped for H1 TPM.
hatch:
GPIO_COMM_0/1/2/3: Enable gpio community all PM configuration
GPIO_COMM_4: Disable RCOMP clock gating due to GPP_C21 IRQ mapped for H1 TPM.
BUG=b:130764684
TEST=H1 TPM interrupt working find and able to boot from fixed boot media
Change-Id: Ia4d5483847a4d243b9038119d4bb5990591cc754
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
GPIO_COMM_0/2/3/4: Enable gpio community all PM configuration.
GPIO_COMM_1: Disable RCOMP clock gating due to GPP_D16 IRQ mapped for H1 TPM.
BUG=b:130764684
TEST=H1 TPM interrupt working find and able to boot from fixed boot media
Change-Id: I1f83f938f201c6574367960b1027555767cf6f3d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The system should boot fine to OS on pressing power button before the
system enters G3. However, on hatch, we observe that the system waits
for few seconds at "Starting kernel" and then resets, with SD card tray
inserted and SD_CD# pad reset config set to DEEP. Hence configuring SD_CD#
pad reset config to PLTRST.
BUG=b:129933011
TEST=Built and verified on hatch.
Change-Id: Ic4466b96332f095ff39b28d98607e95fc3d12d6a
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Set the system serial number from the VPD key "serial_number" and
the mainboard serial number from the VPD key "mlb_serial_number".
BUG=b:132970635
TEST=check serial number is set in SMBIOS based on VPD, and if there
is no VPD key found then it is empty.
Change-Id: Ia8f1486dcb1edc968b8eb1e6d989b10c05913aca
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32851
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The FSP will lock down the configuration of GPP_A12, which
makes the configuration of the GPIO pin on warm reset not
work correctly.
This is only needed for the Arcada variant since it is the only variant
that uses ISH.
BRANCH=sarien
BUG=b:132719369
TEST=ISH_GP6 now works on warm resets on arcarda
Change-Id: Icb3bae2c48eee053189f1a878f5975c6afe51c71
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32831
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the stoneyridge AcpiMmio code into soc/amd/common.
The SB800 southbridge introduced the MMIO hardware blocks at 0xfed80000
commonly known as AcpiMmio. Implementations beginning with Mullins
enable decode in PMx04. Older designs use PMx24 and allow for
configuring the base address. Future work may support the older version.
Comparing the documentation for AMD's RRGs and BKDGs, it is evident that
the block locations have not been reassigned across products. In some
cases, address locations are deprecated and new ones consumed, e.g. the
early GPIO blocks were simpler at offset 0x100 and the newer GPIO banks
are now at 0x1500, 0x1600, and 0x1700.
Note: Do not infer the definitions within the hardware blocks are
consistent across family/model products.
BUG=b:131682806
Change-Id: I083b6339cd29e72289e63c9331a815c46d71600d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32649
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This allows for serial console during the bootblock and enables
bootblock console by default.
Change-Id: I7746e4f819486d6142c96bc4c7480076fbfdfbde
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Previously broadwell used a romcc bootblock and starting verstage in
romstage was madatory but with C_ENVIRONMENT_BOOTBLOCK it is also
possible to have a separate verstage.
This selects using a separate verstage by default but still keeps the
option around to use verstage in romstage.
With a separate verstage the romstage becomes an RW stage.
The mrc.bin however is only added to the RO COREBOOT fmap region as it
requires to be run at a specific offset. This means that coreboot will
have to jump from a RW region to the RO region for that binary and
back to that RW region after that binary is done initializing the
memory.
Change-Id: I900233cadb3c76da329fb98f93917570e633365f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30384
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds a workaround for Samsung C-die 2G/4G memory chips.
For unknown reasons, some boards with Samsung LP3 memory chips
could not pass early CS/CMD training. MRC has to change the
granularity from 16 ticks to 8 ticks, which implies bad margin
with this memory chip. Another way is to enhance the drive
strength for CS. This patch is to enhance the drive strength for CS
and CMD. Enhancing the drive strength for CMD could gain margin abaout
3 more ticks. Root cause needs to be further investigated with memory
vendor.
BUG=b:131177542
BRANCH=None
TEST=USE=fw_debug emerge-atlas chromeos-mrc coreboot chromeos-bootimage
& check the MRC log to ensure correct Rcomp values are passed to
MRC. Tested with board ID #8 and #11.
Change-Id: I9ea3ceda8dc8bf781063d3c16c7c2d9b44e5ddd6
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
Call the raminit from a common location instead of from the mainboard
specific code.
Change-Id: I65d522237a0bb7b2c032536ede10e2cf93c134d8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32760
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To improve the bootflow, the scope of the pei_data needs to be
extended.
Change-Id: Ic6d91692a7bf9218b81da5bb36b5b26dabac454e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This also links the gpio configuration instead of including it as a
header.
Change-Id: I9309d2b842495f6cff33fdab18aa139a82c1959c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The gpio table is only used by depthcharge, and depthcharge rarely
has a need for the "recovery" gpio. On a few boards it does use the
gpio as a signal for confirming physical presence, so on that boards
we'll advertise the board as "presence".
All these strings probably should have been #defines to help avoid
typos (e.g., the "ec_in_rw" in stout seems questionable since everybody
else uses "EC in RW").
Cq-Depend: chromium:1580454
BUG=b:129471321
BRANCH=None
TEST=Local compile and flash (with corresponding changes to depthcharge)
to 2 systems, one with a "presence" gpio and another without. Confirmed
that both systems could enter dev mode.
Change-Id: Id6d62d9e48d3e6646cbc1277ea53f0ca95dd849e
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
A12 is not current set for ISH_GP6 so the ISH_LID_CL#_TAB
signal is not making it to the ISH properly. Enable the second native
function instead of the first.
BRANCH=none
BUG=b:131785573
TEST=gpioget on ISH now shows the correct gpio level
Change-Id: Ib3a654ae659037263aa9aa29d45b42ca67b7955b
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32738
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We keep the support, though. Just now that `libgfxinit` is fixed, we
don't need the distinction anymore. Causally, we also don't need
CPU_INTEL_MODEL_306AX any more.
TEST=Played tint on kontron/ktqm77. Score 606
Change-Id: Id1e33c77f44a66baacba375cbb2aeb71effb7b76
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Leakage power is observed from TOUCH_SCREEN_PD# (GPP_E7 which is connected
to RESET pin of Wacom controller) during S5.
To avoid leakage power, GPP_E7 needs to be turned off before S5 entry.
BUG=b:129899315
TEST=Measure leakage power in S5 from both Arcada and Sarien
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ie4229477b7149c0a75f4a8c6c7c453a37cc1c78c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Add vbt files for nami variants and select Kconfig option
to utilize them. The default vbt is automatically added
by the Kconfig selection and so does not need to be
specified in the makefile with the others.
Test: boot vayne and akali nami variants, verify
display functional and correct vbt loaded.
Change-Id: Iaf49bdee7ae82a0a61192327351267f098eb5ab1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Set tcc offset value to 1 degree celsius for Arcada system.
BRANCH=None
BUG=b:122636962
TEST=Built and tested on Arcada system
Signed-off-by: Bonnie Lin <bonnie_ty_lin@wistron.corp-partner.google.com>
Change-Id: I3ca4be2f7b92e29fb133ecc32023526b177d2ac2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Correct Micron MT40A512M16TB-062E:J SPD CRC to 0x5330 to fix post hang
in AGESA TestPoint:05 TpProcMemSPDChecking.
BUG=b:127394249
BRANCH=master
TEST=emerge-grunt coreboot chromeos-bootimage
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Change-Id: I8fa49e6e938b3195945b3199438cc53f3e9c92e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Use CondRefOf to replace config optios for PTS/WAK acpi method dynamic
loading. Then we can move EC PTS and WAK method to be under mainboard.
BUG=N/A
TEST=Build sarien source code, check build/dsdt.dsl have EC.PTS method
included, build whlrvp soure, check build/dsdt.dsl don't have EC.PTS
method. Both able to build pass.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I9f4bd7240832caf070e65039e4ba2d8656371da8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32371
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A subsequent patch will move the AcpiMmio support into amd/common.
Take this opportunity to rename the blocks in the 0xfed8xxxx region
with more consistency.
Change-Id: I9a69a6ecfc10f78b4860df05a77a061d2fc8be7d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Fill SMBIOS type 9 fields for both sarien and arcada platform.
BUG=b:129485789
TEST=Boot up into OS and check with dmidecode -t 9 to we do have entry.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I47a697131b7aeeb64e0c4b4c0556842f1cb1b02e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
`pei_data` was a struct with blob parameters from pre-FSP times.
Somehow, it sneaked into upstream FSP1.1 support (probably because
early board ports were written for a different blob). When added
upstream, its usage was already perverted. It was declared at SoC
level but mostly used to pass mainboard data from mainboard code
to itself and FSP data from FSP code to itself. Now that no board/
SoC code uses it anymore, we can finally drop it.
Change-Id: Ib0bc402703188539cf2254bdc395cca9dd32d863
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The SoC specific `struct pei_data` was filled with values that were
later only consumed by the mainboard code again. Avoid jumping through
this hoop and fill FSP UPDs directly.
Change-Id: I040f4a55b4f4bad3f6072920e5e2eceded4cb9bb
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The SoC specific `struct pei_data` was filled with values that were
later only consumed by the mainboard code again. Avoid jumping through
this hoop and fill FSP UPDs directly.
The provided solution locates the SPD data in CBFS again to fill SMBIOS
tables. This is not perfect. OTOH, this code isn't mainboard specific
and doesn't belong here anyway.
Change-Id: Ib6103d5b9550846fe17c926631a013ff80b9598f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
`chip.h` is usually used as devicetree interface.
Change-Id: Ied30927d68927b86758a84ccf3f5fbd8cce632f1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32592
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Turn off camera power when s0ix for power saving.
BUG=b:129177593
TEST= measure camera power comsumption is 0mV under s0ix
Change-Id: I5a9b7ec1e95cc9931d8d5f2dc1254805c9d0ffed
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
A13 and A15 need to set low before H12 reset. Change
the program sequence for fit HW requirement.
BUG=b:131876963
TEST=boot up and check SD card functional
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I2f1752070f24833aaaab75dea8493caf2ed7f157
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This patch fixes up all code that would throw a -Wtype-limits warning.
This sometimes involves eliminating unnecessary checks, adding a few odd
but harmless casts or just pragma'ing out the warning for a whole file
-- I tried to find the path of least resistance. I think the overall
benefit of the warning outweighs the occasional weirdness.
Change-Id: Iacd37eb1fad388d9db7267ceccb03e6dcf1ad0d2
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32537
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Run CPU at the highest freqency (1989MHz) to speed up the boot time.
BUG=b:80501386
BRANCH=none
Test=Boots correctly on Kukui
Change-Id: I703ffcb99367f87e6792a72485f5634e0505e5ac
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32466
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updated GPP_A8 to be a GPI and SCI source, to support both wake and
notifications.
BUG=b:128941098
BRANCH=none
TEST=Compiles, simulated pen eject with PCH_INT_L signal. Both evtest
and waking from s0ix confirm this works. The output of /proc/interrupts
confirms the correct interrupt is triggered.
Change-Id: I080fb3cbfb3e2f55209ca31824b00ca820d70f78
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
IASL reports warning 'Control Method should be made Serialized'.
Change _CRS method to Serialized.
BUG=N/A
TEST=Build Google Banon and Google Cyan
Change-Id: Iffa097a2100cfa91efa3b617311500b83f839bce
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
CB acts as I/O handler for QCLib (e.g. DDR training data)
This interface allows bi-directional data flow between
CB and QCLib
Tested and working interfaces:
DDR Training data
QCLib serial console output
DDR Information (base & size)
limits cfg data
TEST=build & run
Change-Id: I073186674a1a593547d1ee1d15c7cd4fd8ad5bc1
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The current Braswell FSP 1.1 header in vendorcode/intel, for
which there is no publicly available FSP binary, contains silicon
init UPDs which are not found in the publicly available header/binary
in the FSP Github repo. This prevents new boards from being added
which use the public Braswell FSP header/binary.
To resolve this, move the UPDs not found in the public header from
the soc's chip.c to ramstage.c for the boards which use them. Add
a Kconfig option to use the current non-public FSP header and
select it for boards which need it (google/cyan variants); set the
public FSP option as the default. Use the Kconfig option to set
FSP_HEADER_PATH to ensure the correct header is used.
Test: build google/cyan and intel/strago using non-public and
public FSP header/binaries respectively.
Change-Id: I43cf18b98c844175a87b61fdbe4b0b24484e5702
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Enable acoustic noise mitgation for arcada platform,
the slow slew rates for Ia and Gt are fast time dived by 8.
BUG=b:131144464
TEST=waveform test and hardware validation result pass.
Signed-off-by: nathan chen <nathan_chen@wistron.corp-partner.google.com>
Change-Id: I395b2fc527705ab207325cfd7147e6af5f300fce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Main objective for this change is to export the bluetooth reset
gpio to the kernel for use in an rf-kill operation.
To do so, we enable USB acpi and define all of the USB2 devices,
which includes bluetooth's reset gpio information.
BUG=b:122540489
BRANCH=None
TEST=emerge-atlas coreboot chromeos-bootimage
$cat sys/firmware/acpi/tables/SSDT > /tmp/ssdt.dat &
retrieve ssdt.dat from DUT &
$iasl -d ./ssdt.dat & check the HS03 node is with "reset-gpio"
under _DSD object
Change-Id: I411ef707782655361bd1b8ac2b914b8ae64defeb
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Caveh Jalali <caveh@google.com>
This patch adds code to initialize two USB DWC3.0 controllers
and its associated QUSB V2 10nm PHYs to the SDM845 SOC, and uses them to
initialize USB3.0 on the cheza mainboard.
Synopsis controller initialization and configuration sequences taken from
USB 3.0 HPG chapter 2.2 and refer PHY HPG chapter 10.2 for QUSB phy
programming.
Includes Super speed mode support.
TEST=USB keypad and mass-storage device enumeration tested with this patch
Change-Id: I475a7757239acb8ef22a4d61afd59b304a7f0acc
Signed-off-by: Chandana Kishori Chiluveru <cchiluve@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
