This patch adds a new --loglevel option to the CBMEM utility which can
be used either numerically (e.g. `cbmem -1 --loglevel 6`) or by name
(e.g. `cbmem -c --loglevel INFO`) to restrict the lines that will be
printed from the CBMEM console log to a maximum loglevel. By default,
using this option means that lines without a loglevel (which usually
happens when payloads or other non-coreboot components add their own
logs to the CBMEM console) will not be printed. Prefixing a `+`
character to the option value (e.g. `--loglevel +6` or
`--loglevel +INFO`) can be used to change that behavior.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I8458027083246df5637dffd3ebfeb4d0a78deadf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Config USE_PM_ACPI_TIMER to y for primus4es only as
commit 1ce0f3aab7 (mb/google/brya: Fix S0i3 regression)
breaks suspend stress test on ES CPU SKU.
BUG=b:211377699
TEST=USE="project_primus emerge-brya coreboot" and verified
the suspend stress test works on primus4es.
Change-Id: I8d19c10e2029e233542a8ceec272f8ede2b4bfac
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Few of the Alder Lake-N Device IDs according to EDS, are named as ADL_M
IDs in the current code. Hence rename those device IDs as ADL_M_N and
use them for Alder Lake-N platform.
Document Number: 619501, 645548
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I6042017c6189cbc3ca9dce0e50acfb68ea4003f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Refactor existing acp code into acp_gen1 variant as preparation for gen2
variant in sabrina.
Change-Id: Id9248584237196b5404b79d3a8552cb90fe4491e
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Check if FSP binary and coreboot FSP structures (fspmupd.h) match
sufficiently.
A change in minor number denotes less critical changes or additions
to the FSP API that still allow for the boot process to proceed.
A change of the AMD image revision major number will halt boot.
The Fspmupd.h header now defines IMAGE_REVISION_ macros for AMD
Picasso, Cezanne and Sabrina APUs.
BUG=b:184650244
TEST=build, boot and check fsp image revision info. Example:
FSP major = 1
FSP minor = 0
FSP revision = 5
FSP build = 0
Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Change-Id: I0fbf9413b0cf3e6093ee9c61ff692ff78ebefebc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
It's available in %r3 in bootblock and needs to be passed to payload in
%r27. We use one of two hypervisor's special registers as a buffer,
which aren't used for anything by the code.
Change-Id: I0911f4b534c6f8cacfa057a5bad7576fec711637
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
"hb-mode" is a -machine flag for QEMU. "hb" stands for Hostboot, which
is OpenPower firmware created by IBM.
QEMU for PPC64 can run initial program in two different modes:
* hb-mode=off with load address 0x00000000
* hb-mode=on with load address 0x08000000
Real hardware always loads firmware at 0x08000000 and coreboot shouldn't
require a special build to be run on QEMU.
Memory layout is updated to reflect change of load address.
Change-Id: I1bdc97a095bd46fccc862985b3bd24f4fa5bc054
Signed-off-by: Yaroslav Kurlaev <yaroslav.kurlaev@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This change adds mem_parts_uesd.txt that contains the new memory parts
used (H54G46CYRBX267,H54G56CYRBX247) by primus and Makefile.inc
generated by gen_part_id using mem_parts_used.txt.
BUG=b:218415732
Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I0d236c51f0c996a22954046876f3494ba9e62693
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Currently apu/amdfw_a-position and apu/amdfw_b-position currently depend on CEZANNE_FW_A_POSITION and CEZANNE_FW_B_POSITION. This causes error messages from awk as these variables are sourced from fmap_config.h and these variables are expanded before fmap_config.h is built. However these variables should not be set to CEZANNE_FW_*_POSITION. These files end up in the FW_MAIN_* fmap regions. These regions are placed at the proper locations through the chromeos.fmd file. The apu/amdfw_*-position variables are the positions within these regions where the files end up. These variables should be set to 0x40 to coincide with the beginning of the FW_MAIN_* regions, accounting for the size of struct cbfs_file + filename + metadata, aligned to 64 bytes. Currently they end up in the correct locations only because fmap_config.h does not exist when the apu/amdfw_*-position variables are expanded.
This change explicity sets the value of these variables to 0x40, removing the errors from awk and ensuring that these files end up in the correct location in the resulting image. These changes are also applied to the Picasso and Sabrina makefiles as well.
BUG=b:198322933
TEST=Verified that the apu/amdfw_* files end up in the correct locations as reported by cbfstool during the build, did timeless builds and confirmed that coreboot.rom images were identical, tested AP firmware on guybrush and zork devices
Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: If1c2b61c5be0bcab52e19349dacbcc391e8aa909
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Introduce and use functions to translate eSPI IO/MMIO decode range IDs
into the corresponding register bits and the IO/MMIO range and size
register IDs into register offsets. This is a preparation to support the
additional eSPI decode ranges on Sabrina where not all enable bits and
base/size registers for one type of decode ranges are consecutive.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id91fe32447a06b049e33dfdacc8edfa2ebb2df39
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This aligns the register names more with the PPR.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4e7dc8dfc0fa5e86b9d4425f2496be86e039b686
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Nissa is using the FM101, which has the following power sequencing
requirements:
Power on: assert WWAN_EN, delay 20 ms, deassert WWAN_RST_L
Power off: assert WWAN_RST_L, delay 20 ms, deassert WWAN_EN
Add a power resource to the USB device, and use wwan_power.asl to
handle the power off sequence.
BUG=b:217092522
TEST=abuild -a -x -c max -p none -t google/brya -b nivviks
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: Ibe1b863a550c6af1ac3eb98f2aaa3db15b149ada
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Nissa is using the FM101 which is USB only. To allow us to reuse the
existing wwan_power.asl for power sequencing, move the PCIe-specific
part behind a new Kconfig HAVE_PCIE_WWAN.
BUG=b:217092522
TEST=Build brya0 and check that generated dsdt.asl doesn't change.
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: Icb6db91ce00deb2b30379f5ff7a974d1feb62ea8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
If the LTE USB DB is not connected, disable the LTE-related GPIOs.
BUG=b:197479026
TEST=abuild -a -x -c max -p none -t google/brya -b nivviks
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: I86251d8ad58d82ff2112ac5f2dfafdabbff4c76f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Add an initial overridetree for nivviks based on the pre-proto schematic
and build matrix.
BUG=b:197479026
TEST=abuild -a -x -c max -p none -t google/brya -b nivviks
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: Id3ecd184415a20a3a52da8bb5e60fe2ce0495b44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
There may be occasions where an I2C device was initialized during
"early initialization," but when used again in ENV_PAYLOAD_LOADER
before resource allocation happens, it would currently return that it
has not been assigned a BAR. However, because of the early BAR
assigned to it, it should still be valid to use that until proper
resources have been assigned, therefore return any BAR that may have
been assigned to the device during early initialization.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I8ab599199592a72ae96cd9f95accfaa0d84e66b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The `chip` argument passed around to many functions in this driver is
actualy unused, so remove it where it is unused.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ib8d32fdf340c8ef49fefd11da433e3b6ee561f29
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
The current SPI NOR speed mainpll_d7_d2 (78MHz) is too fast for MT8186's
HW design, which is capable of up to 52MHz. Therefore, lower the speed
to univpll_d3_d8 (52MHz).
BUG=b:218775654
TEST=emerge-corsola coreboot
TEST=Boot time didn't increase significantly
BRAHCH=none
Change-Id: I5a03e41d4ce47d45b97a805b9b98877ef0dac7b7
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
BSS is loaded as part of the bootblock, it is zeroed in the file so it
doesn't have to be cleared explicitly by the code.
Code for clearing is left as a comment along with a warning about alignment
requirements.
Vector operations are sometimes generated for code such as
'uint8_t x[32] = {0}', this results in an exception when vector registers
(VR) are not enabled. VSR (vector-scalar register) operations are also
enabled, there is no reason not to.
Change-Id: I878ef61619eb4a191805c8911d001312a0d717a0
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Fix regression after commit 9ec7227c9b
cpu/x86/lapic: Move LAPIC configuration to MP init
The call to disable_lapic() got removed and with asus/p2b
SeaBIOS payload was unable to load kernel.
The combination of entering SeaBIOS payload with an
enabled lapic but not having programmed LAPIC_LVT0
for DELIVERY_MODE_EXTINT apparently disconnects i8259
PIC interrupt delivery pin.
Change-Id: If51e5d65153a02ac7af191e7897c04bd4e298006
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
To prevent to modify original value of wdt_mode, we use setbits32 to
update required bits.
BUG=b:218420108
TEST=build pass
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I743c1af3583c18ec8500fc1eb89f31cdbce5317c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61729
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SMMSTORE region needs to be 64K aligned or error will be thrown.
Change-Id: I5d4f71f80c3219ac2c7000e1fa95fd04100d9cfe
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Instead of having runtime failures that are hard to debug because SMM
debugging is disabled by default assert some properties of fmap at
buildtime.
Change-Id: I5b5b511142d93d5799565a8936e9a087117044b3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Guard macro via CONFIG_INTEL_GMA_ADD_VBT, rather than guarding
each of the calls to it (most of which are currently unguarded).
Test: build google/coral w/ and w/o CONFIG_INTEL_GMA_ADD_VBT selected,
verify VBTs added (or not) to CBFS based on Kconfig selection.
Change-Id: Ic25554cb2c61b81bdb4b0987094c3558e0bbcbd8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Several commits were made to the Chromium coral branch
(firmware-coral-10068.B) which were not committed upstream first.
Pull them in here:
486ce56 mainboard/google/coral: Override VBT selection for babymako
c1d7720 Babymako: add touchpad i2c speed config
911d547 mainboard/google/coral: Override VBT selection for babytiger
730a5af Babytiger: add touchpad i2c speed config
724711e rabbid: add the touchpad i2c speed config
80c5d16 mainboard/google/coral: Override VBT selection for babymega
e8931a4 Babymega: add touchpad i2c speed config
These add support for additional coral sub-variants. The I2C speed config
changes were adapted to account for upstream changes not present in the
coral Chromium branch.
Change-Id: Idf2a53a351138aff310385f4026197d74ab6848b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Release firmware on Nasher/Nasher360 are built as coral
sub-variants; remove the old/unused code
Change-Id: Ie8d10a31e663230b7deabf92e1c06cd991bbdccb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Updating from commit id 73193689c:
2021-12-06 16:47:33 +0100 - (Merge changes I7c9f8490,Ia92c6d19 into integration)
to commit id e0a6a512b:
2022-02-03 22:59:34 +0100 - (Merge changes from topic "msm8916" into integration)
This brings in 324 new commits.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I44bca36f4b05e08fe7d7de0966131be84c0a7d2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
EMPTY_WRAP() might be useful for tests other than CBFS's ones. Move it
to the main tests header file to make it easily accessible.
Change-Id: Ic06c55912488681daf6d2c48cb0c879fa97ba4be
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Updating from commit id 98db386:
2021-08-03 11:57:30 -0700 - (herobrine: Add gsi_fw_blobs and Release Notes)
to commit id 9ab0f0b:
2022-01-18 19:01:30 +0530 - (sc7280: Update AOP firmware to version 379)
This brings in 13 new commits:
9ab0f0b sc7280: Update AOP firmware to version 379
826cb9c sc7180/boot : Update qclib blobs binaries and release notes
ddf67d1 sc7280/ boot and shrm blobs updated
8592f11 sc7280: Update AOP firmware to version 364
aef8a0a sc7280/ boot and shrm blobs updated
c72bc4e sc7280/cpucp: Update cpucp blobs binaries and release notes version from 054 to 060
33e57fe sc7280/boot,/shrm : Update qclib blobs binaries and release notes version 13
511851b sc7180/boot : Update qclib blobs binaries and release notes version 30
f91d0ef herobrine: qc_sec blob update
8c50f78 sc7180/boot : Update qclib blobs binaries and release notes
8523ef4 sc7180/qtiseclib: Update version from 26 to 44
5b77a37 sc7280/qtiseclib: Update version from 33 to 44
4815cc2 sc7280: Update AOP firmware to version 360
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I510141916900507fd29a0e9315a3f8d954bc0cab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Create the moli variant of the brask reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:214439135
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_MOLI
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I3f3bfd3db12cba8b73b351e7c700b6a58797c906
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
When booting ADL RVP, coreboot is unable to load VBT binary as
makefile will rename VBT binary to "vbt.bin" when building
coreboot.rom.
The reason for having this function is that chromeOS has emerge
tool to streamline the VBT stitching process to support multiple
VBTs for different RVP boards; while we only need 1 vbt for generic
non-chromeOS usage. Hence add a chomeos kconfig to guard this.
TEST=Able to boot ADL RVP DDR5 with DP display.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I5f6f9554b75f4d62198aac9938e65c71c3e7cee9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add Alder Lake and Tiger Lake specific Crash Log and PMC SRAM device
IDs.
Document Number: 619501, 645548
Change-Id: I64b58b8c345bd54774c4dab7b65258714cd8dc9e
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Add wifi sar for magneto.
Due to fw-config cannot distinguish between magolor and magneto.
Using sku_id to decide to load magneto custom wifi sar.
BUG=b:208261420
TEST= emerge-dedede coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I77f141372ba8e7b8f5849b00e115ad8bb1e7ca00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
ALC5682-VD/ALC5682I-VS load different kernel driver by different _HID
name. Update hid name depending on the AUDIO_CODEC_SOURCE field of
fw_config. Define FW_CONFIG bits 41 - 43 (SSFC bits 9 - 11)
for codec selection.
ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"
BUG=b:204517112
BRANCH=volteer
TEST=ALC5682-VD/ALC5682I-VS audio codec can work
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I5c1c9819af1e0bc2278dadeffb6b19c3f9068f30
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
ALC5682-VD/ALC5682I-VS load different kernel driver by different _HID
name. Update hid name depending on the AUDIO_CODEC_SOURCE field of
fw_config. Define FW_CONFIG bits 41 - 43 (SSFC bits 9 - 11)
for codec selection.
ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"
BUG=b:218245715
BRANCH=volteer
TEST=ALC5682-VD/ALC5682I-VS audio codec can work
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I081dcf5451c82c03592f954ee25267b31ad81753
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
use DEV_PTR to get codec HID for simplify the variant.c code
ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"
BUG=b:204523176
BRANCH=volteer
TEST=ALC5682-VD/ALC5682I-VS audio codec can work
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Idf5b3661e74a189390d25381e03448c28a966f38
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61671
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Mainboards using Sabrina SoC will be using LP5 memory technology.
Generate the initial set of SPDs for the existing LP5 memory parts.
BUG=b:211510456
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ibb43f26b36460290341c5ffcad1ef5a2ff1647c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
CBFS MCache size was assigned a value of the coreboot tables entry size
instead of the MCache size.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I8a8c3a10c6032121b4c5246d53d2643742968c09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Julius Werner