Commit Graph

5933 Commits

Author SHA1 Message Date
Patrick Georgi bbc523146c libpayload: Implement usb_exit
So far it was empty and never published. It now exists and shuts down
all controllers (esp. EHCI which resets the port routers).

Change-Id: I81e355e8a05778d6397675417b085a094a6f48ee
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/397
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-11-04 22:14:29 +01:00
Patrick Georgi 01178bb03b libpayload: Tell EHCI to re-enable USB1 controllers
EHCI can take over all ports (and then reroute devices to
companion controllers if needs be). We do that, and then never
reset it.

Consequence:
Systems with only USB1 HC drivers (OHCI/UHCI) never see any devices.

Change-Id: If1d91e9142a6618289b0b3f6b56587ec857158e3
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/396
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2011-11-04 22:13:39 +01:00
Patrick Georgi 2e768e7f17 libpayload: Drop usb_fatal()
We have fatal(), which is just as good.

Coccinelle script:
  @@
  expression E;
  @@
  -usb_fatal(E)
  +fatal(E)

Change-Id: Iabecbcc7d068cc0f82687bf51d89c2626642cd86
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/395
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2011-11-04 22:11:05 +01:00
Patrick Georgi 3cd0ae2c7b Revert "add support for 1106:3188 (host controller of the old version of k8t800)" due to dependency issues.
This reverts commit 68c554550f59bd96caace96260ae2e30ed55ceb4

Change-Id: I353bd36b008f489a972c7c656d7ad07416f01387
Reviewed-on: http://review.coreboot.org/398
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-11-04 16:44:53 +01:00
Florian Zumbiehl e037f9f174 add support for writing to SMBus with vt8237
Change-Id: I70fe072f8f3447d0be7b7ac64508a954fe47091d
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/372
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2011-11-03 21:39:03 +01:00
Florian Zumbiehl 8c4cf18fc4 add support for 1106:3188 (host controller of the old version of k8t800)
Change-Id: I10135b37a6cef460be9bfbfd34746140310859a6
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/381
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2011-11-03 21:32:40 +01:00
Mathias Krause c4716b4ebf libpayload: Reduce verbosity in USB stack
The USB stack is pretty noisy. Reduce the output to a sane level.

Change-Id: I250949e5cf74a8c6d43822b2e7487143b2ae1c65
Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
Reviewed-on: http://review.coreboot.org/393
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-11-03 19:14:26 +01:00
Mathias Krause 0805201143 libpayload: Put coreboot version into lib_sysinfo
Change-Id: I22319efe90e475c66b9556f734a7a5e54f7c59bc
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/394
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-11-03 19:02:55 +01:00
Florian Zumbiehl d35906173d fix superiotool for NCT6776F
The current code exits config mode of the NCT6776F immediately after
detection, so the register dump shows all 0xffs. This patch adds code to
re-enter config mode for the register dump so that the register contents
can be read.

Change-Id: I4ad0c108b6411a665e31f55dea4b91ca77d1a5f7
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/391
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-11-03 13:57:46 +01:00
Florian Zumbiehl f8ed90332c simplify IDE cable detection for Asus M2V
Change-Id: If8e4dcf405e24b744ac34f581c5609fcce96fd07
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/371
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-11-02 16:50:04 +01:00
Stefan Reinauer 1200ec5a53 buildgcc: Update coreboot reference toolchain to gcc 4.6.2
In addition:
- drop some unneeded patches
- make the scripting support depend on SKIPPYTHON not SKIPGDB
  so it is possible to build GDB with and without scripting support
- rename the repository checkout version of GCC trunk, not X+1
  so we don't have to change it on every version upgrade.

Change-Id: I1b7d5b8921187c1c1d39b04f20bb715ddba72fe8
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/367
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-11-02 10:51:02 +01:00
Florian Zumbiehl 2d4fecec51 don't scan beyond end of CBFS
Change-Id: I66e535f77e513dbfa5fc906ecf288193af78ae62
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/369
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-11-02 10:49:24 +01:00
Stefan Reinauer 2c3cd125be Add Python scripting to GDB.
This allows GDB to run Python scripts. The Python build is dependant on the GDB
build flag.

Changes by Stefan Reinauer:
- update to latest buildgcc script
- disable GDB per default
- disable python scripting, if GDB is not enabled
- bump version number to 1.06

Change-Id: Ie7fc8706deec41c804870415d3c79d225c98cd31
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/153
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2011-11-01 23:23:03 +01:00
Stefan Reinauer e11835e299 libpayload: remove trailing whitespace and run dos2unix
Change-Id: Iffed3602456f5306711c65f06c873c58d4086e11
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/363
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-11-01 19:08:23 +01:00
Patrick Georgi dd69063289 libpayload: Fix OHCI some more
OHCI works when USB_DEBUG is disabled, but not, when disabled.
This is because the controller requires some more time after a
schedule has finished.

Also improve compliance with the OHCI spec.

Change-Id: I4685cc485ff9c52b489fbaa352ab889671cff876
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/365
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-11-01 19:07:47 +01:00
Stefan Reinauer 5ff7c13e85 remove trailing whitespace
Change-Id: Ib91889a374515d36a2b12b53aeb12b6ea6e22732
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/364
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-11-01 19:07:45 +01:00
Patrick Georgi 784544b934 Remove XIP_ROM_BASE
The base is now calculated automatically, and all mentions of that
config option were typical anyway (4GB - XIP_ROM_SIZE).

Change-Id: Icdf908dc043719f3810f7b5b85ad9938f362ea40
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/366
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-11-01 19:06:23 +01:00
Stefan Reinauer 36c04e8a5c Run dos2unix on bayou and remove white space at the end of lines.
Change-Id: If13d9a49ece2699885ae3e998173d3d44507b302
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/362
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2011-10-31 21:29:31 +01:00
Patrick Georgi 1861ff739c buildgcc: Fix colors for dash
The previous fix broke buildgcc colors on MacOS X.
This uses an encoding that should be more universal.

Change-Id: I31ac6090ffb7c04784cf6566823652f229aebbb5
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/361
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-31 15:42:23 +01:00
Kyösti Mälkki 0a0d5e8b86 Add support for E7505 northbridge.
Adapted from northbridge/intel/e7501 with only minor changes.
This commit provides minimal patch from e7501 and I prefer any
cosmetic clean-up to be done after initial merge.

Due the incomplete register specifications, it is safer to have
e7505 as a separate directory in case I improve it to support
wider range of memory configurations. I have no e7501 to test with.

Change-Id: Iba3bf9d69ff5e9d9ef3a6ebf8259f048c55d637d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/295
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-31 15:34:04 +01:00
Sven Schnelle 20fc631ad2 Fix usb debug dongle support
- move enable_usbdebug() declaration to usbdebug.h
- reinitialize debug driver in ramstage, as copying the data
  structure from romstage doesn't work right now. This way of copying
  data from romstage to ramstage is really board/cpu specific, and is
  likely to break often. So don't do it.

Change-Id: I394678ded6679c1803e29eb691b926182bdcab68
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/355
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-31 04:06:10 +01:00
Patrick Georgi 28f6a43755 crossgcc: Fix colors with dash
Ubuntu (and probably other distros) have dash as /bin/sh, which
doesn't display colors by itself. If /usr/bin/printf is found, it's
used instead of the internal printf to re-enable colors.

Change-Id: I3e6d413cd0c8a46ef91821d8c07e88166de58af4
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/352
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-30 21:58:42 +01:00
Rudolf Marek 9438da370f Fix slow CAR execution introduced by 7c7d87182feb78cb2bc02fb3558bef56a41682c9
It is meant to be a address and not a dereference. Otherwise MTRR
is filled with code and not with the address.

This is what I hate at most on the AT&T syntax. Instead of taking
the address, it was a dereference. Not greatly visible, except
I wondered why opcode is not 0xb4 but 0xa1 and it took another
half an our to see it.

Change-Id: I6b339656024de8f6e6b3cde63b16b7ff5562d055
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/358
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2011-10-30 21:28:11 +01:00
Stefan Reinauer af3dce981d Fix gcc 4.6.1 breakage of southbridge/amd/sr5650/pcie.c.
Change-Id: I3ccb3860207e1b3ccac4313f7b537c434af5166f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/360
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2011-10-30 20:49:15 +01:00
Sven Schnelle 54a5aedec6 inteltool: Add Intel i63xx I/O Controller Hub
Change-Id: Iaea7e4d1b206d43661ecb61d2ae517723fb8d008
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/356
Tested-by: build bot (Jenkins)
2011-10-30 13:37:16 +01:00
Sven Schnelle 4c2bfb6256 remove usbdebug.h include from mainboard/romstage code
No romstage is supposed to use usbdebug functions/defines
directly, so remove all those includes. The usb code is now
called and setup from console code.

Change-Id: I9b1120d96f5993303d6b302accc86e14a91f7a9f
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/354
Tested-by: build bot (Jenkins)
2011-10-30 12:37:05 +01:00
Stefan Reinauer 9491b4d5f5 Update coreboot cross toolchain to gcc 4.6.1
- Tested on Mac OS X 10.7.1
- Tested on Ubuntu 10.04 LTS (Lucid Lynx)
- Tested on Ubuntu 11.10 (Oneiric Ocelot)

Please test on Windows and other Linux distributions

Change-Id: I132c01293fc0cff0cfb84556a93c0b8de8e57230
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/250
Tested-by: build bot (Jenkins)
Reviewed-by: Sven Schnelle <svens@stackframe.org>
2011-10-30 12:01:08 +01:00
Patrick Georgi 952b421c27 asus/m5a88-v: Fix build
We added some new flag for certain AMD boards after support for
this board was submitted. Also integrate the mptable refactorings
that happened in the meantime.

Change-Id: I50cf50f343a740832fd1a14a2a1ef5b903315675
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/353
Tested-by: build bot (Jenkins)
Reviewed-by: Sven Schnelle <svens@stackframe.org>
2011-10-30 11:42:51 +01:00
Patrick Georgi 3954b0ad25 Fix coreboot updates
The rule to prepare a new coreboot.pre1 was ignored in the
"update image" scenario because a perfectly fine file exists.
Mark it phony to fix it.

Change-Id: Ie7f8b36b71015a593958cd6e19602bad6b854320
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/351
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-29 06:02:04 +02:00
Christoph Grenz b9da3cd891 w83627hf: add method to retrieve wake event source register to ASL include
Add a method WAKS to devtree.asl which returns the wake-up source register
to simplify retrieving the wake source e.g. in \_WAK.

Change-Id: Ia258f8fc9ff79b18391c55464da73863889e2255
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/297
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-28 22:30:06 +02:00
QingPei Wang cc66d97f50 Add ASUS M5A88-V mainboard support
it's a AMD 880+800 mainboard. I port the code
based on the AMD reference code.
update: 1.use CIMX instead of pmio
          2.fix some whitespace
          3.fix subsystemid of devicetree.cb

Change-Id: I9725ccdbb25365c4007621318efee80b131fec29
Signed-off-by: QingPei Wang <wangqingpei@gmail.com>
Reviewed-on: http://review.coreboot.org/205
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-28 22:26:07 +02:00
Patrick Georgi 914377efd6 Get rid of the old romstage-as-bootblock ROM layout
This change removes CONFIG_TINY_BOOTBLOCK, CONFIG_BIG_BOOTBLOCK, and
all their uses, assuming TINY_BOOTBLOCK=y, BIG_BOOTBLOCK=n.

This might break a couple of boards on runtime, but so far, fixes were
quite simple.
There's a flag day: Code that relies on CONFIG_TINY_BOOTBLOCK must be
adapted.

Change-Id: I1e17a4a1b9c9adb8b43ca4db8aed5a6d44d645f5
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/320
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-28 22:17:36 +02:00
Patrick Georgi 1da104647d Get rid of AUTO_XIP_ROM_BASE
That value is now generated from a code address and CONFIG_XIP_ROM_SIZE.
This works as MTRRs are fully specified by their size and any address
within the range.

Change-Id: Id35d34eaf3be37f59cd2a968e3327d333ba71a34
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/348
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-28 22:17:10 +02:00
Patrick Georgi 0f8590f9ca sb600: Implement EHCI workaround
Linux implements it itself, but older Linuxes and other systems
might not. Without this, the host controller might not respond
to drivers.

Change-Id: I4ff0e3683c02e7aa00d188428847c64c4c5d589d
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/345
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-28 22:15:19 +02:00
Patrick Georgi 5ed8cc0d62 siemens/sitemp_g1p1: Add more devices to PIR and MP table
Linux 2.4 is happier that way

Change-Id: I016609ae1e004ec856e8223893352dcdd061b291
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/346
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-28 22:14:43 +02:00
Kyösti Mälkki 481814d1ab Clear improper use of CONFIG_CACHE_AS_RAM
Choice between printk/print_ is related to CAR, but really
depends whether we compiled with GCC or ROMCC.

Change-Id: I9fe831a215736462e8b3f4b96ffe231133ecf79b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/347
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-28 22:13:50 +02:00
Sven Schnelle d3edd9abe9 T60: remove redundant usbdebug_init call()
called from console code, no need to call it here.

Change-Id: I4c34f89c82cc2478db8de4e98584e69d7ab0ca82
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/350
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-28 22:07:44 +02:00
Stefan Reinauer b15975bf5a copy e7501 component to e7505
Change-Id: Ie69a6b6a040a8b0e7693083b3a2d13c327a165b3
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/310
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-28 22:01:03 +02:00
Patrick Georgi 94a458626a Prevent multiple inclusions of object files and rules
This removes 54 make warnings from the build

Change-Id: I94ac9875526febe2f95334c1c3971641c1d27f8f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/338
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-28 21:48:55 +02:00
Stefan Reinauer ea5c2b62ca Fix checksum calculation both in romstage and ramstage.
The earlier fix for CMOS checksums only fixed the function rtc_set_checksum,
which would fix the checksum, but then coreboot would no longer honor the
settings because it assumed the checksum is wrong after this.
This change fixes the remaining functions.

Change-Id: I3f52d074df29fc29ae1d940b3dcec3aa2cfc96a5
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/342
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-28 09:09:40 +02:00
Rudolf Marek 113c349720 Add support for AMD IMC controller.
This patch adds support to dump SIO like interface of AMD Embedded Controller
in the SB7xx and SB8xxx southbridges. Parts of the register interface are
documented in SBxxx RRG BDG.

Change-Id: Ib2ccaa3dfe33cfa8e7cba19d8ab0798286ad2f92
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/343
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2011-10-27 22:28:55 +02:00
Oskar Enoksson 9bfa1c8c68 Added smbus block read/write for amd8111
Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
Change-Id: I86c80a27fd13c9a2be4034fdfb63be4ab2fadbfc
Reviewed-on: http://review.coreboot.org/281
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-27 19:09:50 +02:00
Patrick Georgi 07b4215e11 Move linux 2.6.11 workaround to generic code
Linux 2.6.11 seems to require a certain order in CPUs listed in mptable,
so enforce it. This was only done on arima/hdama, but now is generic.
Unfortunately this is somewhat slow.

Change-Id: I85715ebae8a009cb816bc9ffd6372708f246bf66
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/280
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-27 19:09:29 +02:00
Sven Schnelle e572ef6136 X60/T60: enable AHCI mode
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Change-Id: I2166ae9ee9e7e0e431583249f015d130d15fac61
Reviewed-on: http://review.coreboot.org/341
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-27 18:27:24 +02:00
Sven Schnelle b2f173e168 i82801gx: Fix port status in AHCI mode
The code used PCI register 0x92 to enable sata ports,
which is wrong. The ICH7 documentation states:

"This register is only used in systems that do not
support AHCI. In AHCI enabled systems, bits[3:0] must
always be set (ICH7R only) / bits[2,0] must always be set
(Mobile only), and the status of the port is controlled
through AHCI memory space."

Writing 0x0f to ICH7-M doesn't seem to hurt, so lets write
0x0f for both variants. This patch makes sata_ahci work on
my Thinkpad T60 and X60s.

Change-Id: If3b3daec2e5fbaa446de00272ebde01cd8d52475
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/340
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-27 18:27:07 +02:00
Stefan Reinauer 5e4e2290b6 Add -Werror to xcompile's testcc
If -Werror is not specified, tests for certain compiler flags
will emit a warning, which makes the build break since we compile
with -Werror.

Change-Id: I7be56530ff9f94e5500bad226c83e47145a808d7
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/336
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-27 10:50:39 +02:00
Stefan Reinauer bbfc9c449f Fix libpayload speaker driver
The frequency for the PC speaker has to be specified as
1193180 / frequency according to http://wiki.osdev.org/PC_Speaker

Change-Id: Iaca9d45807e080efe834611e719b350680b5fb90
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/337
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-27 10:49:41 +02:00
Sven Schnelle 6eb8bef25e X60: enable Cx power saving modes
Change-Id: Ib03d9aa77050edde2538b80b32158cb3f0610be6
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/331
Tested-by: build bot (Jenkins)
2011-10-25 21:03:30 +02:00
Sven Schnelle f02c396f26 T60: add _CST table
Used by power management code to enable Cx powersaving modes.

Change-Id: I02c6b10762245bc48f21a341286236e203421de0
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/322
Tested-by: build bot (Jenkins)
2011-10-25 20:38:44 +02:00
Sven Schnelle d2bc117f79 T60: enable C4onC3 mode
It is safe to enable this setting on these Boards.

Change-Id: Iaa7377117743d18a95c496c25abf9fb4a1b20ad9
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/330
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-25 20:13:30 +02:00