Commit Graph

48531 Commits

Author SHA1 Message Date
Wisley Chen c23ff72cd7 spd/lp4x: Generate initial SPD for H54G68CYRBX248
Generate initial SPD for H54G68CYRBX248

BUG=b:239888704
BRANCH=firmware-brya-14505.B
TEST=util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x

Change-Id: Iae75391938446e9ee387b779ddcaa378a23ee52e
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-28 20:00:05 +00:00
Eric Lai 9473154497 mb/google/brya/var/ghost: Correct CNVi pins
GPP_F0 to GPP_F4 is for CNVi and should be NF1.
GPP_F5 is for CNVi CLK_REQ, and should be NF3 CRF_XTAL_CLKREQ.

BUG=b:240006200
BRANCH=firmware-brya-14505.B
TEST=CNVi wifi can get probed in kernel.

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ice3fde3a457f6f5c058c0a7d3ca2e63775bda96c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
2022-07-28 19:59:54 +00:00
Jeremy Soller 5219ee160e soc/intel/alderlake: Enable LPIT support
Add SLP_S0 residency register and enable LPIT support.

Change-Id: I45e1fc9df3e782cdaac810af3189c5797b1fe413
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-28 19:59:44 +00:00
Felix Singer dca8583f17 util/liveiso/common: Install devmem2 and pcimem
devmem2 and pcimem are useful tools which allow working (reading and
writing) with memory mapped IO.

Change-Id: Ifda547b44af3c8e11cd4171a1dfbce3713455303
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66171
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-28 18:28:24 +00:00
Jeremy Compostella cd6a2ad1b2 soc/intel/alderlake: Set Energy Perf Bias appropriate default value
The current "normal" EPB (six) setting resulted in the desired out of
box power and performance for several CPU generations.

However, a power and performance analysis on Alder Lake and Raptor
Lake CPUs demonstrates that this value results in undesirable higher
uncore power and that seven is a more appropriate value.

Note: the Linux kernel "4ecc933b x86: intel_epb: Allow model specific
      normal EPB value" patch sets the EPB to 7 for Alder Lake.

BRANCH=firmware-brya-14505.B
BUG=b:239853069
TEST=verify that EPB is set by coreboot

Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: I5784656903d4c58bedc5063ee3ef310a99711050
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66059
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-28 14:57:59 +00:00
Jeremy Compostella 117770d324 soc/intel/alderlake: Enable Energy/Performance Bias control
According to document 619503 ADL EDS Vol2, bit 18 of MSR_POWER_CTL
must be set to be able to set the Energy/Performance Bias using MSR
IA32_ENERGY_PERF_BIAS.

Note that since this bit was not set until this patch, the
`set_energy_perf_bias(ENERGY_POLICY_NORMAL);' call in
`soc_core_init()` was systematically failing.

BRANCH=firmware-brya-14505.B
BUG=b:239853069
TEST=verify that EPB is set by coreboot

Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: Ic24abdd7f63f4707b8996da4755a26be148efe4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-28 14:57:54 +00:00
Yunlong Jia ccbf27cbe7 google/trogdor: Add new variant Pazquel360
This patch adds a new variant called Pazquel360 \
that is identical to Pazquel for now.

BUG=b:239987191
TEST=make

Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: I0a9ca4a59fb44256d0d8fcdbdf2a7db533c84412
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Bob Moragues <moragues@google.com>
2022-07-28 14:53:29 +00:00
Paul Menzel 47eb1321c8 commonlib: compiler.h: Use non-concise comment style
The concise multi-line comment style is for inside function bodies to
save space. Outside of it, use non-concise style.

Change-Id: I34d9ec6984b598a37c438fa3c395b5478207e31d
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-07-28 12:32:56 +00:00
Tarun Tuli 646802c598 mb/google/rex: Initial setup for ramstage/early gpio config
This adds the initial gpio configuration for the rex initial variant.

BUG=b:238165977
TEST=Boots and no errors on simics

Change-Id: I55ab31c7943e22df9cec8db4a9f0c3ab6f065ae1
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65952
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-28 11:14:01 +00:00
Subrata Banik a459d360e4 soc/intel/meteorlake: Fix GPIO reset mapping as per GPIO BWG
This patch fixes the documentation discrepancy of GPIO reset type
between PCH EDS and GPIO BWG.

As per GPIO BWG, there are four GPIO reset types in Meteor Lake as
below:
- Power Good - (Value 00)
- Deep - (Value 01)
- Host Reset/PLTRST - (Value 10)
- Global Reset for GPP - (Value 11)

Also, dropped the need for having dedicated reset type for GPIO
community 3. As per the MTL EDS, all GPIO communities have the same
reset type.

BUG=b:213293047
TEST=Able to build and boot Google/Rex without below error msg.
[ERROR] gpio_pad_reset_config_override: Logical to Chipset mapping
        not found

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Id7ea16d89b6f01b00a7b7c52945f6e01e8db6cbd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Will Kim <norwayforest92@gmail.com>
2022-07-28 11:13:34 +00:00
Subrata Banik 2ba4bfef7e soc/intel/gpio: Add new macro for GPP PAD reset type as `Global Reset`
This patch introduces a new macro for GPP PAD reset type as
`Global Reset` as documented in Alder Lake EDS doc 630603.

BUG=b:213293047
TEST=Able to build Google/Kano with this change.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I39428911babc393dd10750801522a00d0b26d3e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-28 11:13:07 +00:00
Michał Żygowski 4a12f54654 MAINTAINERS: Add M. Żygowski and M. Kopeć as MSI MS-7D25 maintainers
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Id7fe11269276f0752545a51d92395cfc03445471
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-07-28 10:13:01 +00:00
Sean Rhodes c14bbbc47b payloads/tianocore: Bind the PCDs for screen size to Kconfig
Bind the PCDs that allow edk2 to use the whole display to a
Kconfig option called TIANOCORE_FULL_SCREEN_SETUP.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ic977a199f3b308c566391e37f126c4fe518b2eb6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-07-27 14:01:15 +00:00
Sean Rhodes 6388a5b892 payloads/tianocore: Correct the multiplication of the SD/MMC timeout
The `call int-multiply` couldn't handle the Kconfig option being a
string so do the calculation in bash.

Tested on:
* Qemu
* StarLite Mk III

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I1879d7efd504e2c42dadb12d2d8add4f69ca7b9c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66161
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-07-27 13:59:57 +00:00
Sean Rhodes ce6f63a898 payloads/tianocore: Add missing CONFIG for SERIAL_SUPPORT
This caused edk2 serial output to be disabled 100% of the time.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: If272369b405e7745fe82f49026cbed0abc50f355
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66160
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-07-27 13:59:19 +00:00
Matt DeVillier 7b087c0594 payloads/tianocore: use BMP (vs SVG) logo file as default
converting the SVG logo to BMP at compile time using 'convert'
introduces terrible aliasing artifacts, so use a properly converted
BMP file as the default instead.

Test: boot qemu w/Tianocore, observe lack of aliasing in coreboot logo

Change-Id: I62d643c24abca57fa35b79732d8cedc83b94815f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-27 13:58:58 +00:00
Matt DeVillier a9bdb4c15e Documentation: Add coreboot logo in BMP format for payload use
Using 'convert' to convert the SVG logo to BMP for Tianocore
introduces terrible aliasing, so add a logo in BMP format
(converted using GIMP).

The default logo file used by Tianocore will be changed in a
subsequent commit.

Change-Id: I2490707a330713709dd4ba8ae99b22b123ba64da
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-07-27 13:58:27 +00:00
Karthikeyan Ramasubramanian 153f976fff soc/amd/sabrina: Disable CCP DMA and HW MODEXP
Enabling them causes firmware keyblock/preamble and/or body verification
failure. Hence disabling them to use software based verification.
Re-enable them once the issue is root-caused.

BUG=b:217414563
TEST=Build and boot to OS in Skyrim with PSP and x86 verstage.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I7e259ae5d790977d08afcb0a77f8d4f38c85f39e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66134
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-27 13:41:30 +00:00
Karthikeyan Ramasubramanian b5ff9b9f3f soc/amd/sabrina: Do not pass SHA operation mode
Currently only SHA_GENERIC is used and does not need to be passed.

BUG=b:217414563
TEST=Build and boot to OS in Skyrim with PSP and x86 verstage.

Change-Id: Id705b1361fffaf940c51515e7f77d7fb0677fc4a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-07-27 13:41:19 +00:00
Franklin Lin 573fa36c3a mb/google/brya/crota: Remove MAC address passthru support
ChromeOS connection manager (shill) already
has support for dock MAC address passthrough, therefore remove the
code to pass a dock's MAC address in ACPI.

BUG=b:235045188
TEST=build coreboot

Signed-off-by: Franklin Lin <franklin_lin@wistron.corp-partner.google.com>
Change-Id: I78320a7c6b0fd5392e24b63bff234229a3f4b9bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66040
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-27 13:41:06 +00:00
Eric Lai c1b01ea9f5 mb/google/brya/var/ghost: Update memory DQ map
Follow latest schematic 6/27 to update the DQ map.

BUG=b:240006200
BRANCH=firmware-brya-14505.B
TEST=build passed.

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I8d0de04a001cab53a245185707ebc9da7a501ec4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66122
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2022-07-27 13:40:50 +00:00
Reka Norman 93928194c4 drivers/wifi/generic: Revert changes to generate missing SSDT for PCIe
wifi

This reverts commit 5e6fd360de.

On nereid, the SSDT entry for the PCIe wifi device is missing, causing
wake-on-WLAN not to work since the _PRW is missing.

It seems like when commit 5e6fd360de changed the SSDT generation logic
for CNVi and PCIe wifi, it broke the PCIe case. `wifi_pcie_ops` are
never assigned to any device, so
`parent && parent->ops == &wifi_pcie_ops` always returns false, and the
`wifi_cnvi_ops` are used even for PCIe devices.

Undo the changes in that CL. This allows both the CNVi and PCIe cases to
work. That CL was meant to fix an issue with the CNVi _PRW containing
garbage, but I can't reproduce this when the change is undone.

It was also meant to fix the following error on CNVi devices, but I
don't see any errors with this change:
[ERROR]  NONE missing set_resources

BUB=b:233325709
TEST=On both nivviks (CNVi) and nereid (PCIe), check that the SSDT
contains the correct wifi device entries (below), including a _PRW
containing the correct GPE, and check that wake-on-WLAN works.

nivviks:
```
    Scope (\_SB.PCI0.CNVW)
    {
        Name (_PRW, Package (0x02)  // _PRW: Power Resources for Wake
        {
            0x6D,
            0x03
        })
        Method (_DSM, 4, Serialized)  // _DSM: Device-Specific Method
        {
            <snip>
        }
    }
```

nereid:
```
    Device (\_SB.PCI0.RP01.WF00)
    {
        Name (_UID, 0x923ACF1C)  // _UID: Unique ID
        Name (_DDN, "WIFI Device")  // _DDN: DOS Device Name
        Name (_ADR, 0x0000000000000000)  // _ADR: Address
    }

    Scope (\_SB.PCI0.RP01.WF00)
    {
        Name (_PRW, Package (0x02)  // _PRW: Power Resources for Wake
        {
            0x23,
            0x03
        })
        Method (_DSM, 4, Serialized)  // _DSM: Device-Specific Method
        {
            <snip>
        }
    }
```

Fixes: 5e6fd360de ("drivers/wifi/generic: Fix properties in generic-under-PCI device case")
Change-Id: I100c5ee3842997c50444e5ce68d583834ed3a8ad
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66063
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-27 13:39:54 +00:00
Tyler Wang 238c199c79 mb/google/nissa/var/craask: Add DPTF passive and critical policies
Add critical, passive policy, and pl values from thermal team.

BUG=b:239495499
TEST=Build and test on MB, system can boot to OS.

Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I8beb3b57ff56c6fe413bb0e3dd43d693aee08e36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66125
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-07-27 13:39:43 +00:00
Srinidhi N Kaushik 9a69002311 soc/intel/meteorlake: Use coreboot native event handler for FSP-S
Beginning FSP 2.2 specifications Fsps Config Upd "FspEventHandler"
was moved to Fsps Arch Upd. Hence we were not seeing Fsps Debug
log was not using coreboot debug library.

This change assigns Fspd Arch Upd FspEventHandler with coreboot
ramstage debug handler when FSP_USES_CB_DEBUG_EVENT_HANDLER
Kconfig is enabled.

Before:

Dumping FSPS_UPD - Size: 0x00001510
0x00000000: 0x41 0x44 0x4C 0x55 0x50 0x44 0x5F 0x53 0x02 0x00 0x00
0x00000010: 0x00

With the fix:

[SPEW ]  Dumping FSPS_UPD - Size: 0x00001528
[SPEW ]  0x00000000: 0x41 0x44 0x4C 0x55 0x50 0x44 0x5F 0x53 0x02
[SPEW ]  0x00000010: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
[SPEW ]  0x00000020: 0x01 0x00 0x00 0x00 0x20 0x00 0x00 0x00 0xAA
[SPEW ]  0x00000030: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
[SPEW ]  0x00000040: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00

BUG=b:237263080
TEST=Able to build and boot MTL RVP, verified the FSP-S debug
log is using coreboot debug library.

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Ie63258f6427b3da7927a866bc3767f548b16e3e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-07-27 13:39:25 +00:00
Matt DeVillier 845222f739 payloads/tianocore: Fix bootsplash/logo handling
commit 108e537928
("payloads/tianocore: Add a proper target for the Boot Splash")
introduced 2 bugs in bootsplash handling:

- the "logo" make target added a spurious "/edk2" to the project dir
- the "logo" make target failed to account for the case where no user-
  defined logo file is used (the upstream Tianocore one will be used
  in this case)

Fix both these issues.

Test: build/boot qemu w/Tianocore w/o user-defined bootsplash file.

Change-Id: Ieebc547670213459823f58956ae87c6bf94b74ef
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-07-27 13:39:17 +00:00
Leo Chou f92ea61e84 mb/google/nissa/var/pujjo: Enable PCIe port 4 for WLAN
Pujjo support WLAN device, enable PCIe port 4 for WLAN device

BUG=b:239899932
TEST=Build and boot on pujjo

Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: Ic8b7240941cf87a4f27963d50fffe28875114a81
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66073
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-27 13:37:23 +00:00
Angel Pons 7127013f7c payloads/ext/tianocore/Makefile: Fix word in comment
revalant ---> relevant

Change-Id: Id31a57644947bf8c0f461dbfc9ca8b1984e9acb8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66151
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-07-27 13:37:03 +00:00
Yu-Ping Wu 3b9d6a41b3 soc/mediatek/mt8195: Skip PCIe ops for eMMC SKUs
To avoid unnecessary PCIe early initialization for non-NVMe devices
(which would take about 150ms on dojo), skip setting PCIe ops when
initializing mt8195 SoC.

BUG=b:238850212
TEST=emerge-cherry coreboot
TEST=Dojo SKU1 (eMMC) boot time <= 1s
BRANCH=cherry

Change-Id: I8945890ba422c0c4eb42683935220b7afbb80dfd
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2022-07-27 13:00:05 +00:00
Yu-Ping Wu 7b7250dfae mb/google/cherry: Introduce mainboard_needs_pcie_init
Implement mainboard_needs_pcie_init() for cherry as a callback for
mt8195 SoC to determine whether to initialize PCIe. When the SKU id is
unknown or unprovisioned (for example at the beginning of the factory
flow), we should still initialize PCIe. Otherwise the devices with NVMe
will fail to boot.

BUG=b:238850212
TEST=emerge-cherry coreboot
BRANCH=cherry

Change-Id: I2ed0ceeb37d2924ca16485fb2d130959a7eff102
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2022-07-27 12:59:59 +00:00
David Wu df721bd0c3 mb/google/brask/var/kuldax: correct Type-A USB3 port0/1 tx_de_emp
1. Set Type-A USB3 port0/1 tx_de_emp to 0x2B to fix the USB3 Gen2 RX
   signal integrity issue.
2. Disable unused USB port.

BUG=b:238230292
TEST=build FW and check Type-A USB3 port0/port1 RX pass

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I8356ca30a965e5774a1556c5cb81e1586c55496c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-26 20:36:31 +00:00
Karthikeyan Ramasubramanian 234e37099a util/amdfwtool: Update the location of PSP verstage and signing key
On SoCs which use A/B recovery layout, PSP verstage and signing keys are
expected to be present only in PSP L2 directory. Update amdfwtool to
include the PSP verstage and signing key only in PSP L2 directory.

BUG=b:239519603, b:238938623
TEST=Build and boot to OS in Skyrim with PSP verstage.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ieeb415be800b7ccf10d6983eb0b567e0a5eaa955
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-07-26 20:36:04 +00:00
Reka Norman 1411ecf6f0 mb/google/nissa/var/joxer: Configure descriptor for eMMC or UFS
Joxer will have both eMMC and UFS SKUs, which require different
settings in the descriptor. So update the descriptor at run-time based
on fw_config.

By default, the descriptor is configured for UFS. This configuration
still boots fine on eMMC SKUs, it just might cause problems with S0ix.

This is a temporary workaround. It will be removed once we've
implemented a proper solution for configuring the descriptor differently
for different SKUs.

BUG=b:238234376
TEST=Make an identical change for nivviks. On both nivviks (eMMC) and
nirwen (UFS), check that it boots and that the logs show the descriptor
being configured as expected.

Change-Id: I14232eb773936f2ecd183687208d332136935601
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-07-26 12:42:24 +00:00
Rex-BC Chen 202f60b960 soc/mediatek/mt8188: Initialize SSPM
SSPM is "Secure System Power Manager" that provides power control in
secure domain. The initialization flow is to load SSPM firmware to
its SRAM space and then enable.

It takes 21 ms to load sspm.bin.

coreboot logs:
CBFS: Found 'sspm.bin' @0x21680 size 0xa815 in mcache @0xffffeac4
mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137348 bytes)

TEST=we can see the sspm logs.
BUG=b:233720142

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Ib6443b64734048c1d71eeac650f36d7c4ac709cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-07-26 12:41:36 +00:00
Rex-BC Chen 0c7a0f9638 soc/mediatek/mt8188: Initialize MCUPM
Load MCUPM firmware and boot up MCUPM in ramstage.

It takes 41 ms to load mcupm.bin.

coreboot logs:
CBFS: Found 'mcupm.bin' @0x12580 size 0xf0c6 in mcache @0xffffead0
mtk_init_mcu: Loaded (and reset) mcupm.bin in 41 msecs (122184 bytes)

TEST=we can see the mcupm logs after reset releases.
BUG=b:233720142

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Id1e62d9d6ede1c453e03eeda0d9b16fafa9e2372
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-07-26 12:40:59 +00:00
Sean Rhodes 108e537928 payloads/tianocore: Add a proper target for the Boot Splash
edk2's default is to show a Boot Splash with their own logo which
looks like it's from the 1960's. Therefore, we replace this image
with coreboot's logo, taken from https://coreboot.org unless a
custom one is specified.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I1b133e2a2cfd45a6650e4523b267f7508974137b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-25 23:46:11 +00:00
Kapil Porwal b1c9f7fd12 mb/google/rex: Set GPIO Tier-1 GPEs in devicetree
Set GPE route as
GPE0_DW0 -> GPP_A
GPE0_DW1 -> GPP_E
GPE0_DW2 -> GPP_F

BUG=b:224325352
TEST=Verified in emulator that there is no regression

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I5e3e09cfc06d2556ea32cca23b3dae114a510498
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-25 21:15:32 +00:00
Subrata Banik 15faf7ea6a Revert "soc/intel/meteorlake: Align TCSS functions through SBI"
This reverts commit b57d172fbb.

Reason for revert: Results into hard hang with serial debug msg as
below:
`[EMERG]  Unable to unhide the P2SB device!`

Intel team is working towards to fix this issue.

BUG=b:239806774
TEST=Able to boot the Intel/MTLRVP with this revert.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic6be37c000afdf4f0c6c22497c233aa0bbc49d48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65500
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-25 21:15:04 +00:00
Subrata Banik 8795c42d29 mb/google/rex: Override LP5 CCC config
This patch overrides `Lp5CccConfig` UPD as per the CCC mapping data
captured from the Rex schematics dated 07/16.

BUG=b:224325352
TEST=Able to build Google/Rex.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ia1d9e3665cff74a803e730c76f62773996efb3dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66049
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-25 15:30:22 +00:00
Subrata Banik bae1de1ac0 soc/intel/meteorlake: Choose PCR write to lock GPIO PAD
Set the SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_PCR config on Meteor Lake
to instruct Pad Configuration Lock.

BUG=b:211573253, b:211950520, b:213596994
TEST=Able to perform GPIO lock programming without error on MTLRVP.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Icd123adb02716149fa51c9e4c987c281f9de2f43
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-07-25 15:30:07 +00:00
Sean Rhodes 5f40fc61c6 mb/starlabs/lite: Add support for VBOOT
Add the required files to support VBOOT for when it is enabled.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I083107b21c23f42193fc88aa174ec22850f45bc8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65705
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-07-25 10:07:03 +00:00
Subrata Banik fb28799ed5 arch/x86: Fix MAX_CPUS check proper for late X2APIC config
The X2APIC_LATE_WORKAROUND kconfig allows bringing APs in XAPIC mode initially hence, it won't work if LAPIC ID is > 0xff.

This patch ensures the MAX_CPUS logic is appropriate while selecting X2APIC_LATE_WORKAROUND kconfig from SoC.

BUG=b:219061518, b:219053812
TEST=Able to build Google/Rex.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I466e6cc568024a9dea80af21e0ebf3572e74a1f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-07-25 10:06:18 +00:00
Leo Chou 4b31af493d mb/google/nissa/var/pujjo: Add new supported memory part
Add pujjo new supported memory parts in mem_parts_used.txt.
Generate SPD id for this part.

Micron MT62F1G32D4DR-031 WT:B

BUG=b:239776504
TEST=Use part_id_gen to generate related settings

Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I95eb194ecbd5d39f66eb566132e75af056899325
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66039
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-07-25 01:03:52 +00:00
Subrata Banik 222852a264 soc/intel/gpio: Update GPIO Lock configuration recommendation
This patch updates the GPIO lock configuration recommendation
kconfig string to ensure the SoC user can select the correct
config as applicable for the SoC.

Note: From MTL onwards GPIO lock config can be performed using
PCR write (MMIO write) and the GPIO team has confirmed this.

BUG=b:213596994
TEST=Able to fix below GPIO lock config error msg on MTL with
`SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_PCR` kconfig enabled.
[INFO ]  Locking pad configuration using SBI
[INFO ]  gpio_pad_config_lock_using_sbi: Locking pad 73
         configuration
[ERROR]  SBI Failure: Transaction Status = 1
[ERROR]  Failed to lock GPIO PAD, response = 1

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Icab1e4849b8e08ee1c695c924599f1513774178f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-25 01:01:58 +00:00
Subrata Banik 471e24e987 mb/google/rex: Add memory configuration board straps
This patch reads various memory configuration GPIOs to fill in below
details:
1. variant_memory_sku()
2. variant_is_half_populated()

BUG=b:224325352
TEST=Able to build Google/Rex.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I23bad8c78523cb56008e6d67e7776e57e42fbeb9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-07-25 01:01:19 +00:00
Subrata Banik 653e157eea soc/intel/meteorlake: Debug consent is set to 3 (USB3 DbC)
This patch ensures the debug consent value is matching with the
inline comment.

TEST=Able to build the Google/Rex.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Icf72eb2aa4064fd78f4f99570a4cf44e41932ec3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66008
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-25 01:00:35 +00:00
Felix Singer c5f7055746 mb/lenovo: Integrate W541 into haswell mainboard
Lots of code from lenovo/haswell can be reused for lenovo/w541. Thus,
integrate it into lenovo/haswell and make it a variant.

Change-Id: If99d842cff777fe27ff63baabc447e69b9d0333c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-07-24 22:24:49 +00:00
Felix Singer b5bdd70758 mb/lenovo/haswell: Make INT15 support T440p specific
In preparation to CB:63514, make the INT15 support specific for the
T440p variant since the W541 doesn't support it currently.

Change-Id: I8dfcc061e1b8a831f75bf9a8035770cb678a85d4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66106
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-24 22:24:24 +00:00
Felix Singer 104b7db894 mb/lenovo/haswell: Hook up variants Makefile
Change-Id: I36091118d98f71dc4141aca4e45858a22d519a9b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-24 22:24:13 +00:00
Wonkyu Kim dc445e9230 intel/common/block/ipu: Add MTL IPU device id
TEST=Build mtlrvp and check IPU0 ACPI ojbect from ssdt

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ib5c3d455d272af0e753c775a5fd3f19851b7937d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66056
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-24 02:49:38 +00:00
Subrata Banik 684d00db4b mb/google/rex: Add GBB related configs
This patch adds more GBB related configs. Select
`HAS_RECOVERY_MRC_CACHE` config.

Additionally, move VBOOT_LID_SWITCH config under VBOOT config.

TEST=Able to build the Google/Rex.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I28976200cbd70dc23f58868ee89c0ac700793be9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66007
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-07-23 20:25:04 +00:00