Using origin/master as the git revision breaks reproducibility, giving
different values depending on when the code was pulled from the
repo at coreboot.org. By using the current revision instead, we get
identical builds.
Change-Id: If4be6e048d6c8e417b8c074199745900ccd82b49
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12807
Tested-by: build bot (Jenkins)
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This requires changes the interface that sets up the system
PLL to support a given reference devider value and given
feedback value.
Also, this requires a change in the dividers used for UART,
USB, I2C setup.
Change-Id: I98cf7c655dbb3e95b8fcee3c7f468122021c70b5
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12765
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The EHCI debug device setup code was removed from broadwell in
commit 49ee5ef: http://review.coreboot.org/11874
However the generic device setup code is in the southbridge/common/intel
directory while broadwell is in the soc directory so this is not used.
Add it back to the broadwell soc to fix undefined reference compile
errors with 'pci_ehci_dbg_dev' and 'pci_ehci_dbg_enable'.
This was tested to compile and produce romstage and ramstage output on a
google/samus board.
Change-Id: Ia93825a1e21a770f6c82d0989cb97980a5c700d6
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/12794
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The port0 and port1 registers were swapped, which meant it did
not work to apply the DTLE settings to the correct SATA port.
This was tested on an unreleased mainboard but is verified with
the documentation to be the correct register addresses now.
Change-Id: Ifb8890a563a741129ec8ddf72e73ab021c7d33da
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/12793
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Locking down the SPI controller with a specific opcode menu kills
the SPI console. Skip this when the SPI console config option is
enabled.
This was tested using an em100 and google/samus board to ensure
the console output does not stop at the finalize step.
Change-Id: Ie460f583214b47544e92d4afa8ef862563a11e36
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/12792
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Upcoming versions of IASL give a warning about unused methods. This
adds an operation after the read to use the local variable and avoid
the warning.
The warning can be completely disabled on the command line, but as it
can find real issues, my preference is to not do that.
Fixes warnings:
dsdt.aml 640: Store (CTMP, Local0)
Warning 3144 - Method Local is set but never used ^ (Local0)
Change-Id: If55bb8e03abb8861e1f2f08a8bcb1be8c9783afe
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12704
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
- Remove it8772f c includes
- Add a new LED API, it8772f_gpio_led
- Stumpy: using it8772f_gpio_led
BUG=chrome-os-partner:28232
BRANCH=Guado
TEST=emerge-guado coreboot chromeos-bootimage
Change-Id: I08de52515d3c1e7e85d1761c09a0cebffda7dda3
Signed-off-by: David Wu <David_Wu@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/241813
Tested-by: David Wu <david_wu@quantatw.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Commit-Queue: David Wu <david_wu@quantatw.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/12797
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Looking at the A10 datasheet, N should go in bits 2:0, but
was being cleared by shifting it left by three bits, then
anding it with 7.
Fixes coverity warning:
CID 1241888 (#1 of 1): Wrong operator used (CONSTANT_EXPRESSION_RESULT)
operator_confusion: (n << 3) & (7U /* 7 << 0 */) is always 0 regardless
of the values of its operands. This occurs as the bitwise second operand
of '|'.
Change-Id: I17e71a73adf37a62607e8e5865b1da749d7278aa
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12779
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Baytrail has I2c Busses 0 to 6, so is supposed to error out
if the I2c driver is called with 7 or greater. Due to an off-by-one
error it could be called with bus 7.
Fixes coverity warning:
CID 1287074 (#1 of 1): Out-of-bounds read (OVERRUN)
3. overrun-local: Overrunning array base_adr of 7 4-byte elements at
element index 7 (byte offset 28) using index bus (which evaluates to 7).
Change-Id: I7caec60298cf27bd669796e0e05e4a896f92befd
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12781
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
- Also update post code comment to keep under 80 characters.
Change-Id: Id0fd0ee5660f2628fe33188855bebb6e3eea8d2e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12780
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Bit 8 of the MR register is automatically set by the PHY
during memory initilization but having it set in the
register leads to a more clear understanding.
Tested on Pistachio bring up board; DDR2 and DDR3 are
initialized properly.
Change-Id: Ie6953e2a96ba2961521b372d280f362ee1c52b94
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12764
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Switching on DQS Gate Early and DQS Gate Extension with
500R DQS/DSQN Resistors. This setup was recommended by
Synopsys.
Tested on Pistachio bring up board; DDR2 and DDR3 are
initialized properly.
Change-Id: I6cd3888d506effe71f5d535367525af2e51f6ba3
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12763
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
clang version now returns:
coreboot toolchain v1.33 November 25th, 2015 clang version 3.6.1
(tags/RELEASE_361/final) (based on LLVM 3.6.1)
Change-Id: I948d7f4d06c244987342cfc7d5c7e728cbed93bd
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12777
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
These files need to be added to cbfs-files after PAYLOAD_CONFIG
and PAYLOAD_VERSION have been defined. Where they were before,
they didn't get added to the final build.
Change-Id: Ib1b230f9eb72a8c1710ef473a9f24c0fb7ec6e17
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12751
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
root_port_init_config() pcie.c wasn't initializing a variable before
passing its pointer to pch_iobp_exec(). pch_iobp_exec() wrote the
uninitialized value into a register.
In theory, the register would only be used if data was being written,
and pch_iobp_exec() was being used to read the data, not write it, so
this change shouldn't have any practical effect.
Fixes coverity error:
CID 1293134 (#1 of 1): Uninitialized scalar variable (UNINIT)
Change-Id: I5d17863d904c6b1ceb30d72b94cd7a40c8fbb437
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12778
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Quoting variables prevents word splitting and glob expansion, and
prevents the script from breaking when input contains spaces, line
feeds, glob characters and such.
See shellcheck warning SC2086.
Change-Id: I7256d2fc2a22bce7723950a534fef6d57cbd097f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12761
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This allows users who build the rom from the board-status repo to
verify that their rom matches the original.
Change-Id: I4e8564e389495909219f92ccdafb8e9568f8f0d0
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12760
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
- Print what the script is doing so when it asks for the ssh password
several times in a row, it's obvious that it's actually doing different
things, not that the password failed.
- Don't print the output from cbfstool - it's not useful.
Change-Id: I785283475e14f242117682800c26db6b4f9f1e2c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12759
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
If the payload_config and payload_version files are in coreboot.rom,
extract and save them.
Change-Id: I36b17ed189f94e2d4e873b0e219e5a9a2abe77a1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12758
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The old serial port read method lost characters from the boot log. This
method works better for me.
- Put get_serial_bootlog arguments into variable names for clarity.
- Fully configure the serial port with stty: disable parity and flow control.
- Change serial port read from reading with 'cat' to reading with 'read'.
- Update help to show current default speed from the variable.
tested under dash, bash, and zsh on several platfoms.
Change-Id: I91ae63a3c226e61019dbdf69c405c3f20ba7db54
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12757
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
As the southbridge largely controls the PCI[e] configuration space
this patch moves the resource allocation from the northbridge
to the southbridge when the extended configuration space region
is enabled.
Change-Id: I0c4ba74ddcc727cd92b848d5d3240e6f9f392101
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12050
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
When enabling the IOMMU on certain systems dmesg is spammed with I/O page faults like the following:
AMD-Vi: Event logged [IO_PAGE_FAULT device=00:14.0 domain=0x000a address=0x000000fdf9103300 flags=0x0030]
Decoding the faulting address:
0x000000fdf9103300
fdf91x Hypertransport system management region
33 SysMgtCmd (System Management Command) = 0x33
3 Base Command Type = 0x3: STPCLK (Stop Clock request)
3 SMAF (System Management Action Field) = [3:1] = 0x1
1 Signal State Bit Map = [0] = 0x1
Therefore, the error appears to be triggered by an upstream C1E request.
This was eventually traced to concurrent access to the SP5100's SPI Flash controller by
multiple APs during startup. Calls to the nvram read functions get_option and read_option
call CBFS functions, which in turn make near-simultaneous requests to the SPI Flash
controller, thus placing the SP5100 in an invalid state. This limitation is not documented
in any public AMD errata, and was only discovered through considerable debugging effort.
Change-Id: I4e61b1ab767b1b7958ac7c1cf20eee41d2261bef
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12061
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The binary is taken from blobs, so the script should live over
there, too.
Change-Id: I3cc0aabc846c352ccf5cb348132b320a37f273a6
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/12725
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
The usage of the pin has changed and therefore this pin needs
to be set up as output and drive low initially.
Change-Id: Ie3eb9cc703f7f73d59fad52ea9e514997d84606a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/12754
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
If we select CONFIG_GDB_STUB without CONFIG_SERIAL:
build/console/console.romstage.o: In function `__gdb_hw_init':
[...]src/include/console/uart.h:74: undefined reference to `uart_init'
build/console/console.romstage.o: In function `__gdb_tx_byte':
[...]/src/include/console/uart.h:75: undefined reference to `uart_tx_byte'
build/console/console.romstage.o: In function `__gdb_tx_flush':
[...]/src/include/console/uart.h:76: undefined reference to `uart_tx_flush'
build/console/console.romstage.o: In function `__gdb_rx_byte':
[...]/src/include/console/uart.h:77: undefined reference to `uart_rx_byte'
Note that CONFIG_GDB_STUB should also work trough usbdebug,
But due to the lack of testing, it has been disabled when added.
This commit gives more information on the issue:
f2f7f03 console: Add console for GDB
Change-Id: I9accf8189dfd2c4ae379c03649d2e5863183457b
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: https://review.coreboot.org/12708
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This is to make towiki pick that information, to make
these boards end up in the laptop list at:
http://www.coreboot.org/Supported_Motherboards
Change-Id: Ibf8bf4bf6566080a34687e36675d4c4c8b89f334
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: https://review.coreboot.org/12716
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The dsdt dependency file is created, but wasn't being used to determine
whether or not to update the dsdt file. If it's present, include it
into the makefile so dsdt.aml gets rebuilt if any of the depencencies
change.
Change-Id: I76bc22541c6b9740841bda891a5b88030cb949cd
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12699
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Implement system reset by calling the watchdog soft reset.
Following the soft reset, the SoC will reset to the same logic
state and therefore have the same effect as a hard (power-on)
reset except for:
- watchdog scratch registers will be unaffected (hard reset
will clear them)
- the real time clock will be unaffected
BUG=none
TEST=tested on Pistachio bring up board
Change-Id: I1332c2249c756f6d8574fc5c407de52f88e60f08
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12755
Tested-by: build bot (Jenkins)
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Verified boot needs hard_reset() now, so offer a dummy implementation
for the Imagination chip. Sorry, I don't have the specs for this chip
anymore to make a real implementation, but I would like to keep this
code from bit rotting.
Change-Id: I15aa47f7d248b99901a2ac0e65a46b43d7718717
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/12723
Tested-by: build bot (Jenkins)
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This file became obsolete when FMAP code moved to src/lib/ and is no
longer built by any Makefile. Let's remove it to avoid confusing people.
Change-Id: I55639af28f9f3d4c4cb0429b805e3f120ecc374e
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12753
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
archive.h is a header file for the programs which need to parse an archive
created by 'archive' tool. See archive.h for the format description.
BUG=chromium:502066
BRANCH=tot
TEST=Tested on Glados
Change-Id: I2bee9d7c12b0e1bce1529dfef360c5fa4ce0872d
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/311201
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://review.coreboot.org/12734
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The remainder of the divide operation was being placed into a Local,
but was never being used, causing an IASL warning. Since this
field is optional, just remove the Local.
Fixes IASL warning:
dsdt.aml 640:Divide (Multiply (CTDN, 125), 100, Local0, PL2V)
Warning 3144 - Method Local is set but never used ^ (Local0)
Change-Id: I0b43ef638b1bc3e1163c45f31f8da57aa0d39e22
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12706
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
To help a user debug issues, print the current XGCCPATH value if
it's set.
Change-Id: I69afdd1c93cfd4747547ecad0d5e1ab4c87511b7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12677
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Section 6.1.3 (Text Strings) of the SMBIOS specification states:
If a string field references no string, a null (0) is placed in that
string field.
Change smbios_add_string() to do that.
Change-Id: I9c28cb89dcfe2c8ef2366c23ee6203e15b7c2513
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/12697
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add the coreboot toolchain version to iasl's version output.
% ./xgcc/bin/iasl -v
Intel ACPI Component Architecture
ASL+ Optimizing Compiler version 20150619-64
Copyright (c) 2000 - 2015 Intel Corporation
coreboot toolchain v1.33 November 25th, 2015
This won't actually be checked until the next version of
iasl so that we don't have to rebuild again for no reason.
The buildgcc version was intentionally not incremented for
this minor change.
Change-Id: I03a1a777fdb84e34bfceb7b1eb43fffbc1f3a2fc
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12688
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
strncmp continues to compare the characters in the input strings past any
null termination it may encounter. Null termination check is added.
Reviewed-on: https://chromium-review.googlesource.com/314815
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Hannah Williams <hannah.williams@intel.com>
Tested-by: Hannah Williams <hannah.williams@intel.com>
(cherry picked from commit ca7022752115eddbcb776f0c0d778249555ddf32)
Reviewed-on: https://chromium-review.googlesource.com/315130
Change-Id: Ifc378966dcf6023efe3d32b026cc89d69b0bb990
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/12721
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This is to match the layout of the non-fsp baytrail to make comparisons
easier and possibly remove duplicate files.
Change-Id: I9a94842d724ab3826de711d398227e7bdc1045ff
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/12686
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
The SB600 code had the base address of the HPET hardcoded throughout.
It looks like the plan was to have it be updated in ACPI if needed,
but this wasn't ever implemented. The variable names being used to
do this update were the same, causing an IASL warning. Because of
this, the operation to update the HPET address actually did nothing.
This was fine, because it didn't actually need to be updated.
- Replace all that code with a #define.
- Add and update some comments in the same area.
Fixes IASL warning:
dsdt.aml 1505: Store(HPBA, HPBA)
Warning 3023 - ^ Duplicate value in list (Source is the
same as Target)
Change-Id: I9ba5fe226a4a464e0045ce7d3406898760df5e5a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12705
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
The macro PCI_DEV_PIRQ_ROUTE ends with a comma and escaped newline.
Ending a macro with an escaped newline is always wrong.
The final comma is not necessary, as all uses of PCI_DEV_PIRQ_ROUTE()
properly separate calls with a comma.
I haven't investigated whether this is causing a real issue, but it should
be leaving gaps in struct baytrail_irq_route.pcidev.
The non-FSP baytrail does not have this issue.
Change-Id: If6782176068b07cb3bc819c00d1cdb1b618bcea8
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/12696
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
$(objgenerated)/empty would touch files before the directory
is created on parallel builds.
Thanks to reproducible-builds.org for hitting this bug.
Change-Id: I7565e9fe130b4e9deaf1c7b9d568ff90b00dda52
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/12717
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Implement hard_reset() as power_reset() to make
vboot happy.
Change-Id: I16831055bd6ba8a8c95836fcf31f29c068153fcc
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/12722
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
Denis 'GNUtoo' Carikli