Commit Graph

44517 Commits

Author SHA1 Message Date
Felix Held 2d4986c168 cpu,soc/x86: always include cpu/x86/mtrr on x86 CPUs/SoCs
All x86-based CPUs and SoCs in the coreboot tree end up including the
Makefile in cpu/x86/mtrr, so include this directly in the Makefile in
cpu/x86 to add it for all x86 CPUs/SoCs. In the unlikely case that a new
x86 CPU/SoC will be added, a CPU_X86_MTRR Kconfig option that is
selected be default could be added and the new CPU/SoC without MTRR
support can override this option that then will be used in the Makefile
to guard adding the Makefile from the cpu/x86/mtrr sub-directory.

In cpu/intel all models except model 2065X and 206AX are selcted by a
socket and rely on the socket's Makefile.inc to add x86/mtrr to the
subdirs, so those models don't add x86/mtrr themselves. The Intel
Broadwell SoC selects CPU_INTEL_HASWELL and which added x86/mtrr to the
subdirs. The Intel Xeon SP SoC directory contains two sub-folders for
different versions or generations which both add x86/mtrr to the subdirs
in their Makefiles.

Change-Id: I743eaac99a85a5c712241ba48a320243c5a51f76
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-25 20:18:40 +00:00
Subrata Banik ac1bba8e34 soc/intel/common: Skip CSE post hook when CSE is disabled
This patch fixes regression introduced by commit bee4bb5f0
(soc/intel/common/cse: Late sending EOP msg if !HECI_DISABLE_USING_SMM)
FAFT test case fail when doing `firmware_DevMode` test.

If CSE is already hidden then accessing CSE registers would be wrong
and will receive junk, hence, return as CSE is already disabled.

BUG=b:203061531
TEST=Brya system can boot to OS with recovery mode.

Change-Id: I2046eb19716c397a066c2c41e1b027a256bd6cf9
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-25 17:14:35 +00:00
Werner Zeh 66b2f20156 drivers/pc80/tpm: Use '%u' as printf formatter for unsigned variables
Use %u instead of %d for printing unsigned variables.

Change-Id: I0f4bf7b80dfbde0802af8ad96fd553cb75d60e6e
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-25 16:12:15 +00:00
Werner Zeh 92ab611c70 drivers/pc80/tpm: Use stopwatch for timeout-loops
There are manual timeout-loops which use a fixed value and udelay().
In all cases there is a debug printk() inside this loop which, when
enabled, takes way longer than the counted microsecond delay. This
leads to the result that e.g. a 1 second delay takes nearly an eternity
if the debug messages are enabled due to the longer function execution
time.

This patch uses the stopwatch scheme for the timeout-loops which still
makes sure that the timeout period is maintained while it takes longer
function calls like printk() into account. In order to keep the minimum
delay between two register accesses on the TPM keep the udelay(1)-call.

TEST=Enable TPM debug messages on a board where the TPM hits a timeout
by failure and make sure that the debug messages occur in the log
just in the timeout period. It still works as expected if the debug
messages are disabled.

Change-Id: I8fd261c9d60a9a60509c847dbc4983bc05f41d48
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-25 16:11:55 +00:00
Mac Chiang 299649a31c mb/google/brya/variants/gimble: Enable Bluetooth offload support
Enable CnviBtAudioOffload UPD

BUG=b:199180746
TEST=emerge-byra coreboot

Signed-off-by: Mac Chiang <mac.chiang@intel.com>
Change-Id: Ic507b1d0f7c2f38de8d24247cd677b897a7463f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-25 14:23:20 +00:00
Ricardo Quesada e1f392ea34 elogtool: add pytest for elogtool
This CL adds a python test for elogtool.
It tests the basic functionality of elogtool: list, clear and add.
A future CL will include more complex tests.

BUG=b:172210863
TEST=pytest elogtool_test.py

Change-Id: If1241ad070d1c690c84f5ca61c0487ba27c2a287
Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-10-25 08:08:41 +00:00
Timofey Komarov 6c8008283c util/inteltool: Add PCH IDs for 200 series chipsets
Signed-off-by: Timofey Komarov <happycorsair@yandex.ru>
Change-Id: Iadad5e79aef9da3fac627adc135525a5001a72b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-24 16:04:49 +00:00
Iru Cai 308a5b9dd1 arch/x86: fix a wrong variable in ioapic_set_max_vectors()
The commit 04a40379b has a wrongly written variable, which sets an
IOAPIC register to a wrong value and makes the Linux kernel unable to
boot.

Tested on HP EliteBook 2760p, the kernel boots after this patch.

Change-Id: Ifda7bb61a431dbf9c2df2f738aa806dd6d8097b8
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-23 16:33:58 +00:00
Felix Held f9146ad569 soc/amd/cezanne,picasso/chipset.cb: drop LAPIC device
After adding code to handle the case of missing the link/bus on the CPU
cluster device in mp_cpu_bus_init, there's no need to have the LAPIC
device in the devicetree any more.

TEST=Mandolin still boots successfully.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Icfc4fb61b373129f3bf4f4de09c38076a8f66733
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-22 14:59:24 +00:00
Felix Held af2da55876 soc/intel/denverton_ns: use mp_cpu_bus_init
After adding the functionality to add a bus/link on the CPU cluster
device in mp_cpu_bus_init if it is missing due to no LAPIC device being
present in the devicetree below the CPU cluster device, we can use
mp_cpu_bus_init as init function in cpu_bus_ops and implement
mp_init_cpus.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I76aebeca1b3227cfd310b6c45f506c042b35ae04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-22 14:59:08 +00:00
Felix Held 60e9114c62 include/device: ensure valid link/bus is passed to mp_cpu_bus_init
When a chipset or mainboard devicetree doesn't have any LAPIC devices in
its CPU cluster, not only the LAPIC device, but also the link/bus
between the CPU cluster device and the LAPIC devices will be missing and
the CPU cluster's dev->link_list will be NULL. This patch handles this
case in the common code like
commit 3c0ecd57c1 (soc/intel/common/cpu:
Handle non-zero BSP APIC ID in init_cpus) and
commit ba936ce5db (soc/intel/denverton_ns:
Ensure CPU device has a valid link) already did in the common Intel SoC
and the Denverton code. With this change all CPUs and SoC that use the
common mp_cpu_bus_init as init function in the CPU cluster's device
operations struct won't require having at least one LAPIC device in the
chipset or mainboard device tree.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib0d85de5cafb6390b8fbd512186899d6a815e972
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-22 14:58:31 +00:00
Lean Sheng Tan dc9b5efa81 soc/intel/elkhartlake: Add PSE PCI devices into header file
Since PSE devices could be initialized as either host owned
(PCI devices) or PSE owned (will be hidden from coreboot and
only visible to PSE interface), add all PSE devices in PCI
list header file for future usage.

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Iaa40cdcb021d05e50504dd85f94e9c021e284d00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58466
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-22 14:54:20 +00:00
Kyösti Mälkki aed59b6721 AGESA binaryPI: Use common acpi_fill_madt()
Change-Id: I01ee0ba99eca6ad4c01848ab133166f8c922684d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-22 14:28:27 +00:00
Kyösti Mälkki c25ecb5443 arch/x86/ioapic: Select IOAPIC with SMP
For coreboot proper, I/O APIC programming is not really required,
except for the APIC ID field. We generally do not guard the related
set_ioapic_id() or setup_ioapic() calls with CONFIG(IOAPIC).
In practice it's something one cannot leave unselected, but maintain
the Kconfig for the time being.

Change-Id: I6e83efafcf6e81d1dfd433fab1e89024d984cc1f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-22 14:18:45 +00:00
Kyösti Mälkki 4bab5691cc mb/emulation/qemu-i440fx: Select IOAPIC
For SMP operation IOAPIC needs to be configured.

For a build with MAX_CPUS=1 emulation might still decode
the IOAPIC MMIO window, it does not really matter to have
it always reserved.

Change-Id: Ia340fc418cd9ceda56a2a10972e130d9f289c589
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-22 14:18:24 +00:00
Kyösti Mälkki 682613f065 sb,soc/intel: Replace set_ioapic_id() with setup_ioapic()
This adds delivery of PIC/i8259 interrupts via ExtNMI on the
affected platfoms.

Change-Id: If99e321fd9b153101d71e1b995b43dba48d8763f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-22 14:16:38 +00:00
Kyösti Mälkki ea6d12a0de sb,soc/intel: Set IOAPIC max entries before APIC ID
This allows to replace set_ioapic_id() call with setup_ioapic()
that also clears redirection table entries.

Change-Id: I854f19c997a96bcdccb11a0906431e3291788cb6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-22 14:15:52 +00:00
Kyösti Mälkki 6139ff9c9a arch/x86/ioapic: Allow IOAPIC with only one vector
Remove the test for count=0 that leaked from drivers/generic/ioapic
implementation. See commit ea2fb8d80 and commit 8cc25d229.

Change-Id: I26944b930851fbea160c844ea46e2faa61c9af8e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-22 14:15:06 +00:00
Kyösti Mälkki 04a40379b0 sb,soc/intel: Set IOAPIC redirection entry count
The number of redirection table entries (aka interrupt vectors) inside
an I/O APIC may depend of the SKU, with the related register being of
type read/write-once. Provide support utilities to either lock or set
this registers value.

Change-Id: I8da869ba390dd821b43032e4ccbc9291c39e6bab
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-22 14:13:42 +00:00
Felix Held e8601f4777 soc/intel/braswell: use mp_cpu_bus_init
Implement mp_init_cpus and use mp_cpu_bus_init as init function in
cpu_bus_ops.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2adcb1e1d79ced804925c81095cc5c0c2e6f9948
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-22 01:28:06 +00:00
Felix Held 37e160efb5 soc/intel/baytrail: use mp_cpu_bus_init
Implement mp_init_cpus and use mp_cpu_bus_init as init function in
cpu_bus_ops.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I057ae8d95bdc510e9e7afb144b692531107fa45d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-22 01:27:48 +00:00
Felix Held 4dd7d11965 cpu/x86/mp_init: move printing of failure message into mp_init_with_smm
Each CPU/SoC checks the return value of the mp_init_with_smm and prints
the same error message if it wasn't successful, so move this check and
printk to mp_init_with_smm. For this the original mp_init_with_smm
function gets renamed to do_mp_init_with_smm and a new mp_init_with_smm
function is created which then calls do_mp_init_with_smm, prints the
error if it didn't return CB_SUCCESS and passes the return value of
do_mp_init_with_smm to its caller.

Since no CPU/SoC code handles a mp_init_with_smm failure apart from
printing a message, also add a comment at the mp_init_with_smm call
sites that the code might want to handle a failure.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I181602723c204f3e43eb43302921adf7a88c81ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-22 01:27:07 +00:00
Felix Held 82faefb339 cpu/x86/mp_init: use cb_err as status return type in remaining functions
Using cb_err as return type of mp_run_on_aps, mp_run_on_all_aps,
mp_run_on_all_cpus and mp_park_aps clarifies the meaning of the
different return values. This patch also adds the types.h include that
provides the definition of the cb_err enum and checks the return value
of all 4 functions listed above against the enum values instead of
either checking if it's non-zero or less than zero to handle the error
case.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4b3f03415a041d3ec9cd0e102980e53868b004b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-22 01:26:30 +00:00
Felix Held 250988d943 soc/amd/common/block/cpu/smm/finalize: simplify finalize_cores
The local variable int r isn't needed, so remove it. This is a
preparation to change the return type of mp_run_on_all_cpus from int to
enum cb_err which will be done in a follow-up patch.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie4c454cbfcc581be41ea3463ea6f852a72886128
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21 20:52:23 +00:00
Felix Held 30f7031488 soc/intel/skylake/cpu: rework failure handling in post_mp_init
Use a boolean type to store the information if any mp_run_on_all_cpus
call failed. This is a preparation to change the return type of
mp_run_on_all_cpus from int to enum cb_err which will be done in a
follow-up patch.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic04ad3e4a781a00ee6edcd7dbd24bc7601be1384
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21 20:51:54 +00:00
Felix Held d27ef5bf6f cpu/x86/mp_init: use cb_err as mp_init_with_smm return type
Using cb_err as return type clarifies the meaning of the different
return values. This patch also adds the types.h include that provides
the definition of the cb_err enum and checks the return value of
mp_init_with_smm against the enum values instead of either checking if
it's non-zero or less than zero to handle the error case.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibcd4a9a63cc87fe176ba885ced0f00832587d492
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-21 20:51:43 +00:00
Tim Chu e0e49c858b include/memory_info.h: Increase DIMM_INFO_TOTAL number from 8 to 16
Increase the number of total dimm to 16 to support system with more
than 8 dimms. Also, remove unneeded comment.

TESTED=On S9S, dmidecode -t 17 shows expected results.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: Iead53e96f37c55ba1b7a13fb62db1a1c10fa2e1f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58440
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-21 20:10:03 +00:00
Tim Chu 13ab1d7879 arch/x86/smbios: Add support for wake-up type in smbios type 1
Add system wake-up type in smbios type 1 - system information.

TESTED=On S9S, can override original value and show expected result
using "dmidecode -t 1".

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: If79ba65426f1f18ebb55a0f3ef022bee83c1a93b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2021-10-21 20:06:59 +00:00
David Wu 91e8c2a1d4 mb/google/brya/var/kano: Correct GPIO GPP_R6 and GPP_R7 setting
Correct GPIO GPP_R6 and GPP_R7 setting to NF2 (DMIC_CLK1 and DMIC_DATA1).

BUG=b:202913826
TEST=FW_NAME=kano emerge-brya coreboot and verify it builds
without error.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ibf8ff0e48c4bab435d082dee27bcd53bc85b088d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CT Lin <ctlin0@nuvoton.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-21 20:05:51 +00:00
David Wu e2c6d9c7cb mb/google/brya/var/brask: Correct SSD power sequence
M.2 spec describes PERST# should be sequenced after power enable.

BUG=b:197385770
TEST=emerge-brask coreboot and verify it builds without error.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ia7e5c7b1a2194d53d98865d33cf1bc6111572876
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-21 20:05:34 +00:00
Kevin Chiu 48bd857789 mb/google/guybrush/var/nipperkin: Enable GPP2 for NVMe bridge eMMC storage
BUG=b:195269555
BRANCH=guybrush
TEST=emerge-guybrush coreboot chromeos-bootimage
     eMMC sku is bootable

Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: If9e0fdc1667cbaac05fdf4c6689d47a561016c9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-21 20:04:59 +00:00
Michael Niewöhner 38107fa80e acpigen,soc/amd,cpu/intel: rework static DWORD for CPPC table
Some elements in the ACPI CPPC table allow static DWORDs. Instead of
using a fake register resource, use a tagged union with the two types
"register" and "DWORD" and respective macros for CPPC table entries.

Test: dumped SSDT before and after do not differ.

Change-Id: Ib853261b5c0ea87ae2424fed188f2d1872be9a06
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-21 20:03:14 +00:00
Karthikeyan Ramasubramanian 679f4fa465 mb/google/guybrush/var/nipperkin: Override GPIO configuration
SOC_PEN_DETECT_ODL, SOC_SAR_INT_L and WWAN_AUX_RESET_L are not connected
in nipperkin. Override those GPIO configurations.

BUG=None
TEST=Build and boot to OS in Nipperkin.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I7e497f83593472ecf4927e5379e1dd7786e77e62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
2021-10-21 19:59:57 +00:00
Karthikeyan Ramasubramanian 72cc0467d7 mb/google/guybrush: Add PCIe Reset GPIO18 to PCIE WWAN DXIO Descriptor
WWAN_AUX_RST_L is asserted during S0i3 entry. But it needs to be
de-asserted before PCIe link training during S0i3 resume. Otherwise the
concerned gpp_bridge_2 PCIe device is not enumerated on Soi3 resume.
This change feeds in the WWAN_AUX_RST_L GPIO in the DXIO descriptor so
that SMU de-asserts this reset on S0i3 resume.

BUG=b:199780346
TEST=Build and boot to OS in Guybrush. Perform suspend/resume cycles for
500 iterations. Ensure that the PCIe devices enumerate fine.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I588c490bf3f8a7beffefc3bfd8ca5167fcbcb9a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-21 19:01:29 +00:00
Karthikeyan Ramasubramanian 0bf9afed7f mb/google/guybrush: Make DXIO Port Descriptor configurable
Instead of a const port descriptor, make it configurable. This will help
to avoid adding duplicate tables for every minor configuration updates.

BUG=None
TEST=Build and boot to OS in Guybrush. Perform suspend/resume, warm and
cold reboot cycles for 10 iterations each.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: If616a08ba54fddab25e5d0d860327255dfd43cbe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58378
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-21 19:00:51 +00:00
Felix Held e198880732 cpu/x86/mp_init: use cb_err as run_ap_work return type
Using cb_err as return type clarifies the meaning of the different
return values. To not change the return types of mp_run_on_aps which is
exposed outside of this compilation unit to keep the scope of this patch
limited, the return value of run_ap_work gets translated to the int
values in mp_run_on_aps. This could also be done by a cast of the
run_ap_work return value to int, but an explicit translation of the
return values should be clearer about what it does there.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id346c8edf06229a929b4783498d8c6774f54a8b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21 18:24:26 +00:00
Felix Held c6f0ed789b cpu/x86/mp_init: use cb_err as mp_init & bsp_do_flight_plan return type
Using cb_err as return type clarifies the meaning of the different
return values. To not change the return types of mp_init_with_smm which
is exposed outside of this compilation unit to keep the scope of this
patch limited, the return value of mp_init gets translated to the int
values in mp_init_with_smm. This could also be done by a cast of the
mp_init return value to int, but an explicit translation of the return
values should be clearer about what it does there.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4129c1db06a877c47cca87782af965b62dcbbdc2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21 18:24:05 +00:00
Felix Held 3dd9cfbdf5 cpu/x86/mp_init: use cb_err as wait_for_aps return type
Using cb_err as return type clarifies the meaning of the different
return values. Also restructure the implementation of wait_for_aps to
not need a local timeout variable.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I86b8c8b0849ae130c78125b83d159147ce11914c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21 18:23:55 +00:00
Felix Held 2939ebd051 cpu/x86/mp_init: use cb_err as apic_wait_timeout return type
Using cb_err as return type clarifies the meaning of the different
return values. Also restructure the implementation of apic_wait_timeout
to not need a local timeout variable.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2fe32c761492d252b154d2f50f2a330cf4f412d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21 18:23:44 +00:00
Felix Held 2461a09b44 cpu/x86/mp_init: use cb_err as install_permanent_handler return type
Using cb_err as return type clarifies the meaning of the different
return values.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifb64b5908b938bb162153433e5f744ab0b95c525
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21 18:23:33 +00:00
Felix Held d04835e1f7 cpu/x86/mp_init: use cb_err as install_relocation_handler return type
Using cb_err as return type clarifies the meaning of the different
return values.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I95f36ba628c7f3ce960a8f3bda730d1c720253cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21 18:23:23 +00:00
Raul E Rangel 3671597b94 cpu/x86: Remove cpu parameter to ap_init
We now pre-populate cpu_info before jumping to the C handler. We no
longer need this parameter.

I moved the stack alignment closer to the actual invocation of the C
handler so it's easier to reason about.

BUG=b:194391185, b:179699789
TEST=Boot guybrush to OS and verify all CPUs still function

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8997683b6613b7031784cabf7039a400f0efdea1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21 17:37:10 +00:00
Raul E Rangel 99c84787b8 cpu/x86: Require CPU_INFO_V2 when selecting PARALLEL_MP
This will reduce the number of AP init paths we need to support.

BUG=b:194391185, b:179699789
TEST=Boot guybrush to OS and see all CPUs initialized correctly

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I05beb591bd7b3a26b6c51c10d4ffd6f8621c12eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21 17:36:57 +00:00
Raul E Rangel 1eae39f4cd arch/x86,cpu/x86: Fix 64-bit CPU_INFO_V2 build errors
There are two possible code sections where the cpu_info macros can be
included: .code32 and .code64

Doing a `push %eax` while in a .code64 section will result in a compiler
error. This macro manually pushes the 32-bit register onto the stack so
we can share the code between 32 and 64 bit builds.

We also can't implicitly dereference per_cpu_segment_selector because
it's a 32-bit address. Trying to do this results in the following:
  E: Invalid reloc type: 11
  E: Illegal use of 32bit sign extended addressing at offset 0x1b2

If we load the address first, then dereference it, we can work around
the limitation.

With these fixes, 64-bit builds can now use CPU_INFO_V2.

BUG=b:179699789
TEST=Boot qemu 64 bit build with CPU_INFO_V2 and 4 CPUs. See AP init
work as expected.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4e72a808c9583bb2d0f697cbbd9cb9c0aa0ea2dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-21 17:36:09 +00:00
David Wu 5a76c79791 mb/google/brya/var/kano: Enable BT offload support
Enable the CnviBtAudioOffload UPD and program the corresponding
BT VPGIOs.

BUG=b:202913826
TEST=emerge-brya coreboot and verify it builds without error.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Id81cba82742f552c098ec3719a0b453b752dc5c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-21 14:37:05 +00:00
Felix Singer ff6416f737 util/release/build-release: Create cross-toolchain version file
Add cross-toolchain version file to the release tarball, which can be
used for pre-setting the variables used in buildgcc.

Change-Id: Iad1e0adaa95b71f161caf978276bfb0a63eac8f4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-21 14:15:57 +00:00
Felix Singer 02750d0400 util/crossgcc/buildgcc: Use pre-set CROSSGCC_VERSION if possible
For reproducibility, a version string is appended to the version of the
tools used in the cross-toolchain. Currently, git is used to determine
that version string at runtime of this script. There are cases, where
it's not possible to determine that version string, e.g. when a release
tarball is used, and if so, the version string is just `v_`.

Thus, allow pre-setting the variable `CROSSGCC_VERSION`.

Change-Id: I888ccd877c93436b5e033528c43bd8667b8d2f10
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-21 14:15:29 +00:00
Sheng-Liang Pan b22a435d22 mb/google/trogdor: determine which panel to use by panel_id for quackingstick
panel_id 6 for AUO B101UAN08.3.

BUG=b:201263032
BRANCH=none
TEST=make

Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I076ded9300c2ec1704a566722870bd0d1a20e9d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58363
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-21 01:57:41 +00:00
Seunghwan Kim 9ce51c3585 mb/google/dedede/var/bugzzy: Add LTE power off sequence
This change adds LTE power off sequence for bugzzy.

BUG=None
BRANCH=dedede
TEST=FW_NAME=bugzzy emerge-dedede coreboot

Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: I6be0e23b9c2c2bed9745011920394006fdaabae6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-21 01:57:23 +00:00
Seunghwan Kim 0c39cd7dab mb/google/dedede/var/bugzzy: Enable/disable LTE function based on FW_CONFIG
Enable/disable LTE function based on DB_PORTS field of FW_CONFIG.
- GPIO control
- USB port setting

BUG=None
BRANCH=dedede
TEST=FW_NAME=bugzzy emerge-dedede coreboot

Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: I8363f8e7052ff9cfa423063a7e8f5a0f9ce1df2c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-21 01:56:58 +00:00