Commit Graph

42594 Commits

Author SHA1 Message Date
Nico Huber c538ce12ae includes: Remove dangling doxygen @}
Change-Id: I05e02f9689c1a6dafb3943657a3db975c2aeacbe
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55592
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18 04:38:50 +00:00
Nico Huber c1536adcf4 includes: Define `CHAR_BIT` in `limits.h`
Change-Id: Ib1d80d0c7457f90596ef5cd9d5ad0c4a33c8d473
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55591
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18 04:38:33 +00:00
Nico Huber 2eae410c54 includes: Provide `wchar.h` with `wchar_t` and `wint_t`
Change-Id: Iacb0e4eaf3f0b6bf843f3bfda5bdfde0f7a98808
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55590
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18 04:38:16 +00:00
Nico Huber 0a31d5e7f5 includes: Add include guards to `stddef.h`
Change-Id: Ifae4f07abd75da9784967c2020eed2c3fe64afa0
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55589
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18 04:37:18 +00:00
Sugnan Prabhu S 9418e33aef drivers/intel/mipi_camera: Remove unnecessary __packed attribute
This patch removes unnecessary __packed attribute from the structure
defined in chip.h

BUG=None
TEST=Tested WFC camera on Brya

Change-Id: I1174606cd22cd353f01d865d0c25bb6f8f8de055
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55566
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18 04:35:47 +00:00
Sheng-Liang Pan f6d46f3bac google/trogdor: change board ID detect to tristate solution.
change binary board ID to tri-state mode.

BUG=b:190250108
BRANCH=None
TEST=emerge-trogdor coreboot

Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I79d1212abc227341be126969ef32e76a635cbdaf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55563
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18 00:58:20 +00:00
Bernardo Perez Priego d4e19bfaba mb/intel/adlrvp_m: Remove DP_HPD 1 & 2 definition from devicetree
Due to latest corresponding UPD filling implementation, this is not
required.

This patch fixed the brokenness caused by
Commit hash b10afbd2e2.

Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I49e434f7bbafcb148e82202697e87c3e4268d7b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-17 20:45:55 +00:00
Martin Roth 57bc814ea1 mb/google/guybrush: Add helpers for cbi fw_config settings
Turn on CBI and add helper functions for determining the board
configuration from the firmware config settings in CBI.

BUG=b:187316460
TEST=Built

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I212e7f413b4d8a7d15122cde90100a0ec28e88a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54639
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-17 19:24:32 +00:00
Felix Held dac1f66c6c soc/amd/stoneyridge: factor out AOAC offset defines
Factoring out those defines brings the Stoneyridge SoC code a bit more
in line with the Cezanne and Picasso SoC code.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifba7f13cc926ac28376233aa0bf317164ca9bbd6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55588
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-17 18:44:04 +00:00
Tim Wawrzynczak 8bca2b18bc mb/google/brya/brya0: Update GPIO tables based on new board rev
This change also restores GPIOs to their proper settings for prior board
revs.

BUG=b:189362981

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I89d7ba94dfbd5e4a000cdde7a0c65f38b53b722d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55325
Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-17 17:13:01 +00:00
Bernardo Perez Priego b10afbd2e2 mb/intel/adlrvp_m: Configure DP_HPD as PAD_NC and disable DdiPortHpd
GPP_A19(DP_HPD1) and GPP_A20(DP_HPD2) were configured native function
(NF1), this causes redundancy with legacy HPD interruption.
This change configures GPP_A19 and GPP_A20 to be no connection and
disables DdiPort1Hpd and DdiPort2Hpd.

BUG=None
TEST=Boot to kernel and verified no kernel HPD pins assertion message.

Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I80ef40a1aca19cd6ad56219175d2fd40890a393d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sanrio Alvares <sanrio.alvares@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2021-06-17 17:05:58 +00:00
Tony Huang e4aa07e2bd mb/google/dedede/var/kracko: Configure I2C high and low times
Configure I2C high / low time in device tree to ensure I2C
CLK runs under I2C_SPEED_FAST (400 kHz).

Touchpad:	387.7kHz
Touchscreen:	389.4kHz
Audio:		387.6kHz
P-sensor:       372.5kHz

BaUG=b:178092096
BRANCH=dedede
TEST=Build and EE check after tuning I2C clock is under 400kHz

Change-Id: I4f6bdd3802cd94671325a89458cde981a2ffa929
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-06-17 17:05:15 +00:00
Rob Barnes 5fd0341fcc ec/google: Fix bad return value
google_chromeec_get_event returns an event number and 0 when there's no event.
This function is usually called in a loop until there are no more events, so
it makes sense to return 0 (i.e. no event) when there's an error.

BUG=b:184074997
TEST=Boot guybrush, no ec errors

Change-Id: I6c0186e4637af9ae24f45cce3638f0913227d6a7
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-17 17:04:56 +00:00
Rex-BC Chen bcf42fb7b1 mb/google/cherry: fix GPIO polarity for TPM interrupt
The GPIO_GSC_AP_INT itself is active low, but the payloads will
create the IRQ using its eint driver, which is active high.

BUG=b:188392736

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ie39f3b9a5dbe15057ef3e96f6c99211949692003
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-06-17 17:03:34 +00:00
Rex-BC Chen e322772355 mb/google/cherry: Add display configuration
BUG=b:189985956

Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
Change-Id: I2b68f6342e7d46d90ea0e7aef9a01ecfd35f8fa9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-06-17 17:03:23 +00:00
Angel Pons 0197edfc5d mb/lenovo/x230: Fix overridetrees not overriding
Any chip entry without a device node below them are silently dropped by
sconfig. Copy the same device node from the devicetree to prevent this.

Change-Id: I778f6b2d980e78142ae12ef941e7d9bd1f753057
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55540
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-17 17:03:05 +00:00
Werner Zeh 2b45ba089b soc/intel/{alderlake,tigerlake}: Fix typo in pmc.h
"corredsponding" --> "corresponding"

Change-Id: I0b0e5d461de29583c269896911167f8a44d84c2a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55555
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-17 15:59:29 +00:00
Angel Pons 4446343adb nb/intel/ironlake: Factor out common uncore ASL
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.

Change-Id: I7e37d32251fa3dcc64aec62dd2d814463c4a9999
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55580
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-17 15:58:44 +00:00
Felix Held 361bb53aa2 soc/amd/picasso: introduce and use devicetree aliases for UART0-3
Since the default state of the MMIO UART devices in the chipset
devicetree is off, the mainboard devicetree entries that disable MMIO
UART devices are removed.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I913a587802020ce4e182b48632cdde1104c2a6e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55545
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-17 14:21:58 +00:00
Arthur Heymans ddbc771524 arch/x86/walkcbfs.S: Fix the cbfs base addr for some fmap
Defining the memory mapped base in fmap for example "FLASH@0xff800000
0x80000" for a 8M flash is optional in fmap files. This will also
reflect in the generated fmap_config.h. Fix the assembly cbfs walker
walkcbfs.S for fmap lacking a definition of the flash base.

Change-Id: I96b18f675e625abee503648ffdc6031978a4269a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-06-17 10:00:45 +00:00
Zhi Li 30701763e3 mb/google/dedede: Create cappy variant
Create the cappy variant of the waddledee reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0).

BUG=b:190515828
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_CAPPY

Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com>
Change-Id: Id5a3b0cb475ee77a9f62523d8322a5e4123ce3be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-06-17 09:58:41 +00:00
Subrata Banik ed5c7ac031 device: Add helper function devfn_disable()
devfn_disable() function is used to disable a device based on
given bus, device function number. This function checks if the
device is at enable state and disables the device.

Change-Id: Ia4a8bfec7fc95c729a5bb156f88e9aab3bf5dd41
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-17 06:48:45 +00:00
Alex1 Kao 857c0cc332 mb/google/dedede/var/pirika: Add camera support
Add camera support in devicetree.

BUG=b:190797339
BRANCH=None.
TEST=built pirika firmware and verified camera function is OK.

Change-Id: I66ded32105f3166e2faec3ea5dcfb93c29822366
Signed-off-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55450
Reviewed-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-17 05:49:17 +00:00
Varshit Pandya 9c414b5685 mb/google/brya: Configure WWAN GPIO early
In order to meet timing requirement of WWAN reseting it in early GPIOs
and asserting Reset GPIO in ramstage

BUG=b:180166408
TEST=Build and boot Brya system and verify enumeration of L850 and FM350 devices

Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com>
Change-Id: Id6d69696b6c645eec3fa314a608c69214bafba82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54912
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-17 05:48:22 +00:00
Nico Huber dca081b5e6 soc/intel/common/pmc: Avoid unnecessary writes of AFTERG3_EN
pmc_set_power_failure_state() is usually called twice, once upon boot
(with `target_on == true`) and once from SMM when the system is shut
down (with `target_on == false`). Assuming settings didn't change
between these calls, there is only one case where we actually need
to write the register value: when updating the state for the
MAINBOARD_POWER_STATE_PREVIOUS feature.

This suits us well as we want to avoid unnecessary writes so we
don't clobber the value set upon boot from within SMM. Due to
inaccessible option backends, SMM might not know the current
option state.

The assumption above, that the option value didn't change, may not
be true if the user changed the option on purpose. In the future,
one would have to reboot the machine for option changes to take
effect. However, this doesn't seem to make a huge difference: One
already needed a controlled shutdown for the update to take effect
before. A reboot doesn't seem much more expensive.

Change-Id: I58dd74b8b073f4f07db090bf7fddb14b5df8239a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55539
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-17 05:46:49 +00:00
Subrata Banik 85c9dda1c4 soc/intel/alderlake/romstage: Refactor soc_memory_init_params function
This patch create separate helper functions to fill-in required
FSP-M UPDs as per IP initialization categories.

This would help to increase the code readability and in future
meaningful addition of FSP-M UPDs is possible rather adding UPDs randomly.

TEST=FSP-M UPD dump shows no change without and with this code change.

Change-Id: I5f23292fd1bd44d0cd55fbefd490b090ccd48365
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55225
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-17 05:43:11 +00:00
Kyösti Mälkki 89a5f0f586 mb/*: Fix some indirect includes
Fix build failures in the case <vc/.../chromeos.h> is removed.

Change-Id: Ie45066f39cd6fb92cca697a6bd5bc8bb8c60b4e7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-17 05:33:34 +00:00
Patrick Georgi ecc5a2f147 3rdparty/libgfxinit: Update to latest ToT
This brings in three new commits that are mostly concerned about
fixing the build with gcc 11.

Change-Id: I35f9100e2bfb2a261b3a0a128697550caf5840d9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55498
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-17 04:29:55 +00:00
Raul E Rangel d742b5e40c timestamp,amd/common/apob_cache: Add timestamps for APOB
Updating the APOB takes a considerable amount of time. I decided to be
granular and split out the operations so we know when we read vs read +
erase + write.

BUG=b:179092979
TEST=Boot guybrush and dump timestamps
   3:after RAM initialization                          3,025,425 (44)
 920:starting APOB read                                3,025,430 (5)
 921:starting APOB erase                               3,025,478 (48)
 922:starting APOB write                               3,027,727 (2,249)
 923:finished APOB                                     3,210,965 (183,238)
   4:end of romstage                                   3,210,971 (6)

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I08e371873112e38f623f452af0eb946f5471c399
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-16 22:42:05 +00:00
Kyösti Mälkki c545baaf47 arch/x86/ioapic: Clear vector table first
Always clear vector 0 entry before optionally overwriting it
with the i8259 timer redirection.

Change-Id: Ia2e96f43e6494711f9fc4fd74229f5817b04b48d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55286
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-16 19:57:51 +00:00
Kyösti Mälkki 5c2594e179 sb/intel/i82870: Use ioapic utility functions
Change-Id: I60ce17fd7640fab064a3d62d8d2b3703993c7b59
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55309
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-16 19:55:09 +00:00
Kyösti Mälkki 8c9a89de99 arch/x86/ioapic: Drop irq_on_fsb as a configurable item
APIC Serial Bus pins were removed with ICH5 already, so a choice
'irq_on_fsb = 0' would not take effect. The related register BOOT_CONFIG
0x3 is also not documented since ICH5.

For emulation/qemu-q35 with ICH9 the choice INTERRUPT_ON_APIC_BUS was
wrong and ignored as BOOT_CONFIG register emulation was never implemented.

For ICH4 and earlier, the choice to use FSB can be made based on the
installed CPU model but this is now just hardwired to match P4 CPUs of
aopen/dxplplusu.

For sb/intel/i82371eb register BOOT_CONFIG 0x3 is also not defined
and the only possible operation mode there is APIC Serial Bus, which
requires no configuration.

Change-Id: Id433e0e67cb83b44a3041250481f307b2ed1ad18
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55257
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-16 19:54:49 +00:00
Felix Held d614e85418 soc/amd/picasso/Kconfig: fix CONSOLE_UART_BASE_ADDRESS for SoC UART2
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6deb2a4c632d39112dcce71f076742a1b62ee89b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-16 19:17:17 +00:00
Felix Held aa7eb08dc8 mb/google/zork: enable UART0 in devicetree
This a mainly a preparation for adding the MMIO UART devices to the
chipset devicetree.

TEST=none

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I533e4a909fdeb1614dbc5df015440b9df5d83233
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-16 19:16:44 +00:00
Felix Held 97fc054979 soc/amd/picasso: introduce and use devicetree aliases for I2C2&I2C3
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I06102f4fcc3bf9de332c71a52c632241b95cde19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-16 19:16:30 +00:00
Felix Held 5d084ddb87 soc/amd/common/block/acpi/bert: fix NULL check
In acpi_soc_get_bert_region after the bert_errors_region call is was
checked if the region parameter is NULL after the call; since region is
a parameter of acpi_soc_get_bert_region, it's non-NULL. What we should
be checking here is if region points to a non-NULL pointer.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reported-by: Coverity (CID:1457506)
Change-Id: I0523504d65725ab2d2df4db28a5dedd90697b917
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-16 19:01:41 +00:00
Felix Held ec225f01b1 soc/amd/cezanne/include/soc/iomap: add eMMC MMIO base addresses
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie97bd6ad076f0ce35fc997d954a003a1252184e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-06-16 16:39:06 +00:00
Felix Held a4480010a4 soc/amd/cezanne,picasso/include/soc/iomap: reflow I2C_DEVICE_COUNT
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7edae2142120dec9e11ef823b561401b7e0bc208
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-06-16 16:38:55 +00:00
Felix Held fab518ba54 soc/amd/cezanne/acpi/mmio: use AOAC offset defines
Even though the code is currently commented out, replace the magic
numbers with the existing defines.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id0dbbadf71f2e5a4d23ee998e2aa0a8b67205845
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-06-16 16:38:37 +00:00
Felix Held 117823e76f soc/amd/cezanne: factor out AOAC offset defines
Factoring out those defines allows using them easily in the ACPI code
without having to use preprocessor macros.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib9dfddb0d4f32a542fa652ff8c14e932c224f247
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-16 16:38:25 +00:00
Felix Held 3b46333b39 soc/amd/picasso/acpi/sb_fch: use AOAC offset defines
Replace the magic numbers with the existing defines.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2d98ea8c5bb0e487c7eef0b0a1cdada9cb04df4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-16 16:38:15 +00:00
Felix Held 038ed9eb7d soc/amd/picasso: factor out AOAC offset defines
Factoring out those defines allows using them easily in the ACPI code
without having to use preprocessor macros.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I99cb03de8782a0eeeb505f567b982099b0e8a18d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-16 16:38:07 +00:00
Felix Held 1532d1c407 soc/amd/cezanne,picasso: add AOAC offset define for the eMMC controller
BUG=b:184978118

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I03554a151aa6a6d9e15d74c63cd02239b788808a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-16 16:37:57 +00:00
Angel Pons 17c89018a5 sb/intel/lynxpoint: Update xHCI _PS0 and _PS3 methods
Lynx Point PCH ACPI reference code version 1.9.1 has two additional
magic steps, which were already present in Broadwell. Add them.

Change-Id: Ia8ca6dcfcfb4ed6b0d957d249b93640ef74670d7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-16 14:51:12 +00:00
Angel Pons c1328a6dba MRC platforms: Fix MRC version printk format specifiers
The printed values are unsigned, and should be printed accordingly.

Change-Id: Ie5edce914c389c70460b1ed3390731e3568340dd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-16 14:50:38 +00:00
Angel Pons 91260932e0 soc/intel/broadwell: Drop `config_t` typedef
The typedef needlessly hides the actual type of the variables.

Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.

Change-Id: I58a58cd402ec679960f460e80b37ff2afb8e3974
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-16 14:50:07 +00:00
Angel Pons 2ec084fffd cpu/intel/haswell: Select `HAVE_DISPLAY_MTRRS`
This option is valid for Broadwell as well as Haswell.

Change-Id: I4f1e9663806bae279f6aca36f09a0c989c12e507
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-16 14:49:55 +00:00
Angel Pons dbdd528ffd soc/intel/broadwell: Separate PCH Kconfig
Split up PCH Kconfig into a separate file. While we're at it, also sort
selected options alphabetically.

Tested with BUILD_TIMELESS=1, coreboot.rom for the Purism Librem 13 v1
remains identical when not adding the .config file in it.

Change-Id: Ic3ff982e7108bf2d25a22e56ac2fbb93070df164
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-16 14:47:45 +00:00
Angel Pons 1708a2fcc9 sb/intel/lynxpoint/Kconfig: Fix typo in help text
Lynxpont ---> LynxPoint

Change-Id: I5af67079ead389beeafd9172aa1b98980dacbd38
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-16 14:46:54 +00:00
Angel Pons a15dea9ab2 mb/prodrive/hermes: Use serial numbers from BMC
The BMC EEPROM layout has been updated to contain system and mainboard
serial numbers. Use these values in SMBIOS Type 1 and Type 2 tables.

Change-Id: I55b51a856b4ad28fd56b02015b2e1d49cd629735
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55275
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-16 09:56:54 +00:00