Commit Graph

28924 Commits

Author SHA1 Message Date
Keith Short c58e3bd90a post_code: add post code for video initialization failure
Add a new post code POST_VIDEO_FAILURE used when the Intel FSP silicon
initialization returns an error when graphics was also initialized.

BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms

Change-Id: Ibc7f7defbed34038f445949010a37c8e368aae20
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-22 17:45:11 +00:00
Keith Short 15588b03b3 post_code: add post code for hardware initialization failure
Add a new post code POST_HW_INIT_FAILURE, used when coreboot fails to
detect or initialize a required hardware component.

BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms

Change-Id: I73820d24b3e1c269d9d446a78ef4f97e167e3552
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-22 17:44:53 +00:00
Keith Short 24302633a5 post_code: add post code for memory error
Add a new post code POST_RAM_FAILURE, used when the Intel FSP code fails
to initialize RAM.

BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms

Change-Id: Ibafefa0fc0b1c525f923929cc91731fbcc1e7533
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-22 16:54:46 +00:00
Keith Short bb41aba0d8 post_code: add post code for invalid vendor binary
Add a new post code POST_INVALID_VENDOR_BINARY, used when coreboot fails
to locate or validate a vendor supplied binary.

BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms

Change-Id: Ib1e359d4e8772c37922b1b779135e58c73bff6b4
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-05-22 16:53:19 +00:00
Keith Short 1835bf0fd4 post_code: add post code for critical CBFS failures
Add a new post code POST_INVALID_CBFS, used when coreboot fails to
locate or validate a resource that is stored in CBFS.

BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms

Change-Id: If1c8b92889040f9acd6250f847db02626809a987
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-22 16:52:48 +00:00
Keith Short 7006458777 post_code: add post code for failure to load next stage
Add a new post code, POST_INVALID_ROM, used when coreboot fails to
locate or validate a resource that is stored in ROM.

BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms

Change-Id: Ie6de6590595d8fcdc57ad156237fffa03d5ead38
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-05-22 14:21:57 +00:00
Jett Rink ba44a27f7f post: during post_code, only call elog when enabled
Now that we call post_code in other stages other than RAMSTAGE, we need
to guard the elog calls with the appropriate condition in order to
compile correctly.

Change-Id: I766c276f28d46492fb05e0e3be71853e21f4e8e0
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-05-22 14:21:42 +00:00
Felix Singer 402fe20e3e mb/up/squared: Add mainboard
Works:
- bootblock, romstage, ramstage
- Serial console UART0, UART1
- SPI flash console
- iGPU init with libgfxinit
- LAN1, LAN2
- USB2, USB3
- HDMI, DisplayPort
- eMMC
- flashing with flashrom externally

WIP:
- Documentation
- VGA
    For some reason Seabios can not find the CBFS region
    and therefore it can't load seavgabios, but generally
    it is working as soon as Linux is booted.
- ACPI

Works not:
- Devices needs proper configuration
- Seabios can't find CBFS region

Untested:
- GPIO pin header
- 60 pin EXHAT
- Camera interface
  - MIPI-CSI2 2-lane (2MP)
  - MIPI-CSI2 4-lane (8MP)
- SATA3
- USB3 OTG
- embedded DisplayPort
- M.2 slot
- mini PCIe
- flashing with flashrom internally using Linux

Change-Id: Ia913534ec176fc600fcd4ce3af335ebe682b0ed4
Signed-off-by: Felix Singer <felix.singer@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-22 12:13:22 +00:00
Elyes HAOUAS fa40e82270 util/sconfig: Move 'static' at beginning of declaration
When using -Werror=old-style-declaration, gcc reports an error:
"'static' is not at beginning of declaration"

Tested on 945G-M4 board.

Change-Id: I7216a4fab2d5878066c871166e6a481d1f201a9d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-05-22 10:09:33 +00:00
Tim Wawrzynczak d93531bcc8 soc/intel/cannonlake: Dump ME f/w version and status information
At the end of device enable, print the ME f/w version number.
Before resume or loading payload, dump the ME's Host Firmware
Status registers.

BUG=b:131437724
BRANCH=none
TEST=Prints seemingly sane values on WHL and CML devices.

Change-Id: Ibeb3a2a85cd84c9baa45f90f20a3dcf69f7d5646
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32527
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-22 10:09:23 +00:00
Kyösti Mälkki fa6233daeb soc/amd/common: Identify AGESA call pattern
The entry to AGESA always follows pattern:

  amd_create_struct()
  amd_dispatch()
  amd_release_struct()

Separate the create/release_struct calls from the more
relevant entry point details.

Change-Id: I1037c9daef3365c8672a198ac60f47fc79ffaea1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31488
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-22 10:08:59 +00:00
Matt DeVillier 1caa3143d6 soc/fsp_baytrail: fix flashconsole on platform
Include spi.c in romstage. Since FSP 1.0 can't use
NO_CAR_GLOBAL_MIGRATION, adjust global variables in spi.c
to use CAR_GLOBAL.

Adapted from early versions of CB:21107

Change-Id: I3487fb8ac317ce920bf1c3ef9d89590051932378
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-05-22 10:06:55 +00:00
Matt DeVillier 8ef2a45bb9 soc/{baytrail/braswell/broadwell}: fix flashconsole on platform
Enabling flashconsole on these platforms fails to build due to
spi.c not being compiled in prior to ramstage. Include in early stages
(bootblock/romstage/postcar) as needed to enable flashconsole support.

Early inclusion of monotonic_timer.c is needed for Broadwell as well.

Change-Id: Idae0578ca92939246021bb85e34b0dcbd41df3b5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-05-22 10:06:50 +00:00
Jacob Garber 9b0d8e7a1f util/romcc: Prevent out-of-bounds read
If 'class > LAST_REGC', then there will be an out-of-bounds read when
accessing 'regcm_bound'. Prevent this by skipping to the next iteration
of the loop. Note that this should not generally happen anyway, since
'result' represents a bitset for the indices of 'regcm_bound', and so
iterations where 'class > LAST_REGC' should already be skipped by the
previous continue statement (since those bits of 'result' should all be
zero).

Found-by: Covericy CID 1129122
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: Id5f5adb0a292763251054aeecf2a5b87a11297b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-05-22 10:03:11 +00:00
Eric Lai b6ee05692d vboot: determine display init before recovery check
Display is required by recovery mode. Determine display init
before recovery check.

BUG=b:133197727,b:133175864
TEST=enter recovery mode, checked the display shows up

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Id6ac611f51241373bca3e2b394a94dcd52d3fde7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-05-22 02:54:27 +00:00
Arthur Heymans be291e8abf soc/intel/fsp1.1: Implement postcar stage
This moves FSP1.1 to use postcar stage to tear down CAR.
On platforms with USE_GENERIC_FSP_CAR_INC the FSP header is found
during the postcar stage so there is no need to push to save it
in CAR global variables.

On FSP1.1 platforms with an open source CAR implementation (Skylake,
even though it still runs the FSP-T), the
soc/intel/common/blocks/cpu/car/exit_car.S code tears down CAR.

This also uses common functions to set up the MTRR to use after
CAR is torn down.

Test: build/boot on google/celes (BSW) and google/chell (SKL)

Change-Id: I2330993842aae9c1365230f0c6bd8a2449dc73a5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-05-21 17:37:32 +00:00
Subrata Banik f91344cd07 soc/intel: Remove unused pointer argument in mca_configure()
Change-Id: Iad3982d9db07a1f17ac39e87ff9c37956e40c258
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: David Guckian
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-05-21 16:20:56 +00:00
Subrata Banik 7196be433e soc/intel/skylake: Remove redundant mca_configure() in ramstage
This patch removes redundant mca_configure() function call
from ramstage to clear machine check exception. First time it's
getting called from soc_core_init() function inside cpu.c file.

TEST=Build and boot SKL/KBL/AML platform without any machine-check
exception.

Change-Id: I7e54fd07816c6317588ab6db06365937c4300ccd
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2019-05-21 16:20:42 +00:00
Patrick Rudolph b461865577 Documentation: Add Rotundu
Add information about flash and programming header.

Change-Id: If34016e20dd580f92695bef5b67dd0c282b0b421
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-05-21 14:23:34 +00:00
Kevin Chiu b19de28c98 mb/google/octopus: Create Garg variant
This commit creates a garg variant for Octopus. The initial settings
override the baseboard was copied from variant bobba.

BUG=b:132668378
BRANCH=master
TEST=emerge-octopus coreboot
Change-Id: I9a36bc5dc3d2b891b1bce86015aa264894d1434b
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2019-05-21 10:20:33 +00:00
Elyes HAOUAS a172228b7a src/arch/arm64: Remove variable set but not used
Change-Id: I4fe5771dd1ebf3d2a981dab08e98f1c018d14133
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-05-21 09:30:00 +00:00
Kane Chen b7f27abb3b mb/google/kohaku: Set ACPI_GPIO_IRQ_EDGE_BOTH for headset INT
Currently, GPP_H0 gpio input rout is set to GPI_INT.
So, ACPI_GPIO_IRQ is required for GPP_H0 in devicetree
This change also aligns hatch's setting.

BUG=b:131742713
TEST=headset is working

Change-Id: Ie1264641bc4dfa5f98b6dab2d6f2133a6f9cbdb8
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ben Kao <ben.kao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-05-21 09:29:44 +00:00
Jacob Garber ae8301fddb util/romcc: Fix parsing of empty string literal
The corner case of an empty string literal was causing romcc to
segfault. This checks if the literal is empty, and if so allocates a
size one buffer for the terminating null character. A test case for
this is added to ensure it doesn't happen again.

Found-by: Coverity CID 1129099
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I067160a3b9998184f44e4878ef6269f372fe68bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-21 09:28:36 +00:00
Jacob Garber b79d2dee2b util/romcc: Free variable after it is used
Free 'arg_type' after it is used to prevent a memory leak.

Found-by: Coverity Scan CID 1129114
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I5e8661547bb7623463ed23fc45269049ffb8c50e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-21 09:27:57 +00:00
Jacob Garber 40a85f85c6 util/romcc: Use 64 bit integers when shifting
'used_indices' is 64 bits wide, so use a fixed-width type to make
that clear. As such, 'index' can have a value of up to 63, so use a
64 bit integer when doing the shifts to prevent overflow.

Found-by: Coverity Scan CID 1287090
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: Ibd089df6be60c8ea46da11e5e83cd58b2e2c54d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32854
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-21 09:27:03 +00:00
Kyösti Mälkki 1dda496a74 binaryPI/00670F000: Remove AGESA.c file
Change-Id: Id48de8b2f6feb6c29d745140c872215faa32eb37
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31487
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-21 09:26:40 +00:00
Kyösti Mälkki 7f8a57e96a soc/amd/common: Refactor AmdCreateStruct() use
AmdCreateStruct() and AmdReleaseStruct() are equally bad
when it comes to lack of correct function declarations
for definitions found in vendorcode binaryPI/AGESA.c.

Replace these with calls that go through the common
module_dispatch() functions.

Change-Id: I611bcbe2a71fb65c8eb759a9dc74cbd9cb74136e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31486
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-21 09:26:21 +00:00
Arthur Heymans 03180212b7 mb/lenovo/r500: Add mainboard
Tested:
- Ethernet NIC
- Wifi RFKill
- USB
- LVDS, VGA with libgfxinit
- Booting with dock attached (COM1)
- Keyboard, trackpoint
- SeaBIOS 1.12
- S3 resume
- Tested in descriptor mode, with vendor FD and ME
- Add VBT to ACPI OPregion

Untested:
- SATA (likely works)
- Trackpad (my cable is broken, likely works)
- Displayport (likely works)
- Descriptorless mode
- DVD drive
- Extra battery
- model with ATI GPU

Does not work:
- Dock hotplug
- Quad core CPU (hangs during AP init, probably needs hardware mod)
- Hotplugging the expresscard slot (works with 'echo 1 | sudo tee
/sys/bus/pci/rescan')

TODO:
- proper dock support
- documentation

note: This board was hard to flash, I had to desolder the flash.

TESTED: on a R500 with an Intel iGPU, SeaBIOS 1.12, Debian 9,
Linux 4.9 from USB

Change-Id: I9e129b2e916acdf2b8534fa9d8d2cfc8f64f5815
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/28644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-21 09:25:41 +00:00
Arthur Heymans 86fa2792b9 mb/lenovo/t400: Add VBT file
All variants (t400, r400, t500, w500) use the same OPROM for the IGD.

Change-Id: I1b9db7b29b22809542f80f60a5e2eb3283fe1c02
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-21 09:25:21 +00:00
Elyes HAOUAS 365cb144c8 src/drivers/intel/fsp2_0: Fix logical 'and' of equal expressions
Probably a copy/paste issue.

Change-Id: I0334bc1f5d145df5af0a307cf8e7c23cc0605f76
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-21 09:25:04 +00:00
Tim Wawrzynczak ddbf2c4af0 soc/intel/cannonlake: Configure SPI CS parameters in FSP UPD.
When FSP UPD parameters are configured, also configure the GSPI CS lines
appropriately.  GSPI driver assumes CS0 is the CS signal to use.

BUG=b:130329260
BRANCH=None
TEST=Boot Kohaku, TPM communcation still functional.

Change-Id: Ic816395b7d198a52c704e6cabcb56889150b741c
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32791
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-20 16:28:38 +00:00
Mike Banon 334e8360ef src/vendorcode/amd/agesa/f15tn: Update microcode to version 0x600111F 2018-03-05
This microcode update for CPU IDs 0x610F01/0x610F31 improves system stability:
in particular, fixes Xen hardware virtualization freezes. Also it attempts to
patch some Spectre-related security vulnerabilities. This new microcode has been
tested by multiple coreboot community members and found working perfectly.

Old version:    0x600110F [2012-01-11]
        replaced by
New version:    0x600111F [2018-03-05]

Change-Id: Ied5da0ff85abb63c2db2eeafd051b8e00916d961
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/28273
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: <awokd@danwin1210.me>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-20 15:15:22 +00:00
Mike Banon cf041d8c83 src/vendorcode/amd/agesa/f16kb: Update microcode to version 0x7000110 2018-02-09
This microcode update for CPU ID 0x700F01 improves system stability:
in particular, fixes Xen hardware virtualization freezes. Also it attempts to
patch some Spectre-related security vulnerabilities. This new microcode has been
tested by multiple coreboot community members and found working perfectly.

Old version:    0x700010B [2013-07-09]
        replaced by
New version:    0x7000110 [2018-02-09]

Change-Id: Iebe6e54d922378a8a1feb97f37b08ac50c8234b2
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/28370
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-20 15:15:10 +00:00
Subrata Banik 0c89ed93d7 mb/google/{arcada, hatch, sarien}: Override FSP default GPIO PM configuration
sarien/arcada:

GPIO_COMM_0/2/3/4: Enable gpio community all PM configuration
GPIO_COMM_1: Disable RCOMP clock gating due to GPP_D18 IRQ mapped for H1 TPM.

hatch:

GPIO_COMM_0/1/2/3: Enable gpio community all PM configuration
GPIO_COMM_4: Disable RCOMP clock gating due to GPP_C21 IRQ mapped for H1 TPM.

BUG=b:130764684
TEST=H1 TPM interrupt working find and able to boot from fixed boot media

Change-Id: Ia4d5483847a4d243b9038119d4bb5990591cc754
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-20 14:50:38 +00:00
Subrata Banik 97ae7430a8 mb/google/dragonegg: Override FSP default GPIO PM configuration
GPIO_COMM_0/2/3/4: Enable gpio community all PM configuration.
GPIO_COMM_1: Disable RCOMP clock gating due to GPP_D16 IRQ mapped for H1 TPM.

BUG=b:130764684
TEST=H1 TPM interrupt working find and able to boot from fixed boot media

Change-Id: I1f83f938f201c6574367960b1027555767cf6f3d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-20 14:50:28 +00:00
Subrata Banik 76a8f9e29f soc/intel/cannonlake: Make use of gpio_pm_configure()
Provide option in chip.h to set dynamic local clock gating
setting.

BUG=b:130764684
TEST=Able to build and boot CML.

Change-Id: Iec60076398b745e11d5025e4d7a5c35374d918a4
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-20 14:50:16 +00:00
Subrata Banik dd5fa02426 soc/intel/icelake: Make use of gpio_pm_configure()
Provide option in chip.h to set dynamic local clock gating
setting.

BUG=b:130764684
TEST=Able to build and boot ICL.

Change-Id: Ic30a490aadb8cc9c05a19a05533ab0196c69b7f1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-20 14:50:06 +00:00
Subrata Banik abdc9bc8c8 soc/intel/common/block/gpio: Add gpio_pm_configure() function
This patch adds new function to perform gpio power management
programming as per EDS.

BUG=b:130764684
TEST=Able to build and boot from fixed media on ICL and CML.

Change-Id: I816a70ad92595f013740a235a9799912ad51665e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-20 14:49:54 +00:00
Keith Short 8ef6732b94 ec/google/wilco: Add support for KB_ERR_CODE to Wilco EC
Adds support for the KB_ERR_CODE command on the Wilco EC. This command
is used to drive diagnostic LEDs on the platform after a failed boot.
This change also adds the Wilco EC mailbox command support to bootblock
and verstage so that those stages can use the KB_ERR_CODE command.

BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms

Change-Id: I96d17baf57694e4e01c676d80c606f67054cd0c3
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32776
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-20 14:48:10 +00:00
Elyes HAOUAS 686b539949 i945: Add device identification D2:F1
Add device identification D2:F1 for desktop version.
(see Intel 945G/945GZ/945GC/945P/945PL Express Chipset
Family datasheet page 192)

Change-Id: Ie060644d635a7031ee6f55420d63751192481091
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-05-20 14:45:55 +00:00
Elyes HAOUAS bd96a84300 util: Fix typo on plural form of index
Change-Id: Idc165f8eafacf3130a29b701bc3610c1a67f69d5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2019-05-20 14:45:35 +00:00
Keith Short cc8665eacc console: Add new function die_with_post_code()
Add a new helper function die_with_post_code() that generates a post
code and an error string prior to halting the CPU.

BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms

Change-Id: I87551d60b253dc13ff76f7898c1f112f573a00a2
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32838
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-20 14:44:27 +00:00
Jett Rink 1eeb94ff4a util/scripts: update references to cross-repo-cherrypick
It appears that the rebase.sh script was renamed to
cross-repo-cherrypick and changed directories. Update comments to
reflect that change.

Change-Id: I863df48378feb48c9b195b1778dcaf1972a4f105
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-20 14:44:08 +00:00
Paul Menzel 2e585a12a2 sb/amd/cimx/sb800: Get rid of power button device in coreboot
Apply commit d7b88dcb (mb/google/x86-boards: Get rid of power button
device in coreboot) to AMD Brazos boards [1]:

> As per the ACPI specification, there are two types of power button
> devices:
> 1. Fixed hardware power button
> 2. Generic hardware power button
>
> Fixed hardware power button is added by the OSPM if POWER_BUTTON flag
> is not set in FADT by the BIOS. This device has its programming model
> in PM1x_EVT_BLK. All ACPI compliant OSes are expected to add this
> power button device by default if the power button FADT flag is not
> set.
>
> On the other hand, generic hardware power button can be used by
> platforms if fixed register space cannot be used for the power button
> device. In order to support this, power button device object with HID
> PNP0C0C is expected to be added to ACPI tables. Additionally,
> POWER_BUTTON flag should be set to indicate the presence of control
> method for power button.
[..]
> This change gets rid of the generic hardware power button from all
> google mainboards and relies completely on the fixed hardware power
> button.

The same problem exists with the AMD Hudson devices in coreboot.

For AMD Hudson (2) and Yangtze based devices this was removed in commit
44f2fab8 (AMD hudson and yangtze boards: Let mainboard declare power
button) [2].

Two devices are detected.

    $ dmesg | grep Button
    [    0.209213] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input0
    [    0.209254] ACPI: Power Button [PWRB]
    [    0.209332] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input1
    [    0.209349] ACPI: Power Button [PWRF]

   $ sudo evtest
    No device specified, trying to scan all of /dev/input/event*
    Available devices:
    /dev/input/event0:      Power Button
    /dev/input/event1:      Power Button
    [..]

[1]: https://review.coreboot.org/5546
[2]: https://review.coreboot.org/27272

Change-Id: I0cbecb72f7e1bf3d051d3b7656c6af4d6f43b497
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/27496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-05-20 14:43:44 +00:00
Krishna Prasad Bhat 811a51ac67 mb/google/hatch: Change SD_CD# reset config to PLTRST
The system should boot fine to OS on pressing power button before the
system enters G3. However, on hatch, we observe that the system waits
for few seconds at "Starting kernel" and then resets, with SD card tray
inserted and SD_CD# pad reset config set to DEEP. Hence configuring SD_CD#
pad reset config to PLTRST.

BUG=b:129933011
TEST=Built and verified on hatch.

Change-Id: Ic4466b96332f095ff39b28d98607e95fc3d12d6a
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-20 14:42:27 +00:00
Frans Hendriks 20989630c4 soc/intel/braswell/pmutil.c: Use GEN_PMCON1 for RTC status
cbmem_find is not available in every stage.
Remove usage of cbmem_find() and use GEN_PMCON1 always.

BUG=NA
TEST=Booting Embedded Linux on Facebook FBG-1701

Change-Id: Id97d57864b3e241e8f046d9b1caebdce199a46b1
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-20 14:42:09 +00:00
Jamie Chen 232113e7cd mb/google/octopus: Override emmc DLL values for Casta
New emmc DLL values for Casta

BUG=b:122307918
TEST=Boot to OS on 12 systems

Change-Id: Ie51885fb9628fa093ecc38f4a3f3157f751ca9ab
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2019-05-20 14:41:47 +00:00
Frans Hendriks c1b77c1391 security/vboot/vboot_crtm.h: Remove ENV_ for vboot_measure_cbfs_hook()
vboot_measure_cbfs_hook() is included when CONFIG_VBOOT_MEASURED_BOOT
is enabled, but this function is defined as 0 in vboot_crtm.h using ENV_

Remove ENV_ for vboot_measure_cbfs_hook() function definition.
This function is added to bootblock stage also.

BUG=NA
TEST=Build Google Banon and Google Cyan

Change-Id: Ic62c18db09c119dfb85340a6b7f36bfd148aaa45
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-05-20 14:41:40 +00:00
Joel Kitching 7576bd7f42 vboot: save whether developer mode is enabled
Save whether or not vboot has selected developer mode as a flag
in vboot_working_data.  Other coreboot code may access this flag
without needing to consult vboot_handoff (which is in the process
of being deprecated).

BUG=b:124141368, b:124192753
TEST=make clean && make test-abuild
BRANCH=none

Change-Id: Ieb6ac4937c943aea78ddc762595a05387d2b8114
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-05-20 12:48:19 +00:00
Elyes HAOUAS fc46ad8a8b src/Kconfig: Move DRAM section to src/lib/Kconfig
These Kconfigs are mostly used in src/lib/.

Change-Id: I7aa5436c6ff5fef53fde2081e902d793f3581c1e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32882
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-20 10:58:56 +00:00