Commit Graph

13033 Commits

Author SHA1 Message Date
Kyösti Mälkki 88ff8b541f AGESA fam15tn / fam15rl / fam16kb: Move LPC decode enable for serial port
Move LPC decode enable out of agesawrapper.c. It should not be on the
execution path of AP CPUs and function is not related to AGESA per se.

Change-Id: I19d6a20fbc7a3d28601caa9aaa1d73d6930257ae
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7602
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-12-03 08:08:18 +01:00
Kyösti Mälkki 8c20a04cae AGESA fam14: Common agesawrapper
Use copy of amd/persimmon.

Change-Id: I7404cb164df9065bcdbaaf5367018870ea675adc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7157
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-03 08:07:20 +01:00
Kyösti Mälkki 923302ae61 AGESA fam12: Common agesawrapper
Change-Id: Ic44d827323dc0d3c776e79c22088a2f1f654bcf2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7156
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-03 08:07:02 +01:00
Kyösti Mälkki e68f4ffb97 AGESA fam15: Common agesawrapper
Place empty OemCustomizeInitEarly() and OemCustomInitPost() in a
common file for now and split eventlog parser to a separate file.

Change-Id: Ia8277ad13a800898b3e1a4e9c8fbd838ae2efeae
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7155
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-03 08:06:47 +01:00
Kyösti Mälkki 9bb38c963f AGESA fam15: Move LPC decode enable for serial port
Move LPC decode enable out of agesawrapper.c. It should not be on the
execution path of AP CPUs and function is not related to AGESA per se.

Change-Id: I19c6a9c7d71c9899fdc898c09c337d747424fcec
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7601
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-03 08:06:35 +01:00
Kyösti Mälkki 27c4edace6 AGESA: Report events with AGESA_EVENTLOG()
NOTE: For fam12 and fam14 ASSERT() is defined empty so execution may
fall through critical failures.

Change-Id: Ifef65d749d340f1df3a43b5fcb38c4315ef944e8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7154
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-12-03 08:04:53 +01:00
Kyösti Mälkki f21c2ac055 AGESA: Use common header for agesawrapper
Change-Id: I5189d0c55635aeb29553fd04a67490cfee3d88d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7153
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-12-03 08:04:34 +01:00
Kyösti Mälkki 2fd006a3e3 AGESA Hudson/Yangtze: Remove unused GPP configuration in devicetree
GPP config from devicetree.cb is not implemented for fam15tn/fam16kb.

Also only for asus/f2a85-m the configuration value matched the actual
programming.

Change-Id: Ic7a9aa1360f4ba35d202f3f7dd1fc3c20a52dde0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7600
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-12-03 08:04:18 +01:00
Kyösti Mälkki 7d8cde756e AGESA Hudson/Yangtze: Remove obsolete devicetree parameters
Change-Id: Ic6affae7e508f28b131c7d07191289f4fcbf2d74
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7599
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-03 08:04:00 +01:00
Kyösti Mälkki 96d92765e1 SPI: Add vendor Atmel
Change-Id: I60e578003b857f5dcabb2e9bc75aa46acddb62b8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7433
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-12-03 05:29:04 +01:00
Kyösti Mälkki 3f382c7c08 SPI: Add Macronix part MX25U12835F
Change-Id: I82482419afdf536a19b99c79131fa5844aaaec07
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7432
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2014-12-03 05:20:34 +01:00
Edward O'Callaghan 893a55ec89 southbridge/amd/agesa/hudson/early_setup.c: Use IS_ENABLED macro
Change-Id: I2adb5a8fe2cede988cc6fdef5ff81da86d267175
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7624
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-02 18:28:58 +01:00
Alexander Couzens 890073915f cubieboard: use new arm bootblock infrastructure
commit 8b685398 (ARM: Overhaul the ARM Makefile.)
change config flags for cpu and mainboard bootblock initialization.
Tested on a20/cubieboard2.

Change-Id: I2a1019c2881bc7aada15322841204992d0106453
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/7188
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-02 14:18:35 +01:00
Alexander Couzens 9b79731dd4 arm/allwinner/a10: use new arm bootblock infrastructure
commit 8b685398 (ARM: Overhaul the ARM Makefile.)
changes config flags for cpu and mainboard bootblock initialization.
Tested on a20/cubieboard2.

Change-Id: I753aa60ff66de9a3352a3a0759e4d0be9d8ae1c7
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/7187
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-02 14:18:34 +01:00
Elyes HAOUAS a3ea1e4590 i945: Bit 49 of CAPID0 trivial fix
Change-Id: Ifeb277c375a0685b76fa01174a990a4cd05023bc
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: http://review.coreboot.org/7587
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-02 13:58:08 +01:00
Patrick Georgi 59ab4e99ee nvramtool: make sure that strings are 0-terminated
The call site expects them to be.

Change-Id: Ic05fc5831f5743d94fe617dfb3b9e329f01866d1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7621
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-02 11:02:17 +01:00
Patrick Georgi 10b3994f1a Drop tianocoreboot ("Project PIANO")
There are four other approaches to provide UEFI on
top of coreboot that actually get to a UEFI shell.
No need to keep this experiment and confuse users.

Change-Id: I81c52e24099852f6daf0d5725aec707bdfd75ae1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7622
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-02 11:02:09 +01:00
Patrick Georgi 546953c0c5 Replace hlt with halt()
There were instances of unneeded arch/hlt.h includes,
various hlt() calls that weren't supposed to exit (but
might have) and various forms of endless loops around
hlt() calls.

All these are sorted out now: unnecessary includes are
dropped, hlt() is uniformly replaced with halt() (except
in assembly, obviously).

Change-Id: I3d38fed6e8d67a28fdeb17be803d8c4b62d383c5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7608
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-02 10:25:55 +01:00
Patrick Georgi 24cca75b47 build system: remove ROMSTAGE_ELF variable
No need to keep that just because x86 has one
extra linking step.

Change-Id: Iffdbf64e0613f89070ed0dfb009379f5ca0bd3c1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7611
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-02 10:24:57 +01:00
Marcel Meißner fffd772e35 tianocoreboot: Update config to make it compile
Change-Id: Ie584460529dcd342702dc00787df9c20e2ef10e7
Signed-off-by: Marcel Meißner <mm-meissner@gmx.de>
Reviewed-on: http://review.coreboot.org/7541
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2014-12-02 10:20:18 +01:00
Andrew Engelbrecht e8905312f0 nvramtool: cmos_read(): Use malloc() instead of alloca()
Fixes crash occurring when 'nvramtool -a' tried to free a prematurely
freed pointer. (Tested on x60)

malloc() is correct because the pointer is accessed outside the calling
function. The pointer is freed in the parent function list_cmos_entry().

Change-Id: I1723f09740657f0f0d9e6954bd6d11c0a3820a42
Signed-off-by: Andrew Engelbrecht <sudoman@ninthfloor.org>
Reviewed-on: http://review.coreboot.org/7620
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-02 10:15:00 +01:00
Ronald G. Minnich e0e784a456 Add UCB RISCV support for architecture, soc, and emulation mainboard..
Works in the RISCV version of QEMU.

Note that the lzmadecode is so unclean that it needs a lot of work.
A cleanup is in progress.

We decided in Prague to do this as one thing, because it forms a nice case study
of the bare minimum you need to add to get a new architecture going in qemu.

Change-Id: If5af15c3a70733d219973e0d032746f8ab027e4d
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/7584
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2014-12-01 19:06:43 +01:00
Patrick Georgi 796fe068d3 Mark non-executable files non-executable
No need to mark Makefiles, C files or devicetrees
executable.

Change-Id: Ide3a0efc5b14f2cbd7e2a65c541b52491575bb78
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7618
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-01 17:33:07 +01:00
Paul Menzel 9562834229 3rdparty: Update to latest commit in blobs repository
Update to commit 9f68e20e (AMD KaveriPI: Add PI header files to support
binary AGESA release), which is the latest commit in the blobs
repository.

Change-Id: I3d643f7565700272c22b59ed764c3269801f4413
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/7595
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-01 08:50:32 +01:00
Damien Zammit 126a2a8a78 gigabyte/ga-b75m-d3h: Add new Intel mainboard
This is based on LENOVO X230 port.
Board boots to linux via SATA or USB.
All USB ports are working.

Remaining Issues:

1. Native raminit sometimes fails with "timC write discovery failed"
   even without changing the ram configuration. I suggest
   altering the native raminit code so that it reboots
   if that message appears to give a chance for the
   boot process to recover.

2. VGA does not work.
   Native graphics initialization only supports LVDS and
   the VGA Option ROM still hangs when run in SeaBIOS.

Change-Id: I91a7aab96d6c5f213b097cd55fcc47d4c94b3172
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/7341
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-11-30 14:56:19 +01:00
Patrick Georgi 6d0cba7978 gcc.c: Test for gcc, not for non-clang
This is gcc specific, not necessary-everywhere-but-on-clang.

Change-Id: Ie02587bd41c856cbf730ea2f72f594a20b5fefbe
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7609
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-11-30 12:20:37 +01:00
Patrick Georgi 32a5a5f467 buildgcc: support DESTDIR for libelf
The libelf build system doesn't support the
DESTDIR variable. Work around by mangling prefix
when installing.

Change-Id: I3a56eb2bf919bcb9b586b945dce26a02dbaff931
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7613
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-11-30 12:20:17 +01:00
Patrick Georgi 4f75af9fe2 Unify remaining binutils invocations
No need to pass calls through gcc in one case and
directly to binutils in another. Just always call
binutils.

Change-Id: Icf9660ce40d3c23f96dfab6a73c169ff07d3e42b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7610
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-11-30 12:20:15 +01:00
Patrick Georgi 02ac6c3572 build system: only do the compiler test for gcc
There isn't a history of broken clang compilers yet
so let's give it a chance.

Change-Id: Iddb63700e3850116313c1ddee69111f936191055
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7607
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-30 12:20:11 +01:00
Patrick Georgi bd79c5eaf1 Replace hlt() loops with halt()
Change-Id: I8486e70615f4c404a342cb86963b5357a934c41d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7606
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-30 12:20:07 +01:00
Patrick Georgi 1b2f2a0714 Introduce halt()
It's a portable and generic way to halt the system.
Useful when waiting for the platform to reset.

Change-Id: Ie07f3333d294a4d3e982cbc2ab9014c94b39fce0
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7605
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-30 12:20:05 +01:00
Patrick Georgi 5f967492e3 intel/sandybridge: make sure to stay in HLT until reboot
It also tells the compiler that we never leave here.

Change-Id: I824569efd46b577588387b29fc7781abf8c42385
Found-by: Coverity Scan
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/7579
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-30 12:20:03 +01:00
FEI WANG 4a145052a3 vendorcode/intel/fsp: Update FSP_VENDORCODE_HEADER_PATH
Minor change in Kconfig to remove "/" defined in
FSP_VENDORCODE_HEADER_PATH and update the path in Makefile.inc.

Change-Id: Ic19ab9560aabe307d45b560f167874383cc920aa
Signed-off-by: Fei Wang <wangfei.jimei@gmail.com>
Signed-off-by: FEI WANG <wangfei.jimei@gmail.com>
Reviewed-on: http://review.coreboot.org/5894
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-11-29 22:58:31 +01:00
York Yang 4a91f64431 mainboard/intel/minnowmax: use Baytrail Gold3 FSP
Baytrail Gold3 FSP support memory down configuration.  Update Minnow Max
to use Gold3 FSP.  Set memory down data in devicetree.cb, instead of use
different FSP image.

Change-Id: Ic03da2d2a1cee5144b9a013d3dd9f982ff043123
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: http://review.coreboot.org/7581
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-11-29 22:57:50 +01:00
Edward O'Callaghan 5f19eb6f40 ec: Use DEVICE_NOOP macro formalism over static stub func
The in source comment:

	/* This function avoids an error on serial console. */

refers to the resource allocator needing to find a non-NULL
function pointer else complaints of "... missing read_resources"
will be spewed.

Unfortunately/fortunately (depending on the time of day) compiler
optimisers have gotten a bit better at optimising away no-op functions
leading to the very message these stubs attempted to avoid. By using
the DEVICE_NOOP formalism that is static inlined 'suggests' (not enforces)
to the compiler to keep these symbols around.

Change-Id: I182019627b6954a4020f9f70e9c829ce3135f63c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7598
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-11-29 14:04:35 +01:00
Patrick Georgi d3060edce2 i945: make PCIe link wait sensible
Waiting for (a & 4) == 3 to become true proves futile
unless you're searching for defective hardware or
neutrino impact.

While I'm not 100% sure that this is the actual intent
(no data-sheets at hand, and the public ones are unhelpful
as usual), it's the likely correct version and it's also
boot-tested on intel/d945gclf.

While at it, replace register number with the name found
in the public datasheet.

Change-Id: I4b87001967a2013e0089806e8cd606d5ee81b0d9
Found-by: Coverity Scan
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6575
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-11-28 17:56:29 +01:00
Kyösti Mälkki 24d875bddc ACPI: Remove CBMEM TOC from GNVS
This existed for ChromeOS but was no longer used with DYNAMIC_CBMEM.
See commit a0b4a8d.

Change-Id: Iae82498ab729df5682d89e66bb9de96457e91619
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7465
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-11-28 07:45:17 +01:00
Edward O'Callaghan 58b532d586 mainboard/lenovo/g505s/devicetree.cb: Fix duplicate typo
Change-Id: Ic2b8ca54b9a16c13439b3081969deec0b7187e01
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7588
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-11-28 06:59:53 +01:00
Edward O'Callaghan 41755901f0 Use AMD_F15_TN_A0 define in FTnLogicalIdTables.c
Change-Id: I6b20ded866fa0418bd24ce9eef3775557c2feec7
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7562
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-11-28 06:59:38 +01:00
Edward O'Callaghan 1ab41db0e3 drivers/i2c/at24rf08c/lenovo_serials.c: Use NULL over '0'
Change-Id: I7d8922d1812814ea2ebd72aaf5b5e28dc592bfb3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7590
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-11-28 04:53:15 +01:00
Edward O'Callaghan 07d89a0e0d drivers/i2c/at24rf08c/lenovo_serials.c: Upper-case'ify
Thereby making consistent with other i2c drivers

Change-Id: I5ddc9d98fbbc1db68a933e3b9a6b92f309b72c41
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7589
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-11-28 04:53:02 +01:00
Vladimir Serbinenko 8d70e94ae1 Make acpi_fill_dmar into parameter
Change-Id: I5e237cb7acbf47b2c8a4cd725ee8e16e422e3b17
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7371
Tested-by: build bot (Jenkins)
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-27 20:37:58 +01:00
Edward O'Callaghan 8be82e1017 southbridge/amd/agesa/hudson/pci.c: Use DEVICE_NOOP macro
Change-Id: I39edaaed67f45e7c56ec02c2aac2a4c5e1b63bc7
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7586
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-11-27 11:28:38 +01:00
Edward O'Callaghan 32960e30f0 mainboard/lenovo/g505s: New port Richland APU A10-5750M
Richland APU A10-5750M
8GB RAM
4MB Flash

Boots to working Linux with SeaBIOS payload. S3 works with
Linux 3.16.3-2 Debian Jessie.

Change-Id: I5d05d1b31400fdb9e41c2e011c5b0bf9986fe970
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/7560
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-11-27 11:28:24 +01:00
Edward O'Callaghan b06eaf76b5 vendorcode/amd/agesa: Use F15TN AGESA for F15RL
For the moment we make use of Trinity f15tn AGESA for Richland
f15rl support until we have properly worked out the discrepancies.

Adds RL-A1 Richland stepping cpuid to F15TnLogicalIdTables lookup.

We later wish to merge f15tn and f15rl support into the AGESA in
any case.

Change-Id: Ia9070d4e392ce7eb912771d1c7b3ef1440f8e8a8
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7559
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2014-11-27 11:28:05 +01:00
Edward O'Callaghan eaab6305be cpu/amd/agesa/family15rl: Provide Richland CPU support
Richland -
 Microarchitecture: Piledriver
 Core stepping:     RL-A1
 CPUID:             610F31

Change-Id: I790085fbf36d836c903dcce77d794abb8578712b
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7537
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-11-27 11:27:51 +01:00
Edward O'Callaghan 12bb8f97b6 northbridge/amd/agesa/family15rl: Provide Richland support
Provide our current development support for Richland. We
would however like to see a unification of 'northbridge/amd/agesa'
instead of another copy-paste merged.

Change-Id: I88005939844d1132cfd3531a9d47389320026814
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7536
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-11-27 11:27:45 +01:00
Vladimir Serbinenko d305aa6fc4 i945: Find memory controller by slot instead of by PCIID.
Slot is the same on all model but PCIID varies. Tested on AOA150.

Change-Id: I474548971ea140f25326a68fe8e86698a6725dea
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7569
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-11-26 23:19:34 +01:00
Vladimir Serbinenko 32d862b5d7 ibexpeak: Don't check for CONFIG_HAVE_SMI_HANDLER.
It's always true for this chipset.

Change-Id: Icd7666ed361c33170b1171da9ec46547685b996e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7571
Tested-by: build bot (Jenkins)
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-11-26 23:19:29 +01:00
Vladimir Serbinenko aec6c4755e sandy/ivy: Remove explicit setting of HAVE_SMI_HANDLER.
Southbridge already selects it, no need to repeat.

Change-Id: I9a5ad553f48e30103371cc2d896168ae4abfb8ef
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7570
Tested-by: build bot (Jenkins)
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-11-26 23:19:23 +01:00